From a20f39e847aad90fbdf71edcbb9145708b26a173 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 30 Oct 2021 12:56:31 +0200
Subject: [PATCH] update core definitions to include Zicsr and Zifencei (#276)

---
 gen_input/CoreDSL-Instruction-Set-Description | 2 +-
 gen_input/TGC_B.core_desc                     | 2 +-
 gen_input/TGC_C.core_desc                     | 2 +-
 gen_input/TGC_D.core_desc                     | 2 +-
 gen_input/TGC_D_XRB_MAC.core_desc             | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gen_input/CoreDSL-Instruction-Set-Description b/gen_input/CoreDSL-Instruction-Set-Description
index 9e3119a..e7aaec6 160000
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
@@ -1 +1 @@
-Subproject commit 9e3119a8064e8515eeca7e5298f88d0d9d224458
+Subproject commit e7aaec6ad9336bd83b4da63dd0c96f8d11887661
diff --git a/gen_input/TGC_B.core_desc b/gen_input/TGC_B.core_desc
index 78e86ec..3686002 100644
--- a/gen_input/TGC_B.core_desc
+++ b/gen_input/TGC_B.core_desc
@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_B provides RV32I {
+Core TGC_B provides RV32I, Zicsr, Zifencei {
 	architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper
diff --git a/gen_input/TGC_C.core_desc b/gen_input/TGC_C.core_desc
index a8fed39..d3a529e 100644
--- a/gen_input/TGC_C.core_desc
+++ b/gen_input/TGC_C.core_desc
@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_C provides RV32I, RV32M, RV32IC {
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper
diff --git a/gen_input/TGC_D.core_desc b/gen_input/TGC_D.core_desc
index 9616296..1187485 100644
--- a/gen_input/TGC_D.core_desc
+++ b/gen_input/TGC_D.core_desc
@@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
-Core TGC_D provides RV32I, RV32M, RV32IC {
+Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper
diff --git a/gen_input/TGC_D_XRB_MAC.core_desc b/gen_input/TGC_D_XRB_MAC.core_desc
index 9968d56..972b111 100644
--- a/gen_input/TGC_D_XRB_MAC.core_desc
+++ b/gen_input/TGC_D_XRB_MAC.core_desc
@@ -62,7 +62,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
   }
 }
 
-Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
+Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper