adds remaining register offsets
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@ -33,8 +33,7 @@
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def getRegisterSizes(){
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def regs = registers.collect{it.size}
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regs[-1]=64 // correct for NEXT_PC
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//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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regs += [32] // append LAST_BRANCH
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regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
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return regs
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}
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%>
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@ -37,8 +37,7 @@ def nativeTypeSize(int size){
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}
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def getRegisterSizes(){
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def regs = registers.collect{nativeTypeSize(it.size)}
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// regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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regs += [32] // append LAST_BRANCH
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regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
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return regs
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}
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def getRegisterOffsets(){
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@ -92,7 +91,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {
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${registers.collect{it.name}.join(', ')}, NUM_REGS, LAST_BRANCH=NUM_REGS
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${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
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};
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using reg_t = uint${addrDataWidth}_t;
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@ -163,6 +162,11 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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registers.each { reg -> if(reg.size>0) {%>
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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}}%>
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uint32_t trap_state = 0, pending_trap = 0;
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uint64_t icount = 0;
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uint64_t cycle = 0;
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uint64_t instret = 0;
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uint32_t instruction = 0;
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uint32_t last_branch = 0;
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} reg;
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#pragma pack(pop)
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