From ee2ded931d88a6ed91d1f8670c1f0b23259795de Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sun, 14 May 2023 17:16:42 +0200 Subject: [PATCH] adds remaining register offsets --- gen_input/templates/CORENAME.cpp.gtl | 3 +-- gen_input/templates/CORENAME.h.gtl | 10 +++++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/gen_input/templates/CORENAME.cpp.gtl b/gen_input/templates/CORENAME.cpp.gtl index 07ce7a3..3a06133 100644 --- a/gen_input/templates/CORENAME.cpp.gtl +++ b/gen_input/templates/CORENAME.cpp.gtl @@ -33,8 +33,7 @@ def getRegisterSizes(){ def regs = registers.collect{it.size} regs[-1]=64 // correct for NEXT_PC - //regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION - regs += [32] // append LAST_BRANCH + regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH return regs } %> diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 8f10609..563631f 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -37,8 +37,7 @@ def nativeTypeSize(int size){ } def getRegisterSizes(){ def regs = registers.collect{nativeTypeSize(it.size)} - // regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION - regs += [32] // append LAST_BRANCH + regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH return regs } def getRegisterOffsets(){ @@ -92,7 +91,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0}; enum reg_e { - ${registers.collect{it.name}.join(', ')}, NUM_REGS, LAST_BRANCH=NUM_REGS + ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH }; using reg_t = uint${addrDataWidth}_t; @@ -163,6 +162,11 @@ struct ${coreDef.name.toLowerCase()}: public arch_if { registers.each { reg -> if(reg.size>0) {%> uint${byteSize(reg.size)}_t ${reg.name} = 0;<% }}%> + uint32_t trap_state = 0, pending_trap = 0; + uint64_t icount = 0; + uint64_t cycle = 0; + uint64_t instret = 0; + uint32_t instruction = 0; uint32_t last_branch = 0; } reg; #pragma pack(pop)