DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fixes m/uintstatus read

This commit is contained in:
Eyck Jentzsch 2023-03-17 10:23:05 +01:00
parent 39b2788b7e
commit febbc4fff0
2 changed files with 20 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/iss/arch/riscv_hart_m_p.h
View File

@ -313,7 +313,7 @@ protected:
iss::status read_ip(unsigned addr, reg_t &val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status read_intstatus(unsigned addr, reg_t& val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_xtvt(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
@ -421,7 +421,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
csr_wr_cb[mtvt] = &this_class::write_xtvt;
// csr_rd_cb[mxnti] = &this_class::read_csr_reg;
// csr_wr_cb[mxnti] = &this_class::write_csr_reg;
csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
csr_rd_cb[mintstatus] = &this_class::read_intstatus;
csr_wr_cb[mintstatus] = &this_class::write_null;
// csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
// csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
@ -965,6 +965,12 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
val = (clic_mprev_lvl&0xff) <<24;
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;

15
src/iss/arch/riscv_hart_mu_p.h
View File

@ -330,7 +330,7 @@ protected:
iss::status write_edeleg(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status read_intstatus(unsigned addr, reg_t& val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_xtvt(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
@ -469,7 +469,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
csr_wr_cb[mtvt] = &this_class::write_xtvt;
// csr_rd_cb[mxnti] = &this_class::read_csr_reg;
// csr_wr_cb[mxnti] = &this_class::write_csr_reg;
csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
csr_rd_cb[mintstatus] = &this_class::read_intstatus;
csr_wr_cb[mintstatus] = &this_class::write_null;
// csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
// csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
@ -480,7 +480,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
if(FEAT & FEAT_EXT_N){
csr_rd_cb[utvt] = &this_class::read_csr_reg;
csr_wr_cb[utvt] = &this_class::write_xtvt;
csr_rd_cb[uintstatus] = &this_class::read_csr_reg;
csr_rd_cb[uintstatus] = &this_class::read_intstatus;
csr_wr_cb[uintstatus] = &this_class::write_null;
csr_rd_cb[uintthresh] = &this_class::read_csr_reg;
csr_wr_cb[uintthresh] = &this_class::write_intthresh;
@ -1158,6 +1158,15 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
auto mode = (addr >> 8) & 0x3;
val = clic_uprev_lvl&0xff;
if(mode==0x3)
val += (clic_mprev_lvl&0xff) <<24;
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;