From febbc4fff036a1c6da9896d6ab079817c938e5a3 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 17 Mar 2023 10:23:05 +0100 Subject: [PATCH] fixes m/uintstatus read --- src/iss/arch/riscv_hart_m_p.h | 10 ++++++++-- src/iss/arch/riscv_hart_mu_p.h | 15 ++++++++++++--- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 9273cab..0c766b5 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -313,7 +313,7 @@ protected: iss::status read_ip(unsigned addr, reg_t &val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); - iss::status write_intstatus(unsigned addr, reg_t val); + iss::status read_intstatus(unsigned addr, reg_t& val); iss::status write_intthresh(unsigned addr, reg_t val); iss::status write_xtvt(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val); @@ -421,7 +421,7 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) csr_wr_cb[mtvt] = &this_class::write_xtvt; // csr_rd_cb[mxnti] = &this_class::read_csr_reg; // csr_wr_cb[mxnti] = &this_class::write_csr_reg; - csr_rd_cb[mintstatus] = &this_class::read_csr_reg; + csr_rd_cb[mintstatus] = &this_class::read_intstatus; csr_wr_cb[mintstatus] = &this_class::write_null; // csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; // csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; @@ -965,6 +965,12 @@ template iss::status riscv_hart_m_p return iss::Ok; } +template +iss::status riscv_hart_m_p::read_intstatus(unsigned addr, reg_t& val) { + val = (clic_mprev_lvl&0xff) <<24; + return iss::Ok; +} + template iss::status riscv_hart_m_p::write_intthresh(unsigned addr, reg_t val) { csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 1459f7c..bb9684a 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -330,7 +330,7 @@ protected: iss::status write_edeleg(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); - iss::status write_intstatus(unsigned addr, reg_t val); + iss::status read_intstatus(unsigned addr, reg_t& val); iss::status write_intthresh(unsigned addr, reg_t val); iss::status write_xtvt(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val); @@ -469,7 +469,7 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr_wr_cb[mtvt] = &this_class::write_xtvt; // csr_rd_cb[mxnti] = &this_class::read_csr_reg; // csr_wr_cb[mxnti] = &this_class::write_csr_reg; - csr_rd_cb[mintstatus] = &this_class::read_csr_reg; + csr_rd_cb[mintstatus] = &this_class::read_intstatus; csr_wr_cb[mintstatus] = &this_class::write_null; // csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; // csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; @@ -480,7 +480,7 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) if(FEAT & FEAT_EXT_N){ csr_rd_cb[utvt] = &this_class::read_csr_reg; csr_wr_cb[utvt] = &this_class::write_xtvt; - csr_rd_cb[uintstatus] = &this_class::read_csr_reg; + csr_rd_cb[uintstatus] = &this_class::read_intstatus; csr_wr_cb[uintstatus] = &this_class::write_null; csr_rd_cb[uintthresh] = &this_class::read_csr_reg; csr_wr_cb[uintthresh] = &this_class::write_intthresh; @@ -1158,6 +1158,15 @@ template iss::status riscv_hart_mu_p +iss::status riscv_hart_mu_p::read_intstatus(unsigned addr, reg_t& val) { + auto mode = (addr >> 8) & 0x3; + val = clic_uprev_lvl&0xff; + if(mode==0x3) + val += (clic_mprev_lvl&0xff) <<24; + return iss::Ok; +} + template iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;