fix else-ambiguity in CoreDSL description

2022-01-31 20:06:12 +01:00 · 2022-01-31 20:06:12 +01:00 · afe8905ac9
parent ecc6091d1e
commit afe8905ac9
3 changed files with 403 additions and 484 deletions
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
@ -1 +0,0 @@
-Subproject commit b005607fc30c4467683b6044eaca7eb378061b53
--- a/incl/iss/arch/tgc_c.h
+++ b/incl/iss/arch/tgc_c.h
@ -217,7 +217,7 @@ struct tgc_c: public arch_if {

    inline uint32_t get_last_branch() { return reg.last_branch; }

-protected:
+
 #pragma pack(push, 1)
    struct TGC_C_regs { 
        uint32_t X0 = 0; 
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
				`@ -1 +0,0 @@`
				`Subproject commit b005607fc30c4467683b6044eaca7eb378061b53`