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DBT-RISE-TGC
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changes templates for correct plugin callback in case of trap

This commit is contained in:
Eyck-Alexander Jentzsch 2023-09-23 10:35:21 +02:00
parent 8db0cc5d05
commit 70839bbbf2
2 changed files with 16 additions and 12 deletions
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2
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -305,6 +305,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
}
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry_plugin:");
this->gen_sync(tu, POST_SYNC, -1);
tu("trap_entry:");
tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));

26
src/vm/tcc/vm_tgc5c.cpp
View File

@ -462,12 +462,11 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
auto new_pc = tu.assignment(tu.ext((tu.bitwise_and(
(tu.add(
tu.load(rs1+ traits::X0, 0),
tu.constant((int16_t)sext<12>(imm),16))),
addr_mask)),32,false),32);
tu.constant(~ 0x1,8))),32,false),32);
tu.open_if(tu.urem(
new_pc,
tu.constant(static_cast<uint32_t>(traits:: INSTR_ALIGNMENT),32)));
@ -477,7 +476,9 @@ private:
tu.store(rd + traits::X0,
tu.constant((uint32_t)(PC+ 4),32));
}
auto PC_val_v = tu.assignment("PC_val", new_pc,32);
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
new_pc,
tu.constant(~ 0x1,8)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
tu.close_scope();
@ -2472,7 +2473,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs2+ traits::X0, 0),
tu.constant( 0,8)));
auto MMIN = tu.assignment(tu.constant((uint32_t)1<<(static_cast<uint32_t>(traits:: XLEN)-1),32),32);
auto MMIN = tu.assignment(tu.constant( 1<<(static_cast<uint32_t>(traits:: XLEN)-1),8),32);
tu.open_if(tu.logical_and(
tu.icmp(ICmpInst::ICMP_EQ,
tu.load(rs1+ traits::X0, 0),
@ -3303,12 +3304,12 @@ private:
pc=pc+ 2;
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)){ auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),
addr_mask),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)) {
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),
tu.constant(~ 0x1,8)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}
else{
this->gen_raise_trap(tu, 0, 2);
@ -3401,13 +3402,12 @@ private:
this->gen_raise_trap(tu, 0, 2);
}
else{
auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
tu.store(1 + traits::X0,
tu.constant((uint32_t)(PC+ 2),32));
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
new_pc,
addr_mask),32);
tu.constant(~ 0x1,8)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}
@ -3626,6 +3626,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
}
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry_plugin:");
this->gen_sync(tu, POST_SYNC, -1);
tu("trap_entry:");
tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));