DBT-RISE
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DBT-RISE-TGC
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cleans vm implementation up

This commit is contained in:
Eyck Jentzsch 2023-07-09 20:13:26 +02:00
parent 250ea3c980
commit e95f422aab
4 changed files with 5 additions and 24 deletions
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7
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -320,7 +320,7 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
@ -336,8 +336,3 @@ std::array<bool, 2> dummy = {
};
}
}
extern "C" {
bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
return iss::dummy.data();
}
}

7
gen_input/templates/tcc/CORENAME.cpp.gtl
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@ -317,7 +317,7 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
@ -333,8 +333,3 @@ std::array<bool, 2> dummy = {
};
}
}
extern "C" {
bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
return iss::dummy.data();
}
}

8
src/vm/interp/vm_tgc_c.cpp
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@ -2651,7 +2651,7 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
@ -2667,8 +2667,4 @@ std::array<bool, 2> dummy = {
};
}
}
extern "C" {
bool* get_tgc_c_interp_creators() {
return iss::dummy.data();
}
}

7
src/vm/tcc/vm_tgc_c.cpp
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@ -3226,7 +3226,7 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
#include <iss/arch/riscv_hart_mu_p.h>
namespace iss {
namespace {
std::array<bool, 2> dummy = {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
@ -3242,8 +3242,3 @@ std::array<bool, 2> dummy = {
};
}
}
extern "C" {
bool* get_tgc_c_tcc_creators() {
return iss::dummy.data();
}
}