DBT-RISE/DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

renames core(s)

Browse Source
This commit is contained in:
Eyck Jentzsch 2023-08-27 15:17:12 +02:00
parent 0b719a4b57
commit c8a4a4c736
11 changed files with 100 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
CMakeLists.txt
View File

@ -31,13 +31,13 @@ add_subdirectory(softfloat)
set(LIB_SOURCES
src/iss/plugin/instruction_count.cpp
src/iss/arch/tgc_c.cpp
src/vm/tcc/vm_tgc_c.cpp
src/vm/interp/vm_tgc_c.cpp
src/iss/arch/tgc5c.cpp
src/vm/tcc/vm_tgc5c.cpp
src/vm/interp/vm_tgc5c.cpp
src/vm/fp_functions.cpp
)
if(WITH_TCC)
list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc_c.cpp)
list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc5c.cpp)
endif()
# library files

4
gen_input/TGC_C.core_desc
View File

@ -1,8 +1,8 @@
import "ISA/RV32I.core_desc"
import "ISA/RVI.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper

24
src/iss/arch/tgc_c.cpp → src/iss/arch/tgc5c.cpp
View File

@ -30,7 +30,7 @@
*
*******************************************************************************/
#include "tgc_c.h"
#include "tgc5c.h"
#include "util/ities.h"
#include <util/logging.h>
#include <cstdio>
@ -39,18 +39,18 @@
using namespace iss::arch;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_names;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
tgc_c::tgc_c() = default;
tgc5c::tgc5c() = default;
tgc_c::~tgc_c() = default;
tgc5c::~tgc5c() = default;
void tgc_c::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
void tgc5c::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
*(base_ptr+i)=0;
reg.PC=address;
reg.NEXT_PC=reg.PC;
@ -59,11 +59,11 @@ void tgc_c::reset(uint64_t address) {
reg.icount=0;
}
uint8_t *tgc_c::get_regs_base_ptr() {
uint8_t *tgc5c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

32
src/iss/arch/tgc_c.h → src/iss/arch/tgc5c.h
View File

@ -30,8 +30,8 @@
*
*******************************************************************************/
#ifndef _TGC_C_H_
#define _TGC_C_H_
#ifndef _TGC5C_H_
#define _TGC5C_H_
#include <array>
#include <iss/arch/traits.h>
@ -41,11 +41,11 @@
namespace iss {
namespace arch {
struct tgc_c;
struct tgc5c;
template <> struct traits<tgc_c> {
template <> struct traits<tgc5c> {
constexpr static char const* const core_type = "TGC_C";
constexpr static char const* const core_type = "TGC5C";
static constexpr std::array<const char*, 36> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
@ -175,15 +175,15 @@ template <> struct traits<tgc_c> {
};
};
struct tgc_c: public arch_if {
struct tgc5c: public arch_if {
using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
using reg_t = typename traits<tgc_c>::reg_t;
using addr_t = typename traits<tgc_c>::addr_t;
using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
using reg_t = typename traits<tgc5c>::reg_t;
using addr_t = typename traits<tgc5c>::addr_t;
tgc_c();
~tgc_c();
tgc5c();
~tgc5c();
void reset(uint64_t address=0) override;
@ -196,9 +196,9 @@ struct tgc_c: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
if (addr.space != traits<tgc5c>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
} else
return virt2phys(addr);
}
@ -211,7 +211,7 @@ struct tgc_c: public arch_if {
#pragma pack(push, 1)
struct TGC_C_regs {
struct TGC5C_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
@ -267,4 +267,4 @@ struct tgc_c: public arch_if {
}
}
#endif /* _TGC_C_H_ */
#endif /* _TGC5C_H_ */

52
src/iss/arch/tgc_mapper.h
View File

@ -2,49 +2,49 @@
#define _ISS_ARCH_TGC_MAPPER_H
#include "riscv_hart_m_p.h"
#include "tgc_c.h"
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#ifdef CORE_TGC_A
#include "tgc5c.h"
using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
#ifdef CORE_TGC5A
#include "riscv_hart_m_p.h"
#include <iss/arch/tgc_a.h>
using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
#include <iss/arch/tgc5a.h>
using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
#endif
#ifdef CORE_TGC_B
#ifdef CORE_TGC5B
#include "riscv_hart_m_p.h"
#include <iss/arch/tgc_b.h>
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#include <iss/arch/tgc5b.h>
using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
#endif
#ifdef CORE_TGC_C_XRB_NN
#ifdef CORE_TGC5C_XRB_NN
#include "riscv_hart_m_p.h"
#include "hwl.h"
#include <iss/arch/tgc_c_xrb_nn.h>
using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
#include <iss/arch/tgc5c_xrb_nn.h>
using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
#endif
#ifdef CORE_TGC_D
#ifdef CORE_TGC5D
#include "riscv_hart_mu_p.h"
#include <iss/arch/tgc_d.h>
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#include <iss/arch/tgc5d.h>
using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_D_XRB_MAC
#ifdef CORE_TGC5D_XRB_MAC
#include "riscv_hart_mu_p.h"
#include <iss/arch/tgc_d_xrb_mac.h>
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#include <iss/arch/tgc5d_xrb_mac.h>
using tgc5d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_D_XRB_NN
#ifdef CORE_TGC5D_XRB_NN
#include "riscv_hart_mu_p.h"
#include "hwl.h"
#include <iss/arch/tgc_d_xrb_nn.h>
using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
#include <iss/arch/tgc5d_xrb_nn.h>
using tgc5d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
#endif
#ifdef CORE_TGC_E
#ifdef CORE_TGC5E
#include "riscv_hart_mu_p.h"
#include <iss/arch/tgc_e.h>
using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#include <iss/arch/tgc5e.h>
using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_X
#ifdef CORE_TGC5X
#include "riscv_hart_mu_p.h"
#include <iss/arch/tgc_x.h>
using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
#include <iss/arch/tgc5x.h>
using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
#endif
#endif

2
src/sysc/core_complex.cpp
View File

@ -145,7 +145,7 @@ public:
std::tie(cpu, vm) = f.create(type+"|"+backend);
} else {
auto base_isa = type.substr(0, 5);
if(base_isa=="tgc_d" || base_isa=="tgc_e") {
if(base_isa=="tgc5d" || base_isa=="tgc5e") {
std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
} else {
std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port);

6
src/sysc/core_complex.h
View File

@ -96,7 +96,7 @@ public:
cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
cci::cci_param<std::string> backend{"backend", "interp"};
@ -121,7 +121,7 @@ public:
scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
scml_property<std::string> core_type{"core_type", "tgc_c"};
scml_property<std::string> core_type{"core_type", "tgc5c"};
scml_property<std::string> backend{"backend", "interp"};
@ -139,7 +139,7 @@ public:
, elf_file{"elf_file", ""}
, enable_disass{"enable_disass", false}
, reset_address{"reset_address", 0ULL}
, core_type{"core_type", "tgc_c"}
, core_type{"core_type", "tgc5c"}
, backend{"backend", "interp"}
, gdb_server_port{"gdb_server_port", 0}
, dump_ir{"dump_ir", false}

18
src/sysc/register_tgc_c.cpp
View File

@ -31,7 +31,7 @@
*******************************************************************************/
#include <iss/factory.h>
#include <iss/arch/tgc_c.h>
#include <iss/arch/tgc5c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/riscv_hart_mu_p.h>
#include "sc_core_adapter.h"
@ -40,14 +40,14 @@
namespace iss {
namespace interp {
volatile std::array<bool, 2> tgc_init = {
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
})
};
@ -55,14 +55,14 @@ volatile std::array<bool, 2> tgc_init = {
#if defined(WITH_TCC)
namespace tcc {
volatile std::array<bool, 2> tgc_init = {
core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
})
};

22
src/vm/interp/vm_tgc_c.cpp → src/vm/interp/vm_tgc5c.cpp
View File

@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgc_c.h>
#include <iss/arch/tgc5c.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace tgc_c {
namespace tgc5c {
using namespace iss::arch;
using namespace iss::debugger;
using namespace std::placeholders;
@ -2635,11 +2635,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
return pc;
}
} // namespace tgc_c
} // namespace tgc5c
template <>
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
@ -2652,15 +2652,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})

10
src/vm/llvm/vm_tgc_c.cpp → src/vm/llvm/vm_tgc5c.cpp
View File

@ -30,8 +30,8 @@
*
*******************************************************************************/
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/tgc5c.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -52,7 +52,7 @@ namespace fp_impl {
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace tgc_c {
namespace tgc5c {
using namespace ::llvm;
using namespace iss::arch;
using namespace iss::debugger;
@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
bb, this->trap_blk, 1);
}
} // namespace tgc_c
} // namespace tgc5c
template <>
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

22
src/vm/tcc/vm_tgc_c.cpp → src/vm/tcc/vm_tgc5c.cpp
View File

@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgc_c.h>
#include <iss/arch/tgc5c.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -48,7 +48,7 @@
namespace iss {
namespace tcc {
namespace tgc_c {
namespace tgc5c {
using namespace iss::arch;
using namespace iss::debugger;
@ -3210,11 +3210,11 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("return *next_pc;");
}
} // namespace tgc_c
} // namespace tgc5c
template <>
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
@ -3227,15 +3227,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
namespace iss {
namespace {
volatile std::array<bool, 2> dummy = {
core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
}),
core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
return {cpu_ptr{cpu}, vm_ptr{vm}};
})