DBT-RISE/DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity
MINRES The Good Folks Series cores ISS
264 Commits 10 Branches 0 Tags 4.3 MiB
C 54.4%
C++ 39.1%
Makefile 3%
HTML 2.6%
CMake 0.7%
Other 0.2%
bfa8166223
Go to file
Eyck Jentzsch bfa8166223 fix wrong template class name
2021-11-08 10:44:33 +01:00
.settings Adapted generated code to support translation block linking 2018-05-15 18:50:11 +02:00
contrib add install target and PA compatibility 2021-08-16 17:02:31 +02:00
gen_input fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
incl fix wrong template class name 2021-11-08 10:44:33 +01:00
softfloat add MSVC 16 compatibility 2021-10-10 19:06:41 +02:00
src fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
.clang-format Added clang-format formatting 2017-09-25 22:29:21 +02:00
.cproject reorganized layout to only contain risc-v stuff 2019-06-11 16:49:37 +00:00
.gitignore update .gitignore 2021-10-01 13:06:10 +02:00
.gitmodules Relative path to a submodule 2020-12-10 15:32:03 +01:00
.project Updated Eclipse project name 2018-04-09 20:05:18 +02:00
CMakeLists.txt get rid of the Boost::thread linking 2021-11-02 10:24:34 +01:00
LICENSE Initial commit 2017-08-27 13:04:48 +02:00
README.md Update TGF naming convention 2020-09-11 10:45:44 +02:00

README.md

DBT-RISE-TGFS

Core of an instruction set simulator based on DBT-RISE implementing Minres The Good Folks Series cores. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-TGFS .

This repo contains only the code of the RISC-V ISS and can only be used with the DBT_RISE. A complete VP using this ISS can be found at https://git.minres.com/VP/Ecosystem-VP which models SiFives FE310 controlling a brushless DC (BLDC) motor.

This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':

  • RV32I (TGF-B)
  • RV32MIC (TGF-C)

All pass the respective compliance tests. Along with those ISA implementations there is a wrapper (riscv_hart_m_p.h) implementing the Machine privileged mode as of privileged spec 1.10. The main.cpp in src allows to build a stand-alone ISS when integrated into a top-level project. For further information please have a look at https://git.minres.com/VP/RISCV-VP.

Last but not least an SystemC wrapper is provided which allows easy integration into SystemC based virtual platforms.

Since DBT-RISE uses a generative approach other needed combinations or custom extension can be generated. For further information please contact info@minres.com.