DBT-RISE
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DBT-RISE-TGC
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Update TGF naming convention

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hotfix/latest_scc
Stanislaw Kaushanski 3 years ago
parent f3d578f050
commit 43488676dd
15 changed files with 102 additions and 102 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 16
      CMakeLists.txt
  2. 4
      README.md
  3. 4
      gen_input/TGFS.core_desc
  4. 32
      incl/iss/arch/tgf_b.h
  5. 32
      incl/iss/arch/tgf_c.h
  6. 22
      src/iss/tgf_b.cpp
  7. 22
      src/iss/tgf_c.cpp
  8. 16
      src/main.cpp
  9. 4
      src/sysc/core_complex.cpp
  10. 8
      src/vm/interp/vm_tgf_b.cpp
  11. 8
      src/vm/interp/vm_tgf_c.cpp
  12. 10
      src/vm/llvm/vm_tgf_b.cpp
  13. 10
      src/vm/llvm/vm_tgf_c.cpp
  14. 8
      src/vm/tcc/vm_tgf_b.cpp
  15. 8
      src/vm/tcc/vm_tgf_c.cpp

16
CMakeLists.txt
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@ -30,21 +30,21 @@ add_subdirectory(softfloat)
FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
set(LIB_HEADERS ${RiscVSCHeaders} )
set(LIB_SOURCES
src/iss/tgf01.cpp
src/iss/tgf02.cpp
src/iss/tgf_b.cpp
src/iss/tgf_c.cpp
src/vm/fp_functions.cpp
src/vm/tcc/vm_tgf01.cpp
src/vm/tcc/vm_tgf02.cpp
src/vm/interp/vm_tgf01.cpp
src/vm/interp/vm_tgf02.cpp
src/vm/tcc/vm_tgf_b.cpp
src/vm/tcc/vm_tgf_c.cpp
src/vm/interp/vm_tgf_b.cpp
src/vm/interp/vm_tgf_c.cpp
src/plugin/instruction_count.cpp
src/plugin/cycle_estimate.cpp
)
if(WITH_LLVM)
set(LIB_SOURCES ${LIB_SOURCES}
src/vm/llvm/fp_impl.cpp
src/vm/llvm/vm_tgf01.cpp
src/vm/llvm/vm_tgf02.cpp
src/vm/llvm/vm_tgf_b.cpp
src/vm/llvm/vm_tgf_c.cpp
)
endif()

4
README.md
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@ -5,8 +5,8 @@ This repo contains only the code of the RISC-V ISS and can only be used with the
This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':
* RV32I (TGF01)
* RV32MIC (TGF02)
* RV32I (TGF-B)
* RV32MIC (TGF-C)
All pass the respective compliance tests. Along with those ISA implementations there is a wrapper (riscv_hart_m_p.h) implementing the Machine privileged mode as of privileged spec 1.10. The main.cpp in src allows to build a stand-alone ISS when integrated into a top-level project. For further information please have a look at [https://git.minres.com/VP/RISCV-VP](https://git.minres.com/VP/RISCV-VP).

4
gen_input/TGFS.core_desc
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGF01 provides RV32I {
Core TGF_B provides RV32I {
constants {
XLEN:=32;
PCLEN:=32;
@ -14,7 +14,7 @@ Core TGF01 provides RV32I {
}
}
Core TGF02 provides RV32I, RV32M, RV32IC {
Core TGF_C provides RV32I, RV32M, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;

32
incl/iss/arch/tgf01.h → incl/iss/arch/tgf_b.h
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@ -31,8 +31,8 @@
*******************************************************************************/
#ifndef _TGF01_H_
#define _TGF01_H_
#ifndef _TGF_B_H_
#define _TGF_B_H_
#include <array>
#include <iss/arch/traits.h>
@ -42,11 +42,11 @@
namespace iss {
namespace arch {
struct tgf01;
struct tgf_b;
template <> struct traits<tgf01> {
template <> struct traits<tgf_b> {
constexpr static char const* const core_type = "TGF01";
constexpr static char const* const core_type = "TGF_B";
static constexpr std::array<const char*, 33> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
@ -156,15 +156,15 @@ template <> struct traits<tgf01> {
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct tgf01: public arch_if {
struct tgf_b: public arch_if {
using virt_addr_t = typename traits<tgf01>::virt_addr_t;
using phys_addr_t = typename traits<tgf01>::phys_addr_t;
using reg_t = typename traits<tgf01>::reg_t;
using addr_t = typename traits<tgf01>::addr_t;
using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
using reg_t = typename traits<tgf_b>::reg_t;
using addr_t = typename traits<tgf_b>::addr_t;
tgf01();
~tgf01();
tgf_b();
~tgf_b();
void reset(uint64_t address=0) override;
@ -185,9 +185,9 @@ struct tgf01: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<tgf01>::MEM || addr.type == iss::address_type::PHYSICAL ||
if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf01>::addr_mask);
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
} else
return virt2phys(addr);
}
@ -199,7 +199,7 @@ struct tgf01: public arch_if {
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct TGF01_regs {
struct TGF_B_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
@ -249,4 +249,4 @@ protected:
}
}
#endif /* _TGF01_H_ */
#endif /* _TGF_B_H_ */

32
incl/iss/arch/tgf02.h → incl/iss/arch/tgf_c.h
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@ -31,8 +31,8 @@
*******************************************************************************/
#ifndef _TGF02_H_
#define _TGF02_H_
#ifndef _TGF_C_H_
#define _TGF_C_H_
#include <array>
#include <iss/arch/traits.h>
@ -42,11 +42,11 @@
namespace iss {
namespace arch {
struct tgf02;
struct tgf_c;
template <> struct traits<tgf02> {
template <> struct traits<tgf_c> {
constexpr static char const* const core_type = "TGF02";
constexpr static char const* const core_type = "TGF_C";
static constexpr std::array<const char*, 33> reg_names{
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
@ -156,15 +156,15 @@ template <> struct traits<tgf02> {
enum mem_type_e { MEM, CSR, FENCE, RES };
};
struct tgf02: public arch_if {
struct tgf_c: public arch_if {
using virt_addr_t = typename traits<tgf02>::virt_addr_t;
using phys_addr_t = typename traits<tgf02>::phys_addr_t;
using reg_t = typename traits<tgf02>::reg_t;
using addr_t = typename traits<tgf02>::addr_t;
using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
using reg_t = typename traits<tgf_c>::reg_t;
using addr_t = typename traits<tgf_c>::addr_t;
tgf02();
~tgf02();
tgf_c();
~tgf_c();
void reset(uint64_t address=0) override;
@ -185,9 +185,9 @@ struct tgf02: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<tgf02>::MEM || addr.type == iss::address_type::PHYSICAL ||
if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf02>::addr_mask);
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
} else
return virt2phys(addr);
}
@ -199,7 +199,7 @@ struct tgf02: public arch_if {
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
struct TGF02_regs {
struct TGF_C_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
@ -249,4 +249,4 @@ protected:
}
}
#endif /* _TGF02_H_ */
#endif /* _TGF_C_H_ */

22
src/iss/tgf01.cpp → src/iss/tgf_b.cpp
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@ -32,26 +32,26 @@
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/tgf01.h>
#include <iss/arch/tgf_b.h>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf01>::reg_names;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf01>::reg_aliases;
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf01>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf01>::reg_byte_offsets;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_names;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
tgf01::tgf01() {
tgf_b::tgf_b() {
reg.icount = 0;
}
tgf01::~tgf01() = default;
tgf_b::~tgf_b() = default;
void tgf01::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf01>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf01>::reg_t),0));
void tgf_b::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf_b>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_b>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
@ -59,11 +59,11 @@ void tgf01::reset(uint64_t address) {
reg.icount=0;
}
uint8_t *tgf01::get_regs_base_ptr() {
uint8_t *tgf_b::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
tgf01::phys_addr_t tgf01::virt2phys(const iss::addr_t &pc) {
tgf_b::phys_addr_t tgf_b::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

22
src/iss/tgf02.cpp → src/iss/tgf_c.cpp
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@ -32,26 +32,26 @@
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/tgf02.h>
#include <iss/arch/tgf_c.h>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf02>::reg_names;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf02>::reg_aliases;
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf02>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf02>::reg_byte_offsets;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_names;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
tgf02::tgf02() {
tgf_c::tgf_c() {
reg.icount = 0;
}
tgf02::~tgf02() = default;
tgf_c::~tgf_c() = default;
void tgf02::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf02>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf02>::reg_t),0));
void tgf_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
@ -59,11 +59,11 @@ void tgf02::reset(uint64_t address) {
reg.icount=0;
}
uint8_t *tgf02::get_regs_base_ptr() {
uint8_t *tgf_c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
tgf02::phys_addr_t tgf02::virt2phys(const iss::addr_t &pc) {
tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

16
src/main.cpp
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@ -36,8 +36,8 @@
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/arch/tgf01.h>
#include <iss/arch/tgf02.h>
#include <iss/arch/tgf_b.h>
#include <iss/arch/tgf_c.h>
#ifdef WITH_LLVM
#include <iss/llvm/jit_helper.h>
#endif
@ -84,7 +84,7 @@ int main(int argc, char *argv[]) {
("mem,m", po::value<std::string>(), "the memory input file")
("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
("isa", po::value<std::string>()->default_value("tgf02"), "isa to use for simulation");
("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
// clang-format on
auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
try {
@ -129,12 +129,12 @@ int main(int argc, char *argv[]) {
vm_ptr vm{nullptr};
cpu_ptr cpu{nullptr};
std::string isa_opt(clim["isa"].as<std::string>());
if (isa_opt == "tgf01") {
if (isa_opt == "tgf_b") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf01>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else if (isa_opt == "tgf02") {
create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else if (isa_opt == "tgf_c") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf02>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else {
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
return 127;
@ -174,7 +174,7 @@ int main(int argc, char *argv[]) {
}
uint64_t start_address = 0;
if (clim.count("mem"))
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf01>::MEM);
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_b>::MEM);
if (clim.count("elf"))
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
auto start_addr = vm->get_arch()->load_file(input);

4
src/sysc/core_complex.cpp
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@ -32,7 +32,7 @@
#include "sysc/core_complex.h"
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgf02.h"
#include "iss/arch/tgf_c.h"
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/server.h"
@ -59,7 +59,7 @@ namespace {
iss::debugger::encoder_decoder encdec;
}
using core_type = iss::arch::tgf02;
using core_type = iss::arch::tgf_c;
namespace {

8
src/vm/interp/vm_tgf01.cpp → src/vm/interp/vm_tgf_b.cpp
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@ -31,7 +31,7 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/tgf01.h>
#include <iss/arch/tgf_b.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace tgf01 {
namespace tgf_b {
using namespace iss::arch;
using namespace iss::debugger;
@ -2063,8 +2063,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t star
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf01>(arch::tgf01 *core, unsigned short port, bool dump) {
auto ret = new tgf01::vm_impl<arch::tgf01>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_b>(arch::tgf_b *core, unsigned short port, bool dump) {
auto ret = new tgf_b::vm_impl<arch::tgf_b>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

8
src/vm/interp/vm_tgf02.cpp → src/vm/interp/vm_tgf_c.cpp
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@ -31,7 +31,7 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/tgf02.h>
#include <iss/arch/tgf_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace tgf02 {
namespace tgf_c {
using namespace iss::arch;
using namespace iss::debugger;
@ -3314,8 +3314,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t star
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf02>(arch::tgf02 *core, unsigned short port, bool dump) {
auto ret = new tgf02::vm_impl<arch::tgf02>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

10
src/vm/llvm/vm_tgf01.cpp → src/vm/llvm/vm_tgf_b.cpp
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@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgf01.h>
#include <iss/arch/tgf_b.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -52,7 +52,7 @@ namespace fp_impl {
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace tgf01 {
namespace tgf_b {
using namespace ::llvm;
using namespace iss::arch;
using namespace iss::debugger;
@ -2570,11 +2570,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
bb, this->trap_blk, 1);
}
} // namespace tgf01
} // namespace tgf_b
template <>
std::unique_ptr<vm_if> create<arch::tgf01>(arch::tgf01 *core, unsigned short port, bool dump) {
auto ret = new tgf01::vm_impl<arch::tgf01>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_b>(arch::tgf_b *core, unsigned short port, bool dump) {
auto ret = new tgf_b::vm_impl<arch::tgf_b>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

10
src/vm/llvm/vm_tgf02.cpp → src/vm/llvm/vm_tgf_c.cpp
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@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgf02.h>
#include <iss/arch/tgf_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -52,7 +52,7 @@ namespace fp_impl {
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace tgf02 {
namespace tgf_c {
using namespace ::llvm;
using namespace iss::arch;
using namespace iss::debugger;
@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
bb, this->trap_blk, 1);
}
} // namespace tgf02
} // namespace tgf_c
template <>
std::unique_ptr<vm_if> create<arch::tgf02>(arch::tgf02 *core, unsigned short port, bool dump) {
auto ret = new tgf02::vm_impl<arch::tgf02>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

8
src/vm/tcc/vm_tgf01.cpp → src/vm/tcc/vm_tgf_b.cpp
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@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgf01.h>
#include <iss/arch/tgf_b.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -49,7 +49,7 @@
namespace iss {
namespace tcc {
namespace tgf01 {
namespace tgf_b {
using namespace iss::arch;
using namespace iss::debugger;
@ -2077,8 +2077,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf01>(arch::tgf01 *core, unsigned short port, bool dump) {
auto ret = new tgf01::vm_impl<arch::tgf01>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_b>(arch::tgf_b *core, unsigned short port, bool dump) {
auto ret = new tgf_b::vm_impl<arch::tgf_b>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

8
src/vm/tcc/vm_tgf02.cpp → src/vm/tcc/vm_tgf_c.cpp
Unescape View File

@ -30,7 +30,7 @@
*
*******************************************************************************/
#include <iss/arch/tgf02.h>
#include <iss/arch/tgf_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -49,7 +49,7 @@
namespace iss {
namespace tcc {
namespace tgf02 {
namespace tgf_c {
using namespace iss::arch;
using namespace iss::debugger;
@ -3269,8 +3269,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf02>(arch::tgf02 *core, unsigned short port, bool dump) {
auto ret = new tgf02::vm_impl<arch::tgf02>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
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