adds changes from latest CoreDSL description
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98dd329833
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a8a2782329
@ -1727,11 +1727,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
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*(X+rd % traits::RFS) = (uint32_t)res;
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
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if(rd != 0) {
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*(X+rd) = (uint32_t)res;
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}
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}
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}
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TRAP_MUL:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::MULH: {
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@ -1750,11 +1755,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (int64_t)(int32_t)*(X+rs2 % traits::RFS);
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*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
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if(rd != 0) {
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*(X+rd) = (uint32_t)(res >> traits::XLEN);
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}
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}
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}
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TRAP_MULH:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::MULHSU: {
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@ -1773,11 +1783,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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int64_t res = (int64_t)(int32_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
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*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
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if(rd != 0) {
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*(X+rd) = (uint32_t)(res >> traits::XLEN);
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}
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}
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}
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TRAP_MULHSU:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::MULHU: {
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@ -1796,11 +1811,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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uint64_t res = (uint64_t)*(X+rs1 % traits::RFS) * (uint64_t)*(X+rs2 % traits::RFS);
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*(X+rd % traits::RFS) = (uint32_t)(res >> traits::XLEN);
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
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if(rd != 0) {
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*(X+rd) = (uint32_t)(res >> traits::XLEN);
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}
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}
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}
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TRAP_MULHU:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::DIV: {
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@ -1819,21 +1839,28 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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if(*(X+rs2 % traits::RFS) != 0) {
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uint32_t MMIN = 1 << (traits::XLEN - 1);
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if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) {
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*(X+rd % traits::RFS) = MMIN;
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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int32_t dividend = (int32_t)*(X+rs1);
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int32_t divisor = (int32_t)*(X+rs2);
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if(rd != 0) {
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if(divisor != 0) {
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uint32_t MMIN = ((uint32_t)1) << (traits::XLEN - 1);
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if(*(X+rs1) == MMIN && divisor == - 1) {
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*(X+rd) = MMIN;
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}
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else {
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*(X+rd) = dividend / divisor;
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}
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}
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else {
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*(X+rd) = (int32_t)- 1;
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}
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}
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}
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}
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else {
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*(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) / (int32_t)*(X+rs2 % traits::RFS);
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}
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}
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else {
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*(X+rd % traits::RFS) = - 1;
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}
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}
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}
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TRAP_DIV:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::DIVU: {
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@ -1852,15 +1879,22 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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if(*(X+rs2 % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) / *(X+rs2 % traits::RFS);
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}
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else {
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*(X+rd % traits::RFS) = - 1;
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}
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(*(X+rs2) != 0) {
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if(rd != 0) {
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*(X+rd) = *(X+rs1) / *(X+rs2);
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}
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)- 1;
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}
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}
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}
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}
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TRAP_DIVU:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::REM: {
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@ -1879,21 +1913,30 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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if(*(X+rs2 % traits::RFS) != 0) {
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uint32_t MMIN = 1 << (traits::XLEN - 1);
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if(*(X+rs1 % traits::RFS) == MMIN && (int32_t)*(X+rs2 % traits::RFS) == - 1) {
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*(X+rd % traits::RFS) = 0;
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(*(X+rs2) != 0) {
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uint32_t MMIN = 1 << (traits::XLEN - 1);
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if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) {
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if(rd != 0) {
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*(X+rd) = 0;
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}
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
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}
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}
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1);
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}
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}
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}
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}
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else {
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*(X+rd % traits::RFS) = (int32_t)*(X+rs1 % traits::RFS) % (int32_t)*(X+rs2 % traits::RFS);
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}
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}
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else {
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*(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
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}
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}
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}
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TRAP_REM:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::REMU: {
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@ -1912,15 +1955,22 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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if(*(X+rs2 % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = *(X+rs1 % traits::RFS) % *(X+rs2 % traits::RFS);
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}
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else {
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*(X+rd % traits::RFS) = *(X+rs1 % traits::RFS);
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}
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}
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}
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if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(*(X+rs2) != 0) {
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if(rd != 0) {
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*(X+rd) = *(X+rs1) % *(X+rs2);
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}
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs1);
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}
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}
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}
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}
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TRAP_REMU:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::CADDI4SPN: {
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@ -2007,8 +2057,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if((rs1 % traits::RFS) != 0) {
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*(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) + (int8_t)sext<6>(imm);
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if(rs1 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rs1 != 0) {
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*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
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}
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}
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}
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TRAP_CADDI:break;
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@ -2061,10 +2116,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (int8_t)sext<6>(imm);
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}
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}
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if(rd >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (int8_t)sext<6>(imm);
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}
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}
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}
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TRAP_CLI:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::CLUI: {
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@ -2082,11 +2142,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if(imm == 0) {
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if(imm == 0 || rd >= traits::RFS) {
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raise(0, 2);
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}
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = (int32_t)sext<18>(imm);
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if(rd != 0) {
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*(X+rd) = (int32_t)sext<18>(imm);
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}
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}
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TRAP_CLUI:break;
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@ -2345,8 +2405,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if(nzuimm) {
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*(X+rs1 % traits::RFS) = *(X+rs1 % traits::RFS) << nzuimm;
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if(rs1 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rs1 != 0) {
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*(X+rs1) = *(X+rs1) << nzuimm;
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}
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}
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}
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TRAP_CSLLI:break;
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@ -2366,14 +2431,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if(rd % traits::RFS) {
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if(rd >= traits::RFS || rd == 0) {
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raise(0, 2);
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}
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else {
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int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CLWSP;
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int32_t res = read_res;
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*(X+rd % traits::RFS) = (int32_t)res;
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}
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else {
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raise(0, 2);
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*(X+rd) = (int32_t)res;
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}
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}
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TRAP_CLWSP:break;
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@ -2393,8 +2458,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = *(X+rs2 % traits::RFS);
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if(rd >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rs2);
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}
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}
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}
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TRAP_CMV:break;
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@ -2413,7 +2483,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if(rs1) {
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if(rs1 && rs1 < traits::RFS) {
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*NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
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super::ex_info.branch_taken=true;
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}
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@ -2451,8 +2521,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if((rd % traits::RFS) != 0) {
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*(X+rd % traits::RFS) = *(X+rd % traits::RFS) + *(X+rs2 % traits::RFS);
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if(rd >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = *(X+rd) + *(X+rs2);
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}
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}
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}
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TRAP_CADD:break;
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@ -2471,11 +2546,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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uint32_t new_pc = *(X+rs1 % traits::RFS);
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*(X+1) = *PC + 2;
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*NEXT_PC = new_pc & ~ 0x1;
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super::ex_info.branch_taken=true;
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}
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if(rs1 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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uint32_t new_pc = *(X+rs1);
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*(X+1) = *PC + 2;
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*NEXT_PC = new_pc & ~ 0x1;
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super::ex_info.branch_taken=true;
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}
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}
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TRAP_CJALR:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::CEBREAK: {
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@ -2506,10 +2586,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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uint32_t offs = *(X+2) + uimm;
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super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 % traits::RFS));
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSWSP;
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}
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if(rs2 >= traits::RFS) {
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raise(0, 2);
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}
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else {
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uint32_t offs = *(X+2) + uimm;
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super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
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if(this->core.trap_state>=0x80000000UL) goto TRAP_CSWSP;
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}
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}
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TRAP_CSWSP:break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::DII: {
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