adds verilog literal and illegal_instr to asmjit

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -174,9 +174,17 @@ private:
      * end opcode definitions
      ****************************************************************************/
     continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
+        this->gen_sync(jh, PRE_SYNC, instr_descr.size());
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_instr_epilogue(jh);
+        this->gen_sync(jh, POST_SYNC, instr_descr.size());
         return BRANCH;
-    }    
+    }
+     
     //decoding functionality
 
     void populate_decoding_tree(decoding_tree_node* root){