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DBT-RISE-TGC
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add marchid setting to CoreDSL description

This commit is contained in:
Eyck Jentzsch 2021-09-30 19:26:21 +02:00
parent 17ee7b138d
commit 4186723d37
4 changed files with 4 additions and 0 deletions
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1
gen_input/TGC_B.core_desc
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@ -8,6 +8,7 @@ Core TGC_B provides RV32I {
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000000000100000000;
unsigned MARCHID_VAL = 0x80000002;
}
}

1
gen_input/TGC_C.core_desc
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@ -8,5 +8,6 @@ Core TGC_C provides RV32I, RV32M, RV32IC {
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000003;
}
}

1
gen_input/TGC_D.core_desc
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@ -8,5 +8,6 @@ Core TGC_D provides RV32I, RV32M, RV32IC {
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

1
gen_input/TGC_D_XRB_MAC.core_desc
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@ -68,5 +68,6 @@ Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}