diff --git a/gen_input/TGC_B.core_desc b/gen_input/TGC_B.core_desc
index 12263b9..78e86ec 100644
--- a/gen_input/TGC_B.core_desc
+++ b/gen_input/TGC_B.core_desc
@@ -8,6 +8,7 @@ Core TGC_B provides RV32I {
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned MARCHID_VAL = 0x80000002;
 	}
 }
 
diff --git a/gen_input/TGC_C.core_desc b/gen_input/TGC_C.core_desc
index 93237ef..a8fed39 100644
--- a/gen_input/TGC_C.core_desc
+++ b/gen_input/TGC_C.core_desc
@@ -8,5 +8,6 @@ Core TGC_C provides RV32I, RV32M, RV32IC {
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MARCHID_VAL = 0x80000003;
     }
 }
diff --git a/gen_input/TGC_D.core_desc b/gen_input/TGC_D.core_desc
index 158f999..9616296 100644
--- a/gen_input/TGC_D.core_desc
+++ b/gen_input/TGC_D.core_desc
@@ -8,5 +8,6 @@ Core TGC_D provides RV32I, RV32M, RV32IC {
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MARCHID_VAL = 0x80000004;
     }
 }
diff --git a/gen_input/TGC_D_XRB_MAC.core_desc b/gen_input/TGC_D_XRB_MAC.core_desc
index 0ab2c8d..9968d56 100644
--- a/gen_input/TGC_D_XRB_MAC.core_desc
+++ b/gen_input/TGC_D_XRB_MAC.core_desc
@@ -68,5 +68,6 @@ Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
         unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MARCHID_VAL = 0x80000004;
     }
 }