DBT-RISE/DBT-RISE-TGC
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop

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alex committed 2024-06-21 13:35:30 +02:00
2 parents 482a4ec253 2fb28364c5
commit 36b076774e
8 files changed
+87 -87
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gen_input/templates/CORENAME.cpp.gtl
+4 -4
View File
@@ -47,10 +47,10 @@ def getRegisterSizes(){
using namespace iss::arch;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;
gen_input/templates/CORENAME.h.gtl
+4 -4
View File
@@ -75,10 +75,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${registers.size}> reg_names{
static constexpr std::array<const char*, ${registers.size()}> reg_names{
{"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
{"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
@@ -99,10 +99,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
gen_input/templates/asmjit/CORENAME.cpp.gtl
+2 -2
View File
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2023 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -129,7 +129,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
gen_input/templates/interp/CORENAME.cpp.gtl
+2 -2
View File
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -160,7 +160,7 @@ private:
};
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
}};
gen_input/templates/llvm/CORENAME.cpp.gtl
+2 -2
View File
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
gen_input/templates/tcc/CORENAME.cpp.gtl
+2 -2
View File
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* Copyright (C) 2020-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
src/iss/arch/tgc5c.h
+1 -1
View File
@@ -53,7 +53,7 @@ template <> struct traits<tgc5c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, RV_CSR_FFLAGS=1ULL, RV_CSR_FRM=2ULL, RV_CSR_FCSR=3ULL, RV_CSR_UTVT=7ULL, RV_CSR_VSTART=8ULL, RV_CSR_VXSAT=9ULL, RV_CSR_VXRM=10ULL, RV_CSR_VCSR=15ULL, RV_CSR_SEED=21ULL, RV_CSR_UNXTI=69ULL, RV_CSR_UINTSTATUS=70ULL, RV_CSR_USCRATCHCSW=72ULL, RV_CSR_USCRATCHCSWL=73ULL, RV_CSR_SSTATUS=256ULL, RV_CSR_SEDELEG=258ULL, RV_CSR_SIDELEG=259ULL, RV_CSR_SIE=260ULL, RV_CSR_STVEC=261ULL, RV_CSR_SCOUNTEREN=262ULL, RV_CSR_STVT=263ULL, RV_CSR_SENVCFG=266ULL, RV_CSR_SSTATEEN0=268ULL, RV_CSR_SSTATEEN1=269ULL, RV_CSR_SSTATEEN2=270ULL, RV_CSR_SSTATEEN3=271ULL, RV_CSR_SSCRATCH=320ULL, RV_CSR_SEPC=321ULL, RV_CSR_SCAUSE=322ULL, RV_CSR_STVAL=323ULL, RV_CSR_SIP=324ULL, RV_CSR_SNXTI=325ULL, RV_CSR_SINTSTATUS=326ULL, RV_CSR_SSCRATCHCSW=328ULL, RV_CSR_SSCRATCHCSWL=329ULL, RV_CSR_STIMECMP=333ULL, RV_CSR_STIMECMPH=349ULL, RV_CSR_SATP=384ULL, RV_CSR_VSSTATUS=512ULL, RV_CSR_VSIE=516ULL, RV_CSR_VSTVEC=517ULL, RV_CSR_VSSCRATCH=576ULL, RV_CSR_VSEPC=577ULL, RV_CSR_VSCAUSE=578ULL, RV_CSR_VSTVAL=579ULL, RV_CSR_VSIP=580ULL, RV_CSR_VSTIMECMP=589ULL, RV_CSR_VSTIMECMPH=605ULL, RV_CSR_VSATP=640ULL, RV_CSR_MSTATUS=768ULL, RV_CSR_MISA=769ULL, RV_CSR_MEDELEG=770ULL, RV_CSR_MIDELEG=771ULL, RV_CSR_MIE=772ULL, RV_CSR_MTVEC=773ULL, RV_CSR_MCOUNTEREN=774ULL, RV_CSR_MTVT=775ULL, RV_CSR_MENVCFG=778ULL, RV_CSR_MSTATEEN0=780ULL, RV_CSR_MSTATEEN1=781ULL, RV_CSR_MSTATEEN2=782ULL, RV_CSR_MSTATEEN3=783ULL, RV_CSR_MSTATUSH=784ULL, RV_CSR_MENVCFGH=794ULL, RV_CSR_MSTATEEN0H=796ULL, RV_CSR_MSTATEEN1H=797ULL, RV_CSR_MSTATEEN2H=798ULL, RV_CSR_MSTATEEN3H=799ULL, RV_CSR_MCOUNTINHIBIT=800ULL, RV_CSR_MHPMEVENT3=803ULL, RV_CSR_MHPMEVENT4=804ULL, RV_CSR_MHPMEVENT5=805ULL, RV_CSR_MHPMEVENT6=806ULL, RV_CSR_MHPMEVENT7=807ULL, RV_CSR_MHPMEVENT8=808ULL, RV_CSR_MHPMEVENT9=809ULL, RV_CSR_MHPMEVENT10=810ULL, RV_CSR_MHPMEVENT11=811ULL, RV_CSR_MHPMEVENT12=812ULL, RV_CSR_MHPMEVENT13=813ULL, RV_CSR_MHPMEVENT14=814ULL, RV_CSR_MHPMEVENT15=815ULL, RV_CSR_MHPMEVENT16=816ULL, RV_CSR_MHPMEVENT17=817ULL, RV_CSR_MHPMEVENT18=818ULL, RV_CSR_MHPMEVENT19=819ULL, RV_CSR_MHPMEVENT20=820ULL, RV_CSR_MHPMEVENT21=821ULL, RV_CSR_MHPMEVENT22=822ULL, RV_CSR_MHPMEVENT23=823ULL, RV_CSR_MHPMEVENT24=824ULL, RV_CSR_MHPMEVENT25=825ULL, RV_CSR_MHPMEVENT26=826ULL, RV_CSR_MHPMEVENT27=827ULL, RV_CSR_MHPMEVENT28=828ULL, RV_CSR_MHPMEVENT29=829ULL, RV_CSR_MHPMEVENT30=830ULL, RV_CSR_MHPMEVENT31=831ULL, RV_CSR_MSCRATCH=832ULL, RV_CSR_MEPC=833ULL, RV_CSR_MCAUSE=834ULL, RV_CSR_MTVAL=835ULL, RV_CSR_MIP=836ULL, RV_CSR_MNXTI=837ULL, RV_CSR_MINTSTATUS=838ULL, RV_CSR_MSCRATCHCSW=840ULL, RV_CSR_MSCRATCHCSWL=841ULL, RV_CSR_MTINST=842ULL, RV_CSR_MTVAL2=843ULL, RV_CSR_PMPCFG0=928ULL, RV_CSR_PMPCFG1=929ULL, RV_CSR_PMPCFG2=930ULL, RV_CSR_PMPCFG3=931ULL, RV_CSR_PMPCFG4=932ULL, RV_CSR_PMPCFG5=933ULL, RV_CSR_PMPCFG6=934ULL, RV_CSR_PMPCFG7=935ULL, RV_CSR_PMPCFG8=936ULL, RV_CSR_PMPCFG9=937ULL, RV_CSR_PMPCFG10=938ULL, RV_CSR_PMPCFG11=939ULL, RV_CSR_PMPCFG12=940ULL, RV_CSR_PMPCFG13=941ULL, RV_CSR_PMPCFG14=942ULL, RV_CSR_PMPCFG15=943ULL, RV_CSR_PMPADDR0=944ULL, RV_CSR_PMPADDR1=945ULL, RV_CSR_PMPADDR2=946ULL, RV_CSR_PMPADDR3=947ULL, RV_CSR_PMPADDR4=948ULL, RV_CSR_PMPADDR5=949ULL, RV_CSR_PMPADDR6=950ULL, RV_CSR_PMPADDR7=951ULL, RV_CSR_PMPADDR8=952ULL, RV_CSR_PMPADDR9=953ULL, RV_CSR_PMPADDR10=954ULL, RV_CSR_PMPADDR11=955ULL, RV_CSR_PMPADDR12=956ULL, RV_CSR_PMPADDR13=957ULL, RV_CSR_PMPADDR14=958ULL, RV_CSR_PMPADDR15=959ULL, RV_CSR_PMPADDR16=960ULL, RV_CSR_PMPADDR17=961ULL, RV_CSR_PMPADDR18=962ULL, RV_CSR_PMPADDR19=963ULL, RV_CSR_PMPADDR20=964ULL, RV_CSR_PMPADDR21=965ULL, RV_CSR_PMPADDR22=966ULL, RV_CSR_PMPADDR23=967ULL, RV_CSR_PMPADDR24=968ULL, RV_CSR_PMPADDR25=969ULL, RV_CSR_PMPADDR26=970ULL, RV_CSR_PMPADDR27=971ULL, RV_CSR_PMPADDR28=972ULL, RV_CSR_PMPADDR29=973ULL, RV_CSR_PMPADDR30=974ULL, RV_CSR_PMPADDR31=975ULL, RV_CSR_PMPADDR32=976ULL, RV_CSR_PMPADDR33=977ULL, RV_CSR_PMPADDR34=978ULL, RV_CSR_PMPADDR35=979ULL, RV_CSR_PMPADDR36=980ULL, RV_CSR_PMPADDR37=981ULL, RV_CSR_PMPADDR38=982ULL, RV_CSR_PMPADDR39=983ULL, RV_CSR_PMPADDR40=984ULL, RV_CSR_PMPADDR41=985ULL, RV_CSR_PMPADDR42=986ULL, RV_CSR_PMPADDR43=987ULL, RV_CSR_PMPADDR44=988ULL, RV_CSR_PMPADDR45=989ULL, RV_CSR_PMPADDR46=990ULL, RV_CSR_PMPADDR47=991ULL, RV_CSR_PMPADDR48=992ULL, RV_CSR_PMPADDR49=993ULL, RV_CSR_PMPADDR50=994ULL, RV_CSR_PMPADDR51=995ULL, RV_CSR_PMPADDR52=996ULL, RV_CSR_PMPADDR53=997ULL, RV_CSR_PMPADDR54=998ULL, RV_CSR_PMPADDR55=999ULL, RV_CSR_PMPADDR56=1000ULL, RV_CSR_PMPADDR57=1001ULL, RV_CSR_PMPADDR58=1002ULL, RV_CSR_PMPADDR59=1003ULL, RV_CSR_PMPADDR60=1004ULL, RV_CSR_PMPADDR61=1005ULL, RV_CSR_PMPADDR62=1006ULL, RV_CSR_PMPADDR63=1007ULL, RV_CSR_SCONTEXT=1448ULL, RV_CSR_HSTATUS=1536ULL, RV_CSR_HEDELEG=1538ULL, RV_CSR_HIDELEG=1539ULL, RV_CSR_HIE=1540ULL, RV_CSR_HTIMEDELTA=1541ULL, RV_CSR_HCOUNTEREN=1542ULL, RV_CSR_HGEIE=1543ULL, RV_CSR_HENVCFG=1546ULL, RV_CSR_HSTATEEN0=1548ULL, RV_CSR_HSTATEELine truncated
constexpr static unsigned FP_REGS_SIZE = 0;
src/vm/interp/vm_tgc5c.cpp
+70 -70
View File
@@ -399,7 +399,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -425,7 +425,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -451,7 +451,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(imm % traits::INSTR_ALIGNMENT) {
@@ -485,7 +485,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t addr_mask = (uint32_t)- 2;
@@ -521,7 +521,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) == *(X+rs2)) {
@@ -554,7 +554,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) != *(X+rs2)) {
@@ -587,7 +587,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
@@ -620,7 +620,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
@@ -653,7 +653,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) < *(X+rs2)) {
@@ -686,7 +686,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) >= *(X+rs2)) {
@@ -719,7 +719,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -750,7 +750,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -781,7 +781,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -812,7 +812,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -843,7 +843,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -874,7 +874,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -901,7 +901,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -928,7 +928,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@@ -955,7 +955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -982,7 +982,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1009,7 +1009,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1036,7 +1036,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1063,7 +1063,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1090,7 +1090,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1117,7 +1117,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1144,7 +1144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1171,11 +1171,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
*(X+rd) = ((uint32_t)((int32_t)*(X+rs1) >> shamt));
}
}
}
@@ -1198,7 +1198,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1225,7 +1225,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1252,7 +1252,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1279,7 +1279,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1306,7 +1306,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1333,7 +1333,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1360,7 +1360,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1387,7 +1387,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1414,7 +1414,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1441,7 +1441,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -1542,7 +1542,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t xrs1 = *(X+rs1);
@@ -1579,7 +1579,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1614,7 +1614,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1649,7 +1649,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1681,7 +1681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1715,7 +1715,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1739,7 +1739,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
@@ -1769,7 +1769,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@@ -1797,7 +1797,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@@ -1825,7 +1825,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) );
@@ -1853,7 +1853,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) );
@@ -1881,7 +1881,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int32_t dividend = (int32_t)*(X+rs1);
@@ -1921,7 +1921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@@ -1955,7 +1955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@@ -1997,7 +1997,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@@ -2033,7 +2033,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@@ -2099,7 +2099,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@@ -2113,7 +2113,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__nop");
this->core.disass_output(pc.val, "c.nop");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@@ -2158,7 +2158,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -2184,7 +2184,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(imm == 0 || rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
@@ -2210,7 +2210,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@@ -2219,13 +2219,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_clui");
this->core.disass_output(pc.val, ".reserved_clui");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")
@@ -2447,7 +2447,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@@ -2473,7 +2473,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rd == 0) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@@ -2500,7 +2500,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -2537,7 +2537,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_cmv");
this->core.disass_output(pc.val, ".reserved_cmv");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@@ -2563,7 +2563,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@@ -2588,7 +2588,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t new_pc = *(X+rs1);
@@ -2602,7 +2602,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::C__EBREAK: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__ebreak");
this->core.disass_output(pc.val, "c.ebreak");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@@ -2628,7 +2628,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@@ -2647,7 +2647,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")