DBT-RISE
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DBT-RISE-TGC
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop

This commit is contained in:
Eyck-Alexander Jentzsch 2024-06-21 13:35:30 +02:00
parent 482a4ec253 2fb28364c5
commit 36b076774e
8 changed files with 87 additions and 87 deletions
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8
gen_input/templates/CORENAME.cpp.gtl
View File

@ -47,10 +47,10 @@ def getRegisterSizes(){
using namespace iss::arch;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;

8
gen_input/templates/CORENAME.h.gtl
View File

@ -75,10 +75,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${registers.size}> reg_names{
static constexpr std::array<const char*, ${registers.size()}> reg_names{
{"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
{"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
@ -99,10 +99,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

4
gen_input/templates/asmjit/CORENAME.cpp.gtl
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2023 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -129,7 +129,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>

4
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -160,7 +160,7 @@ private:
};
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
}};

4
gen_input/templates/llvm/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>

4
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* Copyright (C) 2020-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>

2
src/iss/arch/tgc5c.h
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File diff suppressed because one or more lines are too long

140
src/vm/interp/vm_tgc5c.cpp
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@ -399,7 +399,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -425,7 +425,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -451,7 +451,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(imm % traits::INSTR_ALIGNMENT) {
@ -485,7 +485,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t addr_mask = (uint32_t)- 2;
@ -521,7 +521,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) == *(X+rs2)) {
@ -554,7 +554,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) != *(X+rs2)) {
@ -587,7 +587,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
@ -620,7 +620,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
@ -653,7 +653,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) < *(X+rs2)) {
@ -686,7 +686,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) >= *(X+rs2)) {
@ -719,7 +719,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -750,7 +750,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -781,7 +781,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -812,7 +812,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -843,7 +843,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -874,7 +874,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -901,7 +901,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -928,7 +928,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -955,7 +955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -982,7 +982,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1009,7 +1009,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1036,7 +1036,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1063,7 +1063,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1090,7 +1090,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1117,7 +1117,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1144,7 +1144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1171,11 +1171,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
*(X+rd) = ((uint32_t)((int32_t)*(X+rs1) >> shamt));
}
}
}
@ -1198,7 +1198,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1225,7 +1225,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1252,7 +1252,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1279,7 +1279,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1306,7 +1306,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1333,7 +1333,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1360,7 +1360,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1387,7 +1387,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1414,7 +1414,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1441,7 +1441,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1542,7 +1542,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t xrs1 = *(X+rs1);
@ -1579,7 +1579,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1614,7 +1614,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1649,7 +1649,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1681,7 +1681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1715,7 +1715,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1739,7 +1739,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
@ -1769,7 +1769,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@ -1797,7 +1797,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@ -1825,7 +1825,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) );
@ -1853,7 +1853,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) );
@ -1881,7 +1881,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int32_t dividend = (int32_t)*(X+rs1);
@ -1921,7 +1921,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -1955,7 +1955,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -1997,7 +1997,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -2033,7 +2033,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@ -2099,7 +2099,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@ -2113,7 +2113,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__nop");
this->core.disass_output(pc.val, "c.nop");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2158,7 +2158,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2184,7 +2184,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(imm == 0 || rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
@ -2210,7 +2210,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@ -2219,13 +2219,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_clui");
this->core.disass_output(pc.val, ".reserved_clui");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")
@ -2447,7 +2447,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@ -2473,7 +2473,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rd == 0) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@ -2500,7 +2500,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2537,7 +2537,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_cmv");
this->core.disass_output(pc.val, ".reserved_cmv");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2563,7 +2563,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2588,7 +2588,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t new_pc = *(X+rs1);
@ -2602,7 +2602,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::C__EBREAK: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__ebreak");
this->core.disass_output(pc.val, "c.ebreak");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2628,7 +2628,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@ -2647,7 +2647,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")