adds asmjit
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/*******************************************************************************
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* Copyright (C) 2017, 2023 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/asmjit/vm_base.h>
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#include <asmjit/asmjit.h>
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#include <util/logging.h>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace asmjit {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace ::asmjit;
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::asmjit::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using mem_type_e = typename super::mem_type_e;
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using addr_t = typename super::addr_t;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using this_class = vm_impl<ARCH>;
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using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
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continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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#include "helper_func.h"
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct instruction_descriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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struct decoding_tree_node{
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std::vector<instruction_descriptor> instrs;
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std::vector<decoding_tree_node*> children;
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uint32_t submask = std::numeric_limits<uint32_t>::max();
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uint32_t value;
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decoding_tree_node(uint32_t value) : value(value){}
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};
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decoding_tree_node* root {nullptr};
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const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
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{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
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uint64_t PC = pc.val;
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate disass */
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}
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x86::Compiler& cc = jh.cc;
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//ideally only do this if necessary (someone / plugin needs it)
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cc.mov(jh.pc,PC);
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cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str());
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this->gen_sync(jh, PRE_SYNC, ${idx});
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pc=pc+ ${instr.length/8};
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gen_instr_prologue(jh, pc.val);
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cc.comment("\\n//behavior:");
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/*generate behavior*/
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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gen_instr_epilogue(jh);
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this->gen_sync(jh, POST_SYNC, ${idx});
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return returnValue;
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
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return BRANCH;
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}
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//decoding functionality
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void populate_decoding_tree(decoding_tree_node* root){
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//create submask
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for(auto instr: root->instrs){
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root->submask &= instr.mask;
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}
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//put each instr according to submask&encoding into children
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for(auto instr: root->instrs){
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bool foundMatch = false;
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for(auto child: root->children){
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//use value as identifying trait
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if(child->value == (instr.value&root->submask)){
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child->instrs.push_back(instr);
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foundMatch = true;
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}
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}
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if(!foundMatch){
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decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
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child->instrs.push_back(instr);
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root->children.push_back(child);
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}
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}
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root->instrs.clear();
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//call populate_decoding_tree for all children
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if(root->children.size() >1)
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for(auto child: root->children){
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populate_decoding_tree(child);
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}
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else{
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//sort instrs by value of the mask, this works bc we want to have the least restrictive one last
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std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
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return instr1.mask > instr2.mask;
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});
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}
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}
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compile_func decode_instr(decoding_tree_node* node, code_word_t word){
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if(!node->children.size()){
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if(node->instrs.size() == 1) return node->instrs[0].op;
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for(auto instr : node->instrs){
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if((instr.mask&word) == instr.value) return instr.op;
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}
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}
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else{
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for(auto child : node->children){
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if (child->value == (node->submask&word)){
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return decode_instr(child, word);
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}
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}
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}
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return nullptr;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
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volatile CODE_WORD x = instr;
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instr = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
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for(auto instr: instr_descr){
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root->instrs.push_back(instr);
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}
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populate_decoding_tree(root);
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}
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template <typename ARCH>
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continuation_e
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
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enum {TRAP_ID=1<<16};
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code_word_t instr = 0;
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phys_addr_t paddr(pc);
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auto *const data = (uint8_t *)&instr;
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok)
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throw trap_access(TRAP_ID, pc.val);
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if (instr == 0x0000006f || (instr&0xffff)==0xa001)
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throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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++inst_cnt;
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auto f = decode_instr(root, instr);
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if (f == nullptr)
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f = &this_class::illegal_intruction;
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return (this->*f)(pc, instr, jh);
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}
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} // namespace ${coreDef.name.toLowerCase()}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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} // namespace asmjit
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} // namespace iss
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#include <iss/factory.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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}),
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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})
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};
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}
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}
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x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx){
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x86::Gp tmp_ptr = jh.cc.newUIntPtr("tmp_ptr");
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jh.cc.mov(tmp_ptr, jh.regs_base_ptr);
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jh.cc.add(tmp_ptr, traits::reg_byte_offsets[idx]);
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switch(traits::reg_bit_widths[idx]){
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case 8:
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return x86::ptr_8(tmp_ptr);
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case 16:
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return x86::ptr_16(tmp_ptr);
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case 32:
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return x86::ptr_32(tmp_ptr);
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case 64:
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return x86::ptr_64(tmp_ptr);
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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x86::Gp get_reg_for(jit_holder& jh, unsigned idx){
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//can check for regs in jh and return them instead of creating new ones
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switch(traits::reg_bit_widths[idx]){
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case 8:
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return jh.cc.newInt8();
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case 16:
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return jh.cc.newInt16();
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case 32:
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return jh.cc.newInt32();
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case 64:
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return jh.cc.newInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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x86::Gp get_reg_for(jit_holder& jh, unsigned size, bool is_signed){
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if(is_signed)
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switch(size){
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case 8:
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return jh.cc.newInt8();
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case 16:
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return jh.cc.newInt16();
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case 32:
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return jh.cc.newInt32();
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case 64:
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return jh.cc.newInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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else
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switch(size){
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case 8:
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return jh.cc.newUInt8();
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case 16:
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return jh.cc.newUInt16();
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case 32:
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return jh.cc.newUInt32();
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case 64:
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return jh.cc.newUInt64();
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default:
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throw std::runtime_error("Invalid reg size in get_reg_ptr");
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}
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}
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inline x86::Gp load_reg_from_mem(jit_holder& jh, unsigned idx){
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auto ptr = get_reg_ptr(jh, idx);
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auto reg = get_reg_for(jh, idx);
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jh.cc.mov(reg, ptr);
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return reg;
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}
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inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx){
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auto ptr = get_reg_ptr(jh, idx);
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jh.cc.mov(ptr, reg);
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}
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void gen_instr_prologue(jit_holder& jh, addr_t pc){
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auto& cc = jh.cc;
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cc.comment("\n//(*icount)++;");
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cc.inc(get_reg_ptr(jh, traits::ICOUNT));
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cc.comment("\n//*pc=*next_pc;");
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cc.mov(get_reg_ptr(jh, traits::PC), jh.next_pc);
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cc.comment("\n//*trap_state=*pending_trap;");
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cc.mov(get_reg_ptr(jh, traits::PENDING_TRAP), jh.trap_state);
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cc.comment("\n//increment *next_pc");
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cc.mov(jh.next_pc, pc);
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}
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void gen_instr_epilogue(jit_holder& jh){
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auto& cc = jh.cc;
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cc.comment("\n//if(*trap_state!=0) goto trap_entry;");
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cc.test(jh.trap_state, jh.trap_state);
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cc.jnz(jh.trap_entry);
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//Does this need to be done after every single instruction?
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cc.comment("\n//write back regs to mem");
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write_reg_to_mem(jh, jh.pc, traits::PC);
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write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
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write_reg_to_mem(jh, jh.trap_state, traits::TRAP_STATE);
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}
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void gen_block_prologue(jit_holder& jh) override{
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jh.pc = load_reg_from_mem(jh, traits::PC);
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jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
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jh.trap_state = load_reg_from_mem(jh, traits::TRAP_STATE);
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}
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void gen_block_epilogue(jit_holder& jh) override{
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x86::Compiler& cc = jh.cc;
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cc.comment("\n//return *next_pc;");
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cc.ret(jh.next_pc);
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cc.bind(jh.trap_entry);
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cc.comment("\n//enter_trap(core_ptr, *trap_state, *pc, 0);");
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x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
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cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
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x86::Gp current_pc = get_reg_for(jh, traits::PC);
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cc.mov(current_pc, get_reg_ptr(jh, traits::PC));
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x86::Gp instr = cc.newInt32("instr");
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cc.mov(instr, 0);
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InvokeNode* call_enter_trap;
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cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
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call_enter_trap->setArg(0, jh.arch_if_ptr);
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call_enter_trap->setArg(1, current_trap_state);
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call_enter_trap->setArg(2, current_pc);
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call_enter_trap->setArg(3, instr);
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cc.comment("\n//*last_branch = std::numeric_limits<uint32_t>::max();");
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cc.mov(get_reg_ptr(jh,traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
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cc.comment("\n//return *next_pc;");
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cc.ret(jh.next_pc);
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}
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//TODO implement
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|
||||
void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
|
||||
jh.cc.comment("//gen_raise");
|
||||
}
|
||||
void gen_wait(jit_holder& jh, unsigned type) {
|
||||
jh.cc.comment("//gen_wait");
|
||||
}
|
||||
void gen_leave(jit_holder& jh, unsigned lvl){
|
||||
jh.cc.comment("//gen_leave");
|
||||
}
|
||||
|
||||
enum operation {add, sub, band, bor, bxor, shl, sar , shr};
|
||||
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
|
||||
x86::Gp gen_operation(jit_holder& jh, operation op, x86::Gp a, T b){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
switch (op) {
|
||||
case add: { cc.add(a, b); break; }
|
||||
case sub: { cc.sub(a, b); break; }
|
||||
case band: { cc.and_(a, b); break; }
|
||||
case bor: { cc.or_(a, b); break; }
|
||||
case bxor: { cc.xor_(a, b); break; }
|
||||
case shl: { cc.shl(a, b); break; }
|
||||
case sar: { cc.sar(a, b); break; }
|
||||
case shr: { cc.shr(a, b); break; }
|
||||
default: throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (operation)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
|
||||
enum three_operand_operation{imul, mul, idiv, div, srem, urem};
|
||||
|
||||
x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, x86::Gp b){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
switch (op) {
|
||||
case imul: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.imul(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case mul: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mul(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case idiv: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mov(dummy, 0);
|
||||
cc.idiv(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case div: {
|
||||
x86::Gp dummy = cc.newInt64();
|
||||
cc.mov(dummy, 0);
|
||||
cc.div(dummy, a.r64(), b.r64());
|
||||
return a;
|
||||
}
|
||||
case srem:{
|
||||
x86::Gp rem = cc.newInt32();
|
||||
cc.mov(rem, 0);
|
||||
auto a_reg = cc.newInt32();
|
||||
cc.mov(a_reg, a.r32());
|
||||
cc.idiv(rem, a_reg, b.r32());
|
||||
return rem;
|
||||
}
|
||||
case urem:{
|
||||
x86::Gp rem = cc.newInt32();
|
||||
cc.mov(rem, 0);
|
||||
auto a_reg = cc.newInt32();
|
||||
cc.mov(a_reg, a.r32());
|
||||
cc.div(rem, a_reg, b.r32());
|
||||
return rem;
|
||||
}
|
||||
|
||||
default: throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (three_operand)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
|
||||
x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, T b){
|
||||
x86::Gp b_reg = jh.cc.newInt32();
|
||||
/* switch(a.size()){
|
||||
case 1: b_reg = jh.cc.newInt8(); break;
|
||||
case 2: b_reg = jh.cc.newInt16(); break;
|
||||
case 4: b_reg = jh.cc.newInt32(); break;
|
||||
case 8: b_reg = jh.cc.newInt64(); break;
|
||||
default: throw std::runtime_error(fmt::format("Invalid size ({}) in gen operation", a.size()));
|
||||
} */
|
||||
jh.cc.mov(b_reg, b);
|
||||
return gen_operation(jh, op, a, b_reg);
|
||||
}
|
||||
enum comparison_operation{land, lor, eq, ne, lt, ltu, gt, gtu, lte, lteu, gte, gteu};
|
||||
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
|
||||
x86::Gp gen_operation(jit_holder& jh, comparison_operation op, x86::Gp a, T b){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
x86::Gp tmp = cc.newInt8();
|
||||
cc.mov(tmp,1);
|
||||
Label label_then = cc.newLabel();
|
||||
cc.cmp(a,b);
|
||||
switch (op) {
|
||||
case eq: cc.je(label_then); break;
|
||||
case ne: cc.jne(label_then); break;
|
||||
case lt: cc.jl(label_then); break;
|
||||
case ltu: cc.jb(label_then); break;
|
||||
case gt: cc.jg(label_then); break;
|
||||
case gtu: cc.ja(label_then); break;
|
||||
case lte: cc.jle(label_then); break;
|
||||
case lteu: cc.jbe(label_then); break;
|
||||
case gte: cc.jge(label_then); break;
|
||||
case gteu: cc.jae(label_then); break;
|
||||
case land: {
|
||||
Label label_false = cc.newLabel();
|
||||
cc.cmp(a, 0);
|
||||
cc.je(label_false);
|
||||
auto b_reg = cc.newInt8();
|
||||
cc.mov(b_reg, b);
|
||||
cc.cmp(b_reg, 0);
|
||||
cc.je(label_false);
|
||||
cc.jmp(label_then);
|
||||
cc.bind(label_false);
|
||||
break;
|
||||
}
|
||||
case lor: {
|
||||
cc.cmp(a, 0);
|
||||
cc.jne(label_then);
|
||||
auto b_reg = cc.newInt8();
|
||||
cc.mov(b_reg, b);
|
||||
cc.cmp(b_reg, 0);
|
||||
cc.jne(label_then);
|
||||
break;
|
||||
}
|
||||
default: throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (comparison)", op));
|
||||
}
|
||||
cc.mov(tmp,0);
|
||||
cc.bind(label_then);
|
||||
return tmp;
|
||||
}
|
||||
enum binary_operation{lnot, inc, dec, bnot, neg};
|
||||
|
||||
x86::Gp gen_operation(jit_holder& jh, binary_operation op, x86::Gp a){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
switch (op) {
|
||||
case lnot: throw std::runtime_error("Current operation not supported in gen_operation(lnot)");
|
||||
case inc: { cc.inc(a); break; }
|
||||
case dec: { cc.dec(a); break; }
|
||||
case bnot: { cc.not_(a); break; }
|
||||
case neg: { cc.neg(a); break; }
|
||||
default: throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (unary)", op));
|
||||
}
|
||||
return a;
|
||||
}
|
||||
|
||||
/* template <typename T>
|
||||
inline typename std::enable_if_t<std::is_unsigned<T>::value, x86::Gp> gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) const {
|
||||
auto val_reg = get_reg_for(jh, sizeof(val)*8);
|
||||
auto tmp = get_reg_for(jh, size);
|
||||
jh.cc.mov(val_reg, val);
|
||||
if(is_signed) jh.cc.movsx(tmp, val_reg);
|
||||
else jh.cc.movzx(tmp,val_reg);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
inline typename std::enable_if_t<std::is_signed<T>::value, x86::Gp> gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) const {
|
||||
auto val_reg = get_reg_for(jh, sizeof(val)*8);
|
||||
auto tmp = get_reg_for(jh, size);
|
||||
jh.cc.mov(val_reg, val);
|
||||
if(is_signed) jh.cc.movsx(tmp, val_reg);
|
||||
else jh.cc.movzx(tmp,val_reg);
|
||||
return tmp;
|
||||
} */
|
||||
template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
|
||||
inline x86::Gp gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) {
|
||||
auto val_reg = get_reg_for(jh, sizeof(val)*8);
|
||||
jh.cc.mov(val_reg, val);
|
||||
return gen_ext(jh, val_reg, size, is_signed);
|
||||
}
|
||||
//explicit Gp size cast
|
||||
inline x86::Gp gen_ext(jit_holder& jh, x86::Gp val, unsigned size, bool is_signed) {
|
||||
auto& cc = jh.cc;
|
||||
if(is_signed){
|
||||
switch(val.size()){
|
||||
case 1: cc.cbw(val); break;
|
||||
case 2: cc.cwde(val); break;
|
||||
case 4: cc.cdqe(val); break;
|
||||
case 8: break;
|
||||
default: throw std::runtime_error("Invalid register size in gen_ext");
|
||||
}
|
||||
}
|
||||
switch(size){
|
||||
case 8: cc.and_(val,std::numeric_limits<uint8_t>::max()); return val.r8();
|
||||
case 16: cc.and_(val,std::numeric_limits<uint16_t>::max()); return val.r16();
|
||||
case 32: cc.and_(val,std::numeric_limits<uint32_t>::max()); return val.r32();
|
||||
case 64: cc.and_(val,std::numeric_limits<uint64_t>::max()); return val.r64();
|
||||
case 128: return val.r64();
|
||||
default: throw std::runtime_error("Invalid size in gen_ext");
|
||||
}
|
||||
}
|
||||
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, uint32_t length){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
auto ret_reg = cc.newInt32();
|
||||
|
||||
auto mem_type_reg = cc.newInt32();
|
||||
cc.mov(mem_type_reg, type);
|
||||
|
||||
auto space_reg = cc.newInt32();
|
||||
cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
|
||||
|
||||
auto val_ptr = cc.newUIntPtr();
|
||||
cc.mov(val_ptr, read_mem_buf);
|
||||
|
||||
InvokeNode* invokeNode;
|
||||
uint64_t mask = 0;
|
||||
x86::Gp val_reg = cc.newInt64();
|
||||
|
||||
switch(length){
|
||||
case 1:{
|
||||
cc.invoke(&invokeNode, &read_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint8_t>::max();
|
||||
break;
|
||||
}
|
||||
case 2:{
|
||||
cc.invoke(&invokeNode, &read_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint16_t>::max();
|
||||
break;
|
||||
}
|
||||
case 4:{
|
||||
cc.invoke(&invokeNode, &read_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint32_t>::max();
|
||||
break;
|
||||
}
|
||||
case 8:{
|
||||
cc.invoke(&invokeNode, &read_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
|
||||
mask = std::numeric_limits<uint64_t>::max();
|
||||
break;
|
||||
}
|
||||
default: throw std::runtime_error(fmt::format("Invalid length ({}) in gen_read_mem",length));
|
||||
}
|
||||
|
||||
invokeNode->setRet(0, ret_reg);
|
||||
invokeNode->setArg(0, jh.arch_if_ptr);
|
||||
invokeNode->setArg(1, space_reg);
|
||||
invokeNode->setArg(2, mem_type_reg);
|
||||
invokeNode->setArg(3, addr);
|
||||
invokeNode->setArg(4, val_ptr);
|
||||
|
||||
cc.mov(val_reg, x86::ptr_64(val_ptr));
|
||||
cc.and_(val_reg, mask);
|
||||
cc.cmp(ret_reg,0);
|
||||
cc.jne(jh.trap_entry);
|
||||
return val_reg;
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp length){
|
||||
uint32_t length_val = 0;
|
||||
auto length_ptr = jh.cc.newIntPtr();
|
||||
jh.cc.mov(length_ptr, &length_val);
|
||||
jh.cc.mov(x86::ptr_32(length_ptr),length);
|
||||
|
||||
return gen_read_mem(jh, type, addr, length);
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp length){
|
||||
auto addr_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
|
||||
uint32_t length_val = 0;
|
||||
auto length_ptr = jh.cc.newIntPtr();
|
||||
jh.cc.mov(length_ptr, &length_val);
|
||||
jh.cc.mov(x86::ptr_32(length_ptr),length);
|
||||
|
||||
return gen_read_mem(jh, type, addr_reg, length_val);
|
||||
}
|
||||
inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, uint32_t length){
|
||||
auto addr_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
|
||||
return gen_read_mem(jh, type, addr_reg, length);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, int64_t val){
|
||||
auto val_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(val_reg, val);
|
||||
gen_write_mem(jh, type, addr, val_reg);
|
||||
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp val){
|
||||
x86::Compiler& cc = jh.cc;
|
||||
|
||||
auto mem_type_reg = cc.newInt32();
|
||||
jh.cc.mov(mem_type_reg, type);
|
||||
auto space_reg = cc.newInt32();
|
||||
jh.cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
|
||||
auto ret_reg = cc.newInt32();
|
||||
InvokeNode* invokeNode;
|
||||
|
||||
if(val.isGpb()){
|
||||
cc.invoke(&invokeNode, &write_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint8_t>());
|
||||
}
|
||||
else if(val.isGpw()){
|
||||
cc.invoke(&invokeNode, &write_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint16_t>());
|
||||
}
|
||||
else if(val.isGpd()){
|
||||
cc.invoke(&invokeNode, &write_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint32_t>());
|
||||
}
|
||||
else if(val.isGpq()){
|
||||
cc.invoke(&invokeNode, &write_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint64_t>());
|
||||
}
|
||||
else throw std::runtime_error("Invalid register size in gen_write_mem");
|
||||
|
||||
invokeNode->setRet(0,ret_reg);
|
||||
invokeNode->setArg(0, jh.arch_if_ptr);
|
||||
invokeNode->setArg(1, space_reg);
|
||||
invokeNode->setArg(2, mem_type_reg);
|
||||
invokeNode->setArg(3, addr);
|
||||
invokeNode->setArg(4, val);
|
||||
|
||||
cc.cmp(ret_reg,0);
|
||||
cc.jne(jh.trap_entry);
|
||||
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp val){
|
||||
auto addr_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
gen_write_mem(jh, type, addr_reg, val);
|
||||
}
|
||||
inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_t val){
|
||||
auto val_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(val_reg, val);
|
||||
|
||||
auto addr_reg = jh.cc.newInt64();
|
||||
jh.cc.mov(addr_reg, addr);
|
||||
gen_write_mem(jh, type, addr_reg, val_reg);
|
||||
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue