changes jh globals to seperate riscv specifics

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop

.clang-format

@@ -1,4 +1,3 @@
----
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -13,8 +12,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: true
-AllowShortLoopsOnASingleLine: true
+AllowShortIfStatementsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -39,8 +38,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     120
-CommentPragmas:  '^ IWYU pragma:'
+ColumnLimit:     140
+CommentPragmas:  '^( IWYU pragma:| @suppress)'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -76,13 +75,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Right
+PointerAlignment: Left
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: ControlStatements
+SpaceBeforeParens: Never
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,5 +1,6 @@
 .DS_Store
 /*.il
+/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -14,7 +15,6 @@
 /*.ods
 /build*/
 /*.logs
-language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb
@@ -30,4 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
+/*.yaml
+/*.json

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
-	path = gen_input/CoreDSL-Instruction-Set-Description
-	url = ../CoreDSL-Instruction-Set-Description.git

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

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.settings/org.eclipse.cdt.core.prefs

@@ -1,13 +0,0 @@
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CMakeLists.txt

@@ -1,77 +1,122 @@
-cmake_minimum_required(VERSION 3.12)
+cmake_minimum_required(VERSION 3.18)
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
+
 # ##############################################################################
 #
 # ##############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
+include(flink)
 
-find_package(elfio)
-
-if(WITH_LLVM)
-    if(DEFINED ENV{LLVM_HOME})
-        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-    endif(DEFINED ENV{LLVM_HOME})
-    find_package(LLVM REQUIRED CONFIG)
-    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
-endif()
-
-#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
-#set(CMAKE_MACOSX_RPATH ON)
-#set(CMAKE_SKIP_BUILD_RPATH FALSE)
-#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
-#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
-#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
+find_package(elfio QUIET)
+find_package(jsoncpp)
+find_package(Boost COMPONENTS coroutine REQUIRED)
 
 add_subdirectory(softfloat)
 
-# library files
-FILE(GLOB TGC_SOURCES
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
-)
 set(LIB_SOURCES
+    src/iss/plugin/instruction_count.cpp
+    src/iss/arch/tgc5c.cpp
+    src/vm/interp/vm_tgc5c.cpp
     src/vm/fp_functions.cpp
-    src/plugin/instruction_count.cpp
-    src/plugin/cycle_estimate.cpp
-    ${TGC_SOURCES}
+    src/vm/instruction_decoder.cpp
+    src/iss/semihosting/semihosting.cpp
 )
 
+if(WITH_TCC)
+    list(APPEND LIB_SOURCES
+        src/vm/tcc/vm_tgc5c.cpp
+    )
+endif()
+
 if(WITH_LLVM)
-  set(LIB_SOURCES ${LIB_SOURCES}
+    list(APPEND LIB_SOURCES
+        src/vm/llvm/vm_tgc5c.cpp
         src/vm/llvm/fp_impl.cpp
-    #src/vm/llvm/vm_tgf_b.cpp
-    #src/vm/llvm/vm_tgf_c.cpp
+    )
+endif()
+
+if(WITH_ASMJIT)
+    list(APPEND LIB_SOURCES
+        src/vm/asmjit/vm_tgc5c.cpp
+    )
+endif()
+
+# library files
+FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
+list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+
+foreach(FILEPATH ${GEN_ISS_SOURCES})
+    get_filename_component(CORE ${FILEPATH} NAME_WE)
+    string(TOUPPER ${CORE} CORE)
+    list(APPEND LIB_DEFINES CORE_${CORE})
+endforeach()
+
+message(STATUS "Core defines are ${LIB_DEFINES}")
+
+if(WITH_LLVM)
+    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+endif()
+
+if(WITH_TCC)
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(WITH_ASMJIT)
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(TARGET yaml-cpp::yaml-cpp)
+    list(APPEND LIB_SOURCES
+        src/iss/plugin/cycle_estimate.cpp
+        src/iss/plugin/instruction_count.cpp
     )
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} ${LIB_SOURCES})
-# list code gen dependencies
-if(TARGET ${CORE_NAME}_cpp)
-    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
-endif()
+add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
-    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-else()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
+
+target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+
+target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+
+# only re-export the include paths
+get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
+target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
+get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
+
+if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+endif()
+
+target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
+
+if(TARGET yaml-cpp::yaml-cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
+    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
+endif()
+
+if(WITH_LLVM)
+    find_package(LLVM)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+
+    if(BUILD_SHARED_LIBS)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
     endif()
-if(TARGET CONAN_PKG::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
-elseif(TARGET elfio::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
-else()
-    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
 endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
@@ -92,27 +137,52 @@ install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
     FILES_MATCHING # install only matched files
     PATTERN "*.h" # select header files
 )
+install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
+
 # ##############################################################################
 #
 # ##############################################################################
+set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
-target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-if(WITH_LLVM)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-endif()
-# Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
-if(TARGET Boost::program_options)
-    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
+
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
 else()
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY} ${BOOST_thread_LIBRARY})
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
 endif()
+
+foreach(F IN LISTS TGC_SOURCES)
+    if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endif()
+endforeach()
+
+# if(WITH_LLVM)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+# endif()
+# if(WITH_TCC)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+# endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
+
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
+endif()
+
 target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
+
 if(Tcmalloc_FOUND)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
@@ -126,31 +196,57 @@ install(TARGETS tgc-sim
     PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
     INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
 )
+
+if(BUILD_TESTING)
+    # ... CMake code to create tests ...
+    add_test(NAME tgc-sim-interp
+        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
+
+    if(WITH_TCC)
+        add_test(NAME tgc-sim-tcc
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
+    endif()
+
+    if(WITH_LLVM)
+        add_test(NAME tgc-sim-llvm
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
+    endif()
+
+    if(WITH_ASMJIT)
+        add_test(NAME tgc-sim-asmjit
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
+    endif()
+endif()
+
 # ##############################################################################
 #
 # ##############################################################################
+if(TARGET scc-sysc)
     project(dbt-rise-tgc_sc VERSION 1.0.0)
-
-include(SystemCPackage)
-if(SystemC_FOUND)
-    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    set(LIB_SOURCES
+        src/sysc/core_complex.cpp
+        src/sysc/register_tgc_c.cpp
+    )
+    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
+    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
+    add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
-    endif()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
-    if(WITH_LLVM)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-    endif()
 
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    foreach(F IN LISTS TGC_SOURCES)
+        if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+            string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
+            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        endif()
+    endforeach()
+
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+
+    # if(WITH_LLVM)
+    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    # endif()
+    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
         VERSION ${PROJECT_VERSION}
         FRAMEWORK FALSE
@@ -166,4 +262,3 @@ if(SystemC_FOUND)
         INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
     )
 endif()
-

cmake/flink.cmake

@@ -0,0 +1,35 @@
+# according to https://github.com/horance-liu/flink.cmake/tree/master
+# SPDX-License-Identifier: Apache-2.0
+
+include(CMakeParseArguments)
+
+function(target_do_force_link_libraries target visibility lib)
+  if(MSVC)
+    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
+  elseif(APPLE)
+    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
+  else()
+    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
+  endif()
+endfunction()
+
+function(target_force_link_libraries target)
+  cmake_parse_arguments(FLINK
+    ""
+    ""
+    "PUBLIC;INTERFACE;PRIVATE"
+    ${ARGN}
+  )
+  
+  foreach(lib IN LISTS FLINK_PUBLIC)
+    target_do_force_link_libraries(${target} PUBLIC ${lib})
+  endforeach()
+
+  foreach(lib IN LISTS FLINK_INTERFACE)
+    target_do_force_link_libraries(${target} INTERFACE ${lib})
+  endforeach()
+  
+  foreach(lib IN LISTS FLINK_PRIVATE)
+    target_do_force_link_libraries(${target} PRIVATE ${lib})
+  endforeach()
+endfunction()

contrib/instr/.gitignore

@@ -0,0 +1 @@
+/*.yaml

contrib/instr/TGC5C_instr.yaml

@@ -0,0 +1,624 @@
+
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+    mask: 0b00000000000000000000000001111111
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+    mask: 0b00000000000000000000000001111111
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+    branch:   false
+    delay:   1
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contrib/pa/.gitignore

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+/results
+/cwr
+/*.xml

contrib/pa/README.md

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+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```

contrib/pa/build.tcl

@@ -16,7 +16,7 @@ namespace eval Specification {
                 set libdir "${install_dir}/lib64"
                 set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                 # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
             }
             default {
                puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"

contrib/pa/tgc_import.tcl

@@ -6,14 +6,11 @@ proc getScriptDirectory {} {
     set scriptFolder [file dirname $dispScriptFile]
     return $scriptFolder
 }
-if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
     set hardware /HARDWARE/HW/HW
-} else {
-    set hardware /HARDWARE
-}
 
 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -28,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
 
 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -38,13 +36,15 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
     ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
 
 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/pa/tgc_import_tb.tcl

@@ -0,0 +1,71 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
+::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
+::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
+::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
+::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
+::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml

gen_input/.gitignore

@@ -1 +1,2 @@
 /src-gen/
+/CoreDSL-Instruction-Set-Description

gen_input/TGC5C.core_desc

@@ -0,0 +1,13 @@
+import "ISA/RVI.core_desc"
+import "ISA/RVM.core_desc"
+import "ISA/RVC.core_desc"
+
+Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned int MARCHID_VAL = 0x80000003;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,37 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGC_B provides RV32I {
-	architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGC_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-    }
-}
-
-Core TGC_D provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-    }
-}

gen_input/templates/CORENAME.cpp.gtl

@@ -33,32 +33,33 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 %>
+// clang-format off
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
@@ -70,7 +71,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
 }
-
+// clang-format on

gen_input/templates/CORENAME.h.gtl

@@ -30,14 +30,12 @@
  *
  *******************************************************************************/
 <%
-import com.minres.coredsl.util.BigIntegerWithRadix
-
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 def getRegisterOffsets(){
@@ -57,15 +55,12 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    if(val instanceof BigIntegerWithRadix)
-        return ((BigIntegerWithRadix)val).toCString()
-    else
-        return val.toString()
+    return val.toString()+'ULL'
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-
+// clang-format off
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -80,23 +75,18 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     constexpr static char const* const core_type = "${coreDef.name}";
     
-    static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+    static constexpr std::array<const char*, ${registers.size()}> reg_names{
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
  
-    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
     constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
     enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -109,19 +99,19 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
         {${getRegisterSizes().join(',')}}};
 
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
         {${getRegisterOffsets().join(',')}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
     
-    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };
@@ -140,14 +130,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
     inline uint64_t get_icount() { return reg.icount; }
 
@@ -155,21 +137,13 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-protected:
+
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%
         registers.each { reg -> if(reg.size>0) {%> 
@@ -179,7 +153,8 @@ protected:
         uint64_t icount = 0;
         uint64_t cycle = 0;
         uint64_t instret = 0;
-        uint32_t last_branch;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
     } reg;
 #pragma pack(pop)
     std::array<address_type, 4> addr_mode;
@@ -199,3 +174,4 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
+// clang-format on

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -3,7 +3,10 @@
 		{
 			"name"  :   "${instr.name}",
 			"size"  :   ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"encoding": "${instr.encoding}",
+            "mask":     "${instr.mask}",
+			"branch":   ${instr.modifiesPC},
+			"delay" :   ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -0,0 +1,21 @@
+<% def getInstructionGroups() {
+    def instrGroups = [:]
+    instructions.each {
+        def groupName = it['instruction'].eContainer().name
+        if(!instrGroups.containsKey(groupName)) {
+            instrGroups[groupName]=[]
+        }
+        instrGroups[groupName]+=it;
+    }
+    instrGroups
+}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
+${name}: <% instrList.each { %>
+  ${it.instruction.name}:
+    index: ${index++}
+    encoding: ${it.encoding}
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}%>
+    size:   ${it.length}
+    branch:   ${it.modifiesPC}
+    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
+

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <sysc/iss_factory.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <sysc/sc_core_adapter.h>
+#include <sysc/core_complex.h>
+#include <array>
+<%
+def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
+%>
+namespace iss {
+namespace interp {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#if defined(WITH_LLVM)
+namespace llvm {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_TCC)
+namespace tcc {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_ASMJIT)
+namespace asmjit {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+}
+// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -0,0 +1,361 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/asmjit/vm_base.h>
+#include <asmjit/asmjit.h>
+#include <util/logging.h>
+#include <vm/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace asmjit {
+
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::asmjit;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::asmjit::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using mem_type_e = typename super::mem_type_e;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using super::get_ptr_for;
+    using super::get_reg_for;
+    using super::get_reg_for_Gp;
+    using super::load_reg_from_mem;
+    using super::load_reg_from_mem_Gp;
+    using super::write_reg_to_mem;
+    using super::gen_read_mem;
+    using super::gen_write_mem;
+    using super::gen_wait;
+    using super::gen_leave;
+    using super::gen_sync;
+   
+    using this_class = vm_impl<ARCH>;
+    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
+
+    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    void gen_block_prologue(jit_holder& jh) override;
+    void gen_block_epilogue(jit_holder& jh) override;
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    void gen_instr_prologue(jit_holder& jh);
+    void gen_instr_epilogue(jit_holder& jh);
+    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
+    template <typename T, typename = std::enable_if_t<std::is_integral_v<T>>> void gen_set_tval(jit_holder& jh, T new_tval) ;
+    void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
+
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    } 
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate disass */
+            <%instr.disass.eachLine{%>
+            ${it}<%}%>
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
+        }
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, ${idx});
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc+${instr.length/8};
+        mov(cc, jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        gen_sync(jh, POST_SYNC, ${idx});
+        gen_instr_epilogue(jh);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
+        x86::Compiler& cc = jh.cc;
+        if(this->disass_enabled){          
+            auto mnemonic = std::string("illegal_instruction");
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+        }
+        cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, instr_descr.size());
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        mov(cc, jh.next_pc, pc.val);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_raise(jh, 0, 2);
+        gen_sync(jh, POST_SYNC, instr_descr.size());
+        gen_instr_epilogue(jh);
+        return BRANCH;
+    }
+};
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok)
+        throw trap_access(TRAP_ID, pc.val);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
+        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) 
+        f = &this_class::illegal_instruction;
+    return (this->*f)(pc, instr, jh);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_prologue");
+
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
+
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_epilogue");
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cmp(cc, current_trap_state, 0);
+    cc.jne(jh.trap_entry);
+    cc.inc(get_ptr_for(jh, traits::ICOUNT));
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
+    jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
+    jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
+    jh.globals["tval"] = get_reg_Gp(jh.cc, 64, false);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
+    x86::Compiler& cc = jh.cc;
+    cc.comment("//gen_block_epilogue");
+    cc.ret(jh.next_pc);
+
+    cc.bind(jh.trap_entry);
+    this->write_back(jh);
+
+    x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+
+    x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
+    mov(cc, current_pc, get_ptr_for(jh, traits::PC));
+
+    cc.comment("//enter trap call;");
+    InvokeNode* call_enter_trap;
+    cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
+    call_enter_trap->setArg(0, jh.arch_if_ptr);
+    call_enter_trap->setArg(1, current_trap_state);
+    call_enter_trap->setArg(2, current_pc);
+    call_enter_trap->setArg(3, jh.globals["tval"]);
+
+    x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
+    mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
+    mov(cc, jh.next_pc, current_next_pc);
+
+    mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
+    cc.ret(jh.next_pc);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
+    auto& cc = jh.cc;
+    cc.comment("//gen_raise");
+    auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
+    mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+}
+template <typename ARCH>
+template <typename T, typename>
+void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
+        mov(jh.cc, jh.globals["tval"], new_tval);
+    }
+template <typename ARCH>
+void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
+    if(std::holds_alternative<x86::Gp>(_new_tval)) {
+        x86::Gp new_tval = std::get<x86::Gp>(_new_tval);
+        if(new_tval.size() < 8)
+            new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
+        mov(jh.cc, jh.globals["tval"], new_tval);
+    } else {
+        throw std::runtime_error("Variant not supported in gen_set_tval");
+    }
+}
+
+} // namespace tgc5c
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace asmjit
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,15 +29,23 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
-#include "../fp_functions.h"
+<%
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+}
+%>
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
+#include <vm/fp_functions.h>
 #include <util/logging.h>
+#include <boost/coroutine2/all.hpp>
+#include <functional>
+#include <exception>
+#include <vector>
 #include <sstream>
 
 #ifndef FMT_HEADER_ONLY
@@ -53,6 +61,11 @@ namespace interp {
 namespace ${coreDef.name.toLowerCase()} {
 using namespace iss::arch;
 using namespace iss::debugger;
+using namespace std::placeholders;
+
+struct memory_access_exception : public std::exception{
+    memory_access_exception(){}
+};
 
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
@@ -64,6 +77,7 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
     
     vm_impl();
 
@@ -83,34 +97,15 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
 
-    compile_func decode_inst(code_word_t instr) ;
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        compile_func opc;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->core.reg.trap_state = trap_val;
     }
 
     inline void leave(unsigned lvl){
@@ -121,44 +116,17 @@ protected:
         this->core.wait_until(type);
     }
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    inline void set_tval(uint64_t new_tval){
+        tval = new_tval;
     }
+
+    uint64_t fetch_count{0};
+    uint64_t tval{0};
+
+    using yield_t = boost::coroutines2::coroutine<void>::push_type;
+    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
+    std::vector<coro_t> spawn_blocks;
+
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -166,95 +134,114 @@ protected:
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
     
+    inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
+             if(*it){
+                 (*it)();
+                 ++it;
+             } else
+                 spawn_blocks.erase(it);
+    }
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
+
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
+    struct instruction_descriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
-        compile_func op;
+        typename arch::traits<ARCH>::opcode_e op;
+    };
+    struct decoding_tree_node{
+        std::vector<instruction_descriptor> instrs;
+        std::vector<decoding_tree_node*> children;
+        uint32_t submask = std::numeric_limits<uint32_t>::max();
+        uint32_t value;
+        decoding_tree_node(uint32_t value) : value(value){}
     };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    decoding_tree_node* root {nullptr};
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */
-            <%instr.disass.eachLine{%>${it}
-            <%}%>
-        }
-        // used registers<%instr.usedVariables.each{ k,v->
-            if(v.isArray) {%>
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-        <%}}%>// calculate next pc value
-        *NEXT_PC = *PC + ${instr.length/8};
-        // execute instruction
-        try {
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>} catch(...){}
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  2);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-
-    static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        auto phys_pc = this->core.v2p(pc);
+        if(this->core.has_mmu()) {
+            auto phys_pc = this->core.virt2phys(pc);
 //            if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
 //                if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
 //                if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
+//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
+//                        return iss::Err;
 //            } else {
-            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
+                if (this->core.read(phys_pc, 4, data) != iss::Ok)
+                    return iss::Err;
 //            }
+        } else {
+            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
+                return iss::Err;
+
+        }
         return iss::Ok;
     }
+    
+    void populate_decoding_tree(decoding_tree_node* root){
+        //create submask
+        for(auto instr: root->instrs){
+            root->submask &= instr.mask;
+        }
+        //put each instr according to submask&encoding into children
+        for(auto instr: root->instrs){
+            bool foundMatch = false;
+            for(auto child: root->children){
+                //use value as identifying trait
+                if(child->value == (instr.value&root->submask)){
+                    child->instrs.push_back(instr);
+                    foundMatch = true;
+                }
+            }
+            if(!foundMatch){
+                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
+                child->instrs.push_back(instr);
+                root->children.push_back(child);
+            }
+        }
+        root->instrs.clear();
+        //call populate_decoding_tree for all children
+        if(root->children.size() >1)
+            for(auto child: root->children){
+                populate_decoding_tree(child);      
+            }
+        else{
+            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
+            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
+            return instr1.mask > instr2.mask;
+            }); 
+        }
+    }
+
+    typename arch::traits<ARCH>::opcode_e  decode_instr(decoding_tree_node* node, code_word_t word){
+        if(!node->children.size()){
+            if(node->instrs.size() == 1) return node->instrs[0].op;
+            for(auto instr : node->instrs){
+                if((instr.mask&word) == instr.value) return instr.op;
+            }
+        }
+        else{
+            for(auto child : node->children){
+                if (child->value == (node->submask&word)){
+                    return decode_instr(child, word);
+                }  
+            }  
+        }
+        return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+    }
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -281,19 +268,19 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
+    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
     for(auto instr:instr_descr){
-        auto quadrant = instr.value & 0x3;
-        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-    }
-    for(auto& lut: qlut){
-        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-            return bit_count(a.mask) > bit_count(b.mask);
-        });
+        root->instrs.push_back(instr);
     }
+    populate_decoding_tree(root);
 }
 
-inline bool is_count_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
+inline bool is_icount_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
+}
+
+inline bool is_fcount_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
 }
 
 inline bool is_jump_to_self_enabled(finish_cond_e cond){
@@ -301,36 +288,80 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
-    for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.opc;
-    }
-    return &this_class::illegal_intruction;
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
-    // we fetch at max 4 byte, alignment is 2
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
     auto pc=start;
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto& trap_state = this->core.reg.trap_state;
+    auto& icount =  this->core.reg.icount;
+    auto& cycle =  this->core.reg.cycle;
+    auto& instret =  this->core.reg.instret;
+    auto& instr =  this->core.reg.instruction;
+    // we fetch at max 4 byte, alignment is 2
+    auto *const data = reinterpret_cast<uint8_t*>(&instr);
+
     while(!this->core.should_stop() &&
-            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        auto res = fetch_ins(pc, data);
-        if(res!=iss::Ok){
+            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
+            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
+        fetch_count++;
+        if(fetch_ins(pc, data)!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto f = decode_inst(insn);
-            pc = (this->*f)(pc, insn);
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto inst_id = decode_instr(root, instr);
+            // pre execution stuff
+             this->core.reg.last_branch = 0;
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            try{
+                switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
+                case arch::traits<ARCH>::opcode_e::${instr.name}: {
+                    <%instr.fields.eachLine{%>${it}
+                    <%}%>if(this->disass_enabled){
+                        /* generate console output when executing the command */<%instr.disass.eachLine{%>
+                        ${it}<%}%>
+                    }
+                    // used registers<%instr.usedVariables.each{ k,v->
+                    if(v.isArray) {%>
+                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+                    auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+                    <%}}%>// calculate next pc value
+                    *NEXT_PC = *PC + ${instr.length/8};
+                    // execute instruction<%instr.behavior.eachLine{%>
+                    ${it}<%}%>
+                    break;
+                }// @suppress("No break at end of case")<%}%>
+                default: {
+                    *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                    raise(0,  2);
+                }
+                }
+            }catch(memory_access_exception& e){}
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
+            // trap check
+            if(trap_state!=0){
+                //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
+                auto mcause = (trap_state>>16) & 0xff; 
+                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
+            } else {
+                icount++;
+                instret++;
+            }
+            cycle++;
+            pc.val=*NEXT_PC;
+            this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
     }
     return pc;
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -340,3 +371,34 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace interp
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+#include <util/logging.h>
+#include <vm/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
+}
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::llvm;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::llvm::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    template <typename T> inline ConstantInt *size(T type) {
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
+    }
+
+    void setup_module(Module* m) override {
+        super::setup_module(m);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
+    }
+
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
+        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
+    }
+
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
+    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
+    void gen_leave_trap(unsigned lvl);
+    void gen_wait(unsigned type);
+    void set_tval(uint64_t new_tval);
+    void set_tval(Value* new_tval);
+    void gen_trap_behavior(BasicBlock *) override;
+    void gen_instr_prologue();
+    void gen_instr_epilogue(BasicBlock *bb);
+
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
+        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
+    }
+
+    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+                                                           this->get_type(traits::XLEN));
+        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
+    }
+
+    // some compile time constants
+
+    using this_class = vm_impl<ARCH>;
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }   
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
+            ${it}<%}%>
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,${idx});
+        
+        this->gen_set_pc(pc, traits::PC);
+        this->set_tval(instr);
+        pc=pc+ ${instr.length/8};
+        this->gen_set_pc(pc, traits::NEXT_PC);
+        
+        this->gen_instr_prologue();
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        this->gen_sync(POST_SYNC, ${idx});
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+        if(this->disass_enabled){
+            auto mnemonic = std::string("illegal_instruction");
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
+                                   get_reg_ptr(traits::PC), true);
+        this->builder.CreateStore(
+            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
+                                     this->gen_const(64U, 1)),
+            get_reg_ptr(traits::ICOUNT), true);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        this->set_tval(instr);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        bb = this->leave_blk;
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+        return std::make_tuple(BRANCH, nullptr);
+    }    
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) {
+        f = &this_class::illegal_instruction;
+    }
+    return (this->*f)(pc, instr, this_block);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+    this->builder.SetInsertPoint(leave_blk);
+    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
+    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
+    this->builder.CreateCall(this->mod->getFunction("wait"), args);
+}
+
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
+    auto tmp_tval = this->gen_const(64, tval);
+    this->set_tval(tmp_tval);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
+    this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
+}
+template <typename ARCH> 
+void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+    this->builder.SetInsertPoint(trap_blk);
+    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
+    std::vector<Value *> args{this->core_ptr,
+                                this->adj_to64(trap_state_val),
+                                this->adj_to64(cur_pc_val),
+                              this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
+    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+
+    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
+    this->builder.CreateRet(trap_addr_val);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue() {
+    auto* trap_val =
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
+    this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
+}
+            
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
+    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
+    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          target_bb, this->trap_blk, 1);
+    this->builder.SetInsertPoint(target_bb);
+    // update icount
+    auto* icount_val = this->builder.CreateAdd(
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
+    this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
+}
+
+} // namespace ${coreDef.name.toLowerCase()}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace llvm
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -1,325 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::llvm;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
-public:
-    using super = typename iss::llvm::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
-
-    template <typename T> inline ConstantInt *size(T type) {
-        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
-    }
-
-    void setup_module(Module* m) override {
-        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
-    }
-
-    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
-    }
-
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
-
-    void gen_leave_behavior(BasicBlock *leave_blk) override;
-
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-
-    void gen_leave_trap(unsigned lvl);
-
-    void gen_wait(unsigned type);
-
-    void gen_trap_behavior(BasicBlock *) override;
-
-    void gen_trap_check(BasicBlock *bb);
-
-    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(get_reg_ptr(i), false);
-    }
-
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
-                                                           this->get_type(traits<ARCH>::XLEN));
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
-    }
-
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
-                                                                                  code_word_t instr,
-                                                                                  BasicBlock *bb);
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-	std::array<compile_func *, 4> qlut;
-
-	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
-    	${it}<%}%>
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
-		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
-                                   get_reg_ptr(traits<ARCH>::PC), true);
-        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
-                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->gen_raise_trap(0, 2);     // illegal instruction trap
-		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        this->gen_trap_check(this->leave_blk);
-        return std::make_tuple(BRANCH, nullptr);
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
-}
-
-template <typename ARCH>
-std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-    // curr pc on stack
-    ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
-    if (f == nullptr) {
-        f = &this_class::illegal_intruction;
-    }
-    return (this->*f)(pc, insn, this_block);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
-    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
-    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateRet(trap_addr_val);
-}
-
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
-    this->gen_cond_branch(this->builder.CreateICmp(
-                              ICmpInst::ICMP_EQ, v,
-                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          bb, this->trap_blk, 1);
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace llvm
-} // namespace iss

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2020 MINRES Technologies GmbH
+ * Copyright (C) 2020-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,15 +29,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/tcc/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
+#include <vm/instruction_decoder.h>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -55,10 +55,12 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
     using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
+    using mem_type_e  = typename traits::mem_type_e;    
     using addr_t      = typename super::addr_t;
     using tu_builder  = typename super::tu_builder;
 
@@ -82,7 +84,7 @@ protected:
     using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
     void setup_module(std::string m) override {
         super::setup_module(m);
@@ -98,16 +100,20 @@ protected:
 
     void gen_wait(tu_builder& tu, unsigned type);
 
+    inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
+
+    inline void gen_set_tval(tu_builder& tu, value new_tval);
+
     inline void gen_trap_check(tu_builder& tu) {
         tu("if(*trap_state!=0) goto trap_entry;");
     }
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
         switch(reg_num){
-        case traits<ARCH>::NEXT_PC:
+        case traits::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
-        case traits<ARCH>::PC:
+        case traits::PC:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
@@ -119,167 +125,158 @@ protected:
         }
     }
 
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
     
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    std::array<compile_func *, 4> qlut;
-
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
 
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
+    struct instruction_descriptor {
+        uint32_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
 
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+        tu("${instr.name}_{:#010x}:", pc.val);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
         }
+        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
+        pc=pc+ ${instr.length/8};
+        gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu.open_scope();
+        this->gen_set_tval(tu, instr);
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        tu.close_scope();
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);        
+        return returnValue;
+    }
     <%}%>
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
         vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
+        }
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         gen_raise_trap(tu, 0, 2);     // illegal instruction trap
+        this->gen_set_tval(tu, instr);
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
         }
+        return std::move(g_instr_descr);
+    }()) {}
 
 template <typename ARCH>
 std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    code_word_t instr = 0;
     phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
     if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
     if (f == nullptr) {
-        f = &this_class::illegal_intruction;
+        f = &this_class::illegal_instruction;
     }
-    return (this->*f)(pc, insn, tu);
+    return (this->*f)(pc, instr, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
 }
 
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
+    tu(fmt::format("tval = {};", new_tval));
+}
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
+    tu(fmt::format("tval = {};", new_tval.str));
+}
+
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    this->gen_sync(tu, POST_SYNC, -1);    
+    tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -287,5 +284,36 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-}
+} // namesapce tcc
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

incl/iss/arch/.gitignore

@@ -1 +0,0 @@
-/tgc_*.h

incl/iss/arch/riscv_hart_m_p.h

@@ -1,976 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial implementation
- ******************************************************************************/
-
-#ifndef _RISCV_HART_M_P_H
-#define _RISCV_HART_M_P_H
-
-#include "riscv_hart_common.h"
-#include "iss/arch/traits.h"
-#include "iss/instrumentation_if.h"
-#include "iss/log_categories.h"
-#include "iss/vm_if.h"
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <array>
-#include <elfio/elfio.hpp>
-#include <fmt/format.h>
-#include <iomanip>
-#include <sstream>
-#include <type_traits>
-#include <unordered_map>
-#include <functional>
-#include <util/bit_field.h>
-#include <util/ities.h>
-#include <util/sparse_array.h>
-
-#if defined(__GNUC__)
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#else
-#define likely(x) x
-#define unlikely(x) x
-#endif
-
-namespace iss {
-namespace arch {
-
-template <typename BASE> class riscv_hart_m_p : public BASE {
-protected:
-    const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-    const std::array<const char *, 16> trap_str = {{""
-                                              "Instruction address misaligned", // 0
-                                              "Instruction access fault",       // 1
-                                              "Illegal instruction",            // 2
-                                              "Breakpoint",                     // 3
-                                              "Load address misaligned",        // 4
-                                              "Load access fault",              // 5
-                                              "Store/AMO address misaligned",   // 6
-                                              "Store/AMO access fault",         // 7
-                                              "Environment call from U-mode",   // 8
-                                              "Environment call from S-mode",   // 9
-                                              "Reserved",                       // a
-                                              "Environment call from M-mode",   // b
-                                              "Instruction page fault",         // c
-                                              "Load page fault",                // d
-                                              "Reserved",                       // e
-                                              "Store/AMO page fault"}};
-    const std::array<const char *, 12> irq_str = {
-        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-public:
-    using core = BASE;
-    using this_class = riscv_hart_m_p<BASE>;
-    using phys_addr_t = typename core::phys_addr_t;
-    using reg_t = typename core::reg_t;
-    using addr_t = typename core::addr_t;
-
-    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
-    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
-
-    // primary template
-    template <class T, class Enable = void> struct hart_state {};
-    // specialization 32bit
-    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
-    public:
-        BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        BF_FIELD(SD, 31, 1);
-        // Trap SRET
-        BF_FIELD(TSR, 22, 1);
-        // Timeout Wait
-        BF_FIELD(TW, 21, 1);
-        // Trap Virtual Memory
-        BF_FIELD(TVM, 20, 1);
-        // Make eXecutable Readable
-        BF_FIELD(MXR, 19, 1);
-        // permit Supervisor User Memory access
-        BF_FIELD(SUM, 18, 1);
-        // Modify PRiVilege
-        BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        BF_FIELD(XS, 15, 2);
-        // floating-point unit status Off/Initial/Clean/Dirty
-        BF_FIELD(FS, 13, 2);
-        // machine previous privilege
-        BF_FIELD(MPP, 11, 2);
-        // supervisor previous privilege
-        BF_FIELD(SPP, 8, 1);
-        // previous machine interrupt-enable
-        BF_FIELD(MPIE, 7, 1);
-        // previous supervisor interrupt-enable
-        BF_FIELD(SPIE, 5, 1);
-        // previous user interrupt-enable
-        BF_FIELD(UPIE, 4, 1);
-        // machine interrupt-enable
-        BF_FIELD(MIE, 3, 1);
-        // supervisor interrupt-enable
-        BF_FIELD(SIE, 1, 1);
-        // user interrupt-enable
-        BF_FIELD(UIE, 0, 1);
-        END_BF_DECL();
-
-        mstatus_t mstatus;
-
-        static const reg_t mstatus_reset_val = 0x1800;
-
-        void write_mstatus(T val) {
-            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
-            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
-            mstatus = new_val;
-        }
-
-        static constexpr uint32_t get_mask() {
-            //return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
-            //       +-SD
-            //       |        +-TSR
-            //       |        |+-TW
-            //       |        ||+-TVM
-            //       |        |||+-MXR
-            //       |        ||||+-SUM
-            //       |        |||||+-MPRV
-            //       |        |||||| +-XS
-            //       |        |||||| | +-FS
-            //       |        |||||| | | +-MPP
-            //       |        |||||| | | |  +-SPP
-            //       |        |||||| | | |  |+-MPIE
-            //       |        ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
-        }
-    };
-    using hart_state_type = hart_state<reg_t>;
-
-    constexpr reg_t get_irq_mask() {
-        return 0b100010001000; // only machine mode is supported
-    }
-
-    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
-    }
-
-    riscv_hart_m_p();
-    virtual ~riscv_hart_m_p() = default;
-
-    void reset(uint64_t address) override;
-
-    std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
-
-    iss::status read(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
-
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
-
-    const reg_t& get_mhartid() const { return mhartid_reg;	}
-	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->reg.icount);
-    };
-
-    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
-
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
-    void set_csr(unsigned addr, reg_t val){
-        csr[addr & csr.page_addr_mask] = val;
-    }
-
-protected:
-    struct riscv_instrumentation_if : public iss::instrumentation_if {
-
-        riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
-        : arch(arch) {}
-        /**
-         * get the name of this architecture
-         *
-         * @return the name of this architecture
-         */
-        const std::string core_type_name() const override { return traits<BASE>::core_type; }
-
-        virtual uint64_t get_pc() { return arch.get_pc(); };
-
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
-
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
-
-        riscv_hart_m_p<BASE> &arch;
-    };
-
-    friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }
-
-    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
-    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
-
-    virtual iss::status read_csr(unsigned addr, reg_t &val);
-    virtual iss::status write_csr(unsigned addr, reg_t val);
-
-    hart_state_type state;
-    int64_t cycle_offset{0};
-    uint64_t mcycle_csr{0};
-    int64_t instret_offset{0};
-    uint64_t minstret_csr{0};
-    reg_t fault_data;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
-    riscv_instrumentation_if instr_if;
-
-    using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
-    using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
-    using csr_page_type = typename csr_type::page_type;
-    mem_type mem;
-    csr_type csr;
-    std::stringstream uart_buf;
-    std::unordered_map<reg_t, uint64_t> ptw;
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
-    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
-    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
-
-private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
-    iss::status read_null(unsigned addr, reg_t &val);
-    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
-    iss::status read_cycle(unsigned addr, reg_t &val);
-    iss::status write_cycle(unsigned addr, reg_t val);
-    iss::status read_instret(unsigned addr, reg_t &val);
-    iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_tvec(unsigned addr, reg_t &val);
-    iss::status read_time(unsigned addr, reg_t &val);
-    iss::status read_status(unsigned addr, reg_t &val);
-    iss::status write_status(unsigned addr, reg_t val);
-    iss::status write_cause(unsigned addr, reg_t val);
-    iss::status read_ie(unsigned addr, reg_t &val);
-    iss::status write_ie(unsigned addr, reg_t val);
-    iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ip(unsigned addr, reg_t val);
-    iss::status read_hartid(unsigned addr, reg_t &val);
-    iss::status write_epc(unsigned addr, reg_t val);
-
-    reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
-
-protected:
-    void check_interrupt();
-};
-
-template <typename BASE>
-riscv_hart_m_p<BASE>::riscv_hart_m_p()
-: state()
-, instr_if(*this) {
-    // reset values
-    csr[misa] = traits<BASE>::MISA_VAL;
-    csr[mvendorid] = 0x669;
-    csr[marchid] = 0x80000003;
-    csr[mimpid] = 1;
-
-    uart_buf.str("");
-    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
-        csr_rd_cb[addr] = &this_class::read_null;
-        //csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    // special handling & overrides
-    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
-    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
-    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
-
-    csr_rd_cb[mcycle] = &this_class::read_cycle;
-    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
-    csr_rd_cb[minstret] = &this_class::read_instret;
-    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
-    csr_rd_cb[mstatus] = &this_class::read_status;
-    csr_wr_cb[mstatus] = &this_class::write_status;
-    csr_wr_cb[mcause] = &this_class::write_cause;
-    csr_rd_cb[mtvec] = &this_class::read_tvec;
-    csr_wr_cb[mepc] = &this_class::write_epc;
-    csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_ip;
-    csr_rd_cb[mie] = &this_class::read_ie;
-    csr_wr_cb[mie] = &this_class::write_ie;
-    csr_rd_cb[mhartid] = &this_class::read_hartid;
-    csr_rd_cb[mcounteren] = &this_class::read_null;
-    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_wr_cb[misa] = &this_class::write_null;
-    csr_wr_cb[mvendorid] = &this_class::write_null;
-    csr_wr_cb[marchid] = &this_class::write_null;
-    csr_wr_cb[mimpid] = &this_class::write_null;
-}
-
-template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
-    FILE *fp = fopen(name.c_str(), "r");
-    if (fp) {
-        std::array<char, 5> buf;
-        auto n = fread(buf.data(), 1, 4, fp);
-        if (n != 4) throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if (reader.get_class() != ELFCLASS32)
-                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-            auto entry = reader.get_entry();
-            for (const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                            traits<BASE>::MEM, pseg->get_physical_address(),
-                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
-                    if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
-                                   << pseg->get_physical_address();
-                }
-            }
-            for(const auto sec : reader.sections) {
-                if(sec->get_name() == ".symtab") {
-                    if ( SHT_SYMTAB == sec->get_type() ||
-                            SHT_DYNSYM == sec->get_type() ) {
-                        ELFIO::symbol_section_accessor symbols( reader, sec );
-                        auto sym_no = symbols.get_symbols_num();
-                        std::string   name;
-                        ELFIO::Elf64_Addr    value   = 0;
-                        ELFIO::Elf_Xword     size    = 0;
-                        unsigned char bind    = 0;
-                        unsigned char type    = 0;
-                        ELFIO::Elf_Half      section = 0;
-                        unsigned char other   = 0;
-                        for ( auto i = 0U; i < sym_no; ++i ) {
-                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
-                            if(name=="tohost") {
-                                tohost = value;
-                            } else if(name=="fromhost") {
-                                fromhost = value;
-                            }
-                        }
-                    }
-                } else if (sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-
-            }
-            return std::make_pair(entry, true);
-        }
-        throw std::runtime_error("memory load file is not a valid elf file");
-    }
-    throw std::runtime_error("memory load file not found");
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, uint8_t *const data) {
-#ifndef NDEBUG
-    if (access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
-    } else if(access && iss::access_type::FETCH){
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
-    } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
-   }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
-                if(alignment>1 && (addr&(alignment-1))){
-                    this->reg.trap_state = 1<<31 | 4<<16;
-                    fault_data=addr;
-                    return iss::Err;
-                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)){
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
-                    fault_data=addr;
-                }
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                fault_data=ta.addr;
-                return iss::Err;
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            return iss::Ok;
-        } break;
-        case traits<BASE>::RES: {
-            auto it = atomic_reservation.find(addr);
-            if (it != atomic_reservation.end() && it->second != 0) {
-                memset(data, 0xff, length);
-                atomic_reservation.erase(addr);
-            } else
-                memset(data, 0, length);
-        } break;
-        default:
-            return iss::Err; // assert("Not supported");
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        fault_data=ta.addr;
-        return iss::Err;
-    }
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, const uint8_t *const data) {
-#ifndef NDEBUG
-    const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
-    switch (length) {
-    case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
-    }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
-                    this->reg.trap_state = 1<<31 | 6<<16;
-                    fault_data=addr;
-                    return iss::Err;
-                }
-                auto res = type==iss::address_type::PHYSICAL?
-                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) {
-                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
-                    fault_data=addr;
-                }
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                fault_data=ta.addr;
-                return iss::Err;
-            }
-
-            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-            if ((paddr.val + length) > mem.size()) return iss::Err;
-            switch (paddr.val) {
-            case 0x10013000: // UART0 base, TXFIFO reg
-            case 0x10023000: // UART1 base, TXFIFO reg
-                uart_buf << (char)data[0];
-                if (((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-                    // '"<<uart_buf.str()<<"'";
-                    std::cout << uart_buf.str();
-                    uart_buf.str("");
-                }
-                return iss::Ok;
-            case 0x10008000: { // HFROSC base, hfrosccfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                return iss::Ok;
-            }
-            case 0x10008008: { // HFROSC base, pllcfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                x |= 0x80; // set pll lock upon writing
-                return iss::Ok;
-            } break;
-            default: {}
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            switch (addr) {
-            case 2:
-            case 3: {
-                ptw.clear();
-                auto tvm = state.mstatus.TVM;
-                return iss::Ok;
-            }
-            }
-        } break;
-        case traits<BASE>::RES: {
-            atomic_reservation[addr] = data[0];
-        } break;
-        default:
-            return iss::Err;
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        fault_data=ta.addr;
-        return iss::Err;
-    }
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
-        throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_rd_cb.find(addr);
-    if (it == csr_rd_cb.end() || !it->second) // non existent register
-        throw illegal_instruction_fault(this->fault_data);
-    return (this->*(it->second))(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
-        throw illegal_instruction_fault(this->fault_data);
-    if((addr&0xc00)==0xc00) // writing to read-only region
-        throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_wr_cb.find(addr);
-    if (it == csr_wr_cb.end() || !it->second) // non existent register
-        throw illegal_instruction_fault(this->fault_data);
-    return (this->*(it->second))(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
-    val = csr[addr];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
-    val = 0;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
-    csr[addr] = val;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
-    if (addr == mcycle) {
-        val = static_cast<reg_t>(cycle_val);
-    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(cycle_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
-    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
-        mcycle_csr = static_cast<uint64_t>(val);
-    } else {
-        if (addr == mcycle) {
-            mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
-        } else  {
-            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
-        }
-    }
-    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
-    if ((addr&0xff) == (minstret&0xff)) {
-        val = static_cast<reg_t>(this->reg.instret);
-    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(this->reg.instret >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
-    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
-        this->reg.instret = static_cast<uint64_t>(val);
-    } else {
-        if ((addr&0xff) == (minstret&0xff)) {
-            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
-        } else  {
-            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
-        }
-    }
-    this->reg.instret--;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
-    if (addr == time) {
-        val = static_cast<reg_t>(time_val);
-    } else if (addr == timeh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(time_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
-    val = state.mstatus & hart_state_type::get_mask();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
-    state.write_mstatus(val);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
-    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
-    val = csr[mie];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
-    val = mhartid_reg;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    csr[mie] = (csr[mie] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
-    val = csr[mip];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    mask &= ~(1 << 7); // MTIP is read only
-    csr[mip] = (csr[mip] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
-    csr[addr] = val & get_pc_mask();
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
-    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->reg.icount > 30000) data[3] |= 0x80;
-    } break;
-    default: {
-        for(auto offs=0U; offs<length; ++offs) {
-            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
-        }
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
-    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
-        if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
-            uart_buf.str("");
-        }
-        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
-    default: {
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-        // tohost handling in case of riscv-test
-        if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
-                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            auto tohost_lower =
-                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-            if (tohost_lower || tohost_upper) {
-                uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
-                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
-                    switch (hostvar >> 48) {
-                    case 0:
-                        if (hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
-                        } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
-                        }
-                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
-                        this->interrupt_sim=hostvar;
-                        break;
-                        //throw(iss::simulation_stopped(hostvar));
-                    case 0x0101: {
-                        char c = static_cast<char>(hostvar & 0xff);
-                        if (c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
-                            uart_buf.str("");
-                        } else
-                            uart_buf << c;
-                        to_host_wr_cnt = 0;
-                    } break;
-                    default:
-                        break;
-                    }
-                } else if (tohost_lower)
-                    to_host_wr_cnt++;
-            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
-                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
-                uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
-                *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-            }
-        }
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
-    BASE::reset(address);
-    state.mstatus = hart_state_type::mstatus_reset_val;
-}
-
-template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
-    //auto ideleg = csr[mideleg];
-    // Multiple simultaneous interrupts and traps at the same privilege level are
-    // handled in the following decreasing priority order:
-    // external interrupts, software interrupts, timer interrupts, then finally
-    // any synchronous traps.
-    auto ena_irq = csr[mip] & csr[mie];
-
-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
-    auto enabled_interrupts = m_enabled ? ena_irq : 0;
-
-    if (enabled_interrupts != 0) {
-        int res = 0;
-        while ((enabled_interrupts & 1) == 0) {
-        	enabled_interrupts >>= 1;
-        	res++;
-        }
-        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
-    }
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
-    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
-    // calculate and write mcause val
-    auto trap_id = bit_sub<0, 16>(flags);
-    auto cause = bit_sub<16, 15>(flags);
-    if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
-    // calculate effective privilege level
-    if (trap_id == 0) { // exception
-        // store ret addr in xepc register
-        csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
-        csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
-        fault_data = 0;
-    } else {
-        csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
-        this->reg.pending_trap = 0;
-    }
-    csr[mcause] = (trap_id << 31) + cause;
-    // update mstatus
-    // xPP field of mstatus is written with the active privilege mode at the time
-    // of the trap; the x PIE field of mstatus
-    // is written with the value of the active interrupt-enable bit at the time of
-    // the trap; and the x IE field of mstatus
-    // is cleared
-    // store the actual privilege level in yPP and store interrupt enable flags
-    state.mstatus.MPP = PRIV_M;
-    state.mstatus.MPIE = state.mstatus.MIE;
-    state.mstatus.MIE = false;
-
-    // get trap vector
-    auto ivec = csr[mtvec];
-    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
-    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.PRIV = PRIV_M;
-    this->reg.trap_state = 0;
-    std::array<char, 32> buffer;
-#if defined(_MSC_VER)
-    sprintf(buffer.data(), "0x%016llx", addr);
-#else
-    sprintf(buffer.data(), "0x%016lx", addr);
-#endif
-    if((flags&0xffffffff) != 0xffffffff)
-    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                       << " at address " << buffer.data() << " occurred";
-    return this->reg.NEXT_PC;
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    state.mstatus.MIE = state.mstatus.MPIE;
-    state.mstatus.MPIE = 1;
-    // sets the pc to the value stored in the x epc register.
-    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
-    CLOG(INFO, disass) << "Executing xRET";
-    check_interrupt();
-    return this->reg.NEXT_PC;
-}
-
-} // namespace arch
-} // namespace iss
-
-#endif /* _RISCV_HART_M_P_H */

incl/iss/arch/tgc_c.h

@@ -1,282 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#ifndef _TGC_C_H_
-#define _TGC_C_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgc_c;
-
-template <> struct traits<tgc_c> {
-
-    constexpr static char const* const core_type = "TGC_C";
-    
-    static constexpr std::array<const char*, 35> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
- 
-    static constexpr std::array<const char*, 35> reg_aliases{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
-
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-    
-    enum class opcode_e : unsigned short {
-        LUI = 0,
-        AUIPC = 1,
-        JAL = 2,
-        JALR = 3,
-        BEQ = 4,
-        BNE = 5,
-        BLT = 6,
-        BGE = 7,
-        BLTU = 8,
-        BGEU = 9,
-        LB = 10,
-        LH = 11,
-        LW = 12,
-        LBU = 13,
-        LHU = 14,
-        SB = 15,
-        SH = 16,
-        SW = 17,
-        ADDI = 18,
-        SLTI = 19,
-        SLTIU = 20,
-        XORI = 21,
-        ORI = 22,
-        ANDI = 23,
-        SLLI = 24,
-        SRLI = 25,
-        SRAI = 26,
-        ADD = 27,
-        SUB = 28,
-        SLL = 29,
-        SLT = 30,
-        SLTU = 31,
-        XOR = 32,
-        SRL = 33,
-        SRA = 34,
-        OR = 35,
-        AND = 36,
-        FENCE = 37,
-        ECALL = 38,
-        EBREAK = 39,
-        URET = 40,
-        SRET = 41,
-        MRET = 42,
-        WFI = 43,
-        CSRRW = 44,
-        CSRRS = 45,
-        CSRRC = 46,
-        CSRRWI = 47,
-        CSRRSI = 48,
-        CSRRCI = 49,
-        MUL = 50,
-        MULH = 51,
-        MULHSU = 52,
-        MULHU = 53,
-        DIV = 54,
-        DIVU = 55,
-        REM = 56,
-        REMU = 57,
-        CADDI4SPN = 58,
-        CLW = 59,
-        CSW = 60,
-        CADDI = 61,
-        CNOP = 62,
-        CJAL = 63,
-        CLI = 64,
-        CLUI = 65,
-        CADDI16SP = 66,
-        __reserved_clui = 67,
-        CSRLI = 68,
-        CSRAI = 69,
-        CANDI = 70,
-        CSUB = 71,
-        CXOR = 72,
-        COR = 73,
-        CAND = 74,
-        CJ = 75,
-        CBEQZ = 76,
-        CBNEZ = 77,
-        CSLLI = 78,
-        CLWSP = 79,
-        CMV = 80,
-        CJR = 81,
-        __reserved_cmv = 82,
-        CADD = 83,
-        CJALR = 84,
-        CEBREAK = 85,
-        CSWSP = 86,
-        DII = 87,
-        MAX_OPCODE
-    };
-};
-
-struct tgc_c: public arch_if {
-
-    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
-    using reg_t =  typename traits<tgc_c>::reg_t;
-    using addr_t = typename traits<tgc_c>::addr_t;
-
-    tgc_c();
-    ~tgc_c();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-#pragma pack(push, 1)
-    struct TGC_C_regs { 
-        uint32_t X0 = 0; 
-        uint32_t X1 = 0; 
-        uint32_t X2 = 0; 
-        uint32_t X3 = 0; 
-        uint32_t X4 = 0; 
-        uint32_t X5 = 0; 
-        uint32_t X6 = 0; 
-        uint32_t X7 = 0; 
-        uint32_t X8 = 0; 
-        uint32_t X9 = 0; 
-        uint32_t X10 = 0; 
-        uint32_t X11 = 0; 
-        uint32_t X12 = 0; 
-        uint32_t X13 = 0; 
-        uint32_t X14 = 0; 
-        uint32_t X15 = 0; 
-        uint32_t X16 = 0; 
-        uint32_t X17 = 0; 
-        uint32_t X18 = 0; 
-        uint32_t X19 = 0; 
-        uint32_t X20 = 0; 
-        uint32_t X21 = 0; 
-        uint32_t X22 = 0; 
-        uint32_t X23 = 0; 
-        uint32_t X24 = 0; 
-        uint32_t X25 = 0; 
-        uint32_t X26 = 0; 
-        uint32_t X27 = 0; 
-        uint32_t X28 = 0; 
-        uint32_t X29 = 0; 
-        uint32_t X30 = 0; 
-        uint32_t X31 = 0; 
-        uint32_t PC = 0; 
-        uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0;
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t last_branch;
-    } reg;
-#pragma pack(pop)
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-    uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGC_C_H_ */

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-include(Common)
+#include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)
@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat ${LIB_SOURCES})
+add_library(softfloat STATIC ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)

softfloat/build/Linux-386-GCC/platform.h

@@ -50,4 +50,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-386-SSE2-GCC/platform.h

@@ -50,4 +50,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-ARM-VFPv2-GCC/platform.h

@@ -50,4 +50,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -54,4 +54,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #endif
 #include "opts-GCC.h"
-

softfloat/build/Win32-MinGW/platform.h

@@ -50,4 +50,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Win32-SSE2-MinGW/platform.h

@@ -50,4 +50,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Win64-MinGW-w64/platform.h

@@ -51,4 +51,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #include "opts-GCC.h"
-

softfloat/build/template-FAST_INT64/platform.h

@@ -47,4 +47,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     /*----------------------------------------------------------------------------
      *----------------------------------------------------------------------------*/
     == > #define THREAD_LOCAL _Thread_local
-

softfloat/build/template-not-FAST_INT64/platform.h

@@ -47,4 +47,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     /*----------------------------------------------------------------------------
      *----------------------------------------------------------------------------*/
     == > #define THREAD_LOCAL _Thread_local
-

softfloat/source/8086-SSE/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -149,8 +148,7 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -162,7 +160,8 @@ uint_fast32_t
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -184,8 +183,7 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +214,7 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -235,13 +232,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,9 +256,7 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
 
 #endif
 
 #endif
-

softfloat/source/8086/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -149,8 +148,7 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -162,7 +160,8 @@ uint_fast32_t
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -184,8 +183,7 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +214,7 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -235,13 +232,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,9 +256,7 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
 
 #endif
 
 #endif
-

softfloat/source/ARM-VFPv2-defaultNaN/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -73,7 +73,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | "Common NaN" structure, used to transfer NaN representations from one format
 | to another.
 *----------------------------------------------------------------------------*/
-struct commonNaN { char _unused; };
+struct commonNaN {
+    char _unused;
+};
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
@@ -93,7 +95,9 @@ struct commonNaN { char _unused; };
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f16UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&0x0200))                                                                                                                    \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
@@ -107,8 +111,7 @@ struct commonNaN { char _unused; };
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -128,7 +131,9 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f32UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&0x00400000))                                                                                                                \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
@@ -142,8 +147,7 @@ uint_fast16_t
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -155,7 +159,8 @@ uint_fast32_t
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -163,7 +168,9 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f64UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&UINT64_C(0x0008000000000000)))                                                                                              \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
@@ -177,8 +184,7 @@ uint_fast32_t
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -192,7 +198,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -208,7 +215,9 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                   \
+    if(!((uiA0)&UINT64_C(0x4000000000000000)))                                                                                             \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -217,8 +226,7 @@ uint_fast64_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE && !defined softfloat_commonNaNToExtF80UI
 INLINE
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
-{
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) {
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNExtF80UI64;
     uiZ.v0 = defaultNaNExtF80UI0;
@@ -237,13 +245,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -257,7 +259,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -266,7 +269,9 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                     \
+    if(!((uiA64)&UINT64_C(0x0000800000000000)))                                                                                            \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -274,8 +279,7 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE && !defined softfloat_commonNaNToF128UI
 INLINE
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
-{
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) {
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNF128UI64;
     uiZ.v0 = defaultNaNF128UI0;
@@ -294,13 +298,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
 
 #else
 
@@ -315,7 +313,9 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_extF80MToCommonNaN(aSPtr, zPtr)                                                                                          \
+    if(!((aSPtr)->signif & UINT64_C(0x4000000000000000)))                                                                                  \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -324,17 +324,12 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE && !defined softfloat_commonNaNToExtF80M
 INLINE
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
-{
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) {
     zSPtr->signExp = defaultNaNExtF80UI64;
     zSPtr->signif = defaultNaNExtF80UI0;
 }
 #else
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
 #endif
 
 /*----------------------------------------------------------------------------
@@ -343,12 +338,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -366,7 +356,9 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f128MToCommonNaN(aWPtr, zPtr)                                                                                            \
+    if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000)))                                                                          \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -376,17 +368,14 @@ void
 *----------------------------------------------------------------------------*/
 #if defined INLINE && !defined softfloat_commonNaNToF128M
 INLINE
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
-{
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) {
     zWPtr[indexWord(4, 3)] = defaultNaNF128UI96;
     zWPtr[indexWord(4, 2)] = defaultNaNF128UI64;
     zWPtr[indexWord(4, 1)] = defaultNaNF128UI32;
     zWPtr[indexWord(4, 0)] = defaultNaNF128UI0;
 }
 #else
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 #endif
 
 /*----------------------------------------------------------------------------
@@ -397,11 +386,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
 
 #endif
 
 #endif
-

softfloat/source/ARM-VFPv2/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -149,8 +148,7 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -162,7 +160,8 @@ uint_fast32_t
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -184,8 +183,7 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +214,7 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -235,13 +232,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,9 +256,7 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
 
 #endif
 
 #endif
-

softfloat/source/RISCV/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -149,8 +148,7 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
@@ -162,7 +160,8 @@ uint_fast32_t
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -184,8 +183,7 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,9 +214,7 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -235,13 +232,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,9 +256,7 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
 
 #endif
 
 #endif
-

softfloat/source/include/internals.h

@@ -37,33 +37,43 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef internals_h
 #define internals_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitives.h"
 #include "softfloat_types.h"
+#include <stdbool.h>
+#include <stdint.h>
 
-union ui16_f16 { uint16_t ui; float16_t f; };
-union ui32_f32 { uint32_t ui; float32_t f; };
-union ui64_f64 { uint64_t ui; float64_t f; };
+union ui16_f16 {
+    uint16_t ui;
+    float16_t f;
+};
+union ui32_f32 {
+    uint32_t ui;
+    float32_t f;
+};
+union ui64_f64 {
+    uint64_t ui;
+    float64_t f;
+};
 
 #ifdef SOFTFLOAT_FAST_INT64
-union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; };
-union ui128_f128 { struct uint128 ui; float128_t f; };
+union extF80M_extF80 {
+    struct extFloat80M fM;
+    extFloat80_t f;
+};
+union ui128_f128 {
+    struct uint128 ui;
+    float128_t f;
+};
 #endif
 
-enum {
-    softfloat_mulAdd_subC    = 1,
-    softfloat_mulAdd_subProd = 2
-};
+enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 };
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
 uint_fast32_t softfloat_roundToUI32(bool, uint_fast64_t, uint_fast8_t, bool);
 
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast64_t
- softfloat_roundToUI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
 #else
 uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool);
 #endif
@@ -71,9 +81,7 @@ uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 int_fast32_t softfloat_roundToI32(bool, uint_fast64_t, uint_fast8_t, bool);
 
 #ifdef SOFTFLOAT_FAST_INT64
-int_fast64_t
- softfloat_roundToI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
 #else
 int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool);
 #endif
@@ -87,7 +95,10 @@ int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
 
 #define isNaNF16UI(a) (((~(a)&0x7C00) == 0) && ((a)&0x03FF))
 
-struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; };
+struct exp8_sig16 {
+    int_fast8_t exp;
+    uint_fast16_t sig;
+};
 struct exp8_sig16 softfloat_normSubnormalF16Sig(uint_fast16_t);
 
 float16_t softfloat_roundPackToF16(bool, int_fast16_t, uint_fast16_t);
@@ -95,9 +106,7 @@ float16_t softfloat_normRoundPackToF16( bool, int_fast16_t, uint_fast16_t );
 
 float16_t softfloat_addMagsF16(uint_fast16_t, uint_fast16_t);
 float16_t softfloat_subMagsF16(uint_fast16_t, uint_fast16_t);
-float16_t
- softfloat_mulAddF16(
-     uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
+float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t);
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
@@ -108,7 +117,10 @@ float16_t
 
 #define isNaNF32UI(a) (((~(a)&0x7F800000) == 0) && ((a)&0x007FFFFF))
 
-struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
+struct exp16_sig32 {
+    int_fast16_t exp;
+    uint_fast32_t sig;
+};
 struct exp16_sig32 softfloat_normSubnormalF32Sig(uint_fast32_t);
 
 float32_t softfloat_roundPackToF32(bool, int_fast16_t, uint_fast32_t);
@@ -116,9 +128,7 @@ float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );
 
 float32_t softfloat_addMagsF32(uint_fast32_t, uint_fast32_t);
 float32_t softfloat_subMagsF32(uint_fast32_t, uint_fast32_t);
-float32_t
- softfloat_mulAddF32(
-     uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t );
+float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t);
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
@@ -129,7 +139,10 @@ float32_t
 
 #define isNaNF64UI(a) (((~(a)&UINT64_C(0x7FF0000000000000)) == 0) && ((a)&UINT64_C(0x000FFFFFFFFFFFFF)))
 
-struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
+struct exp16_sig64 {
+    int_fast16_t exp;
+    uint_fast64_t sig;
+};
 struct exp16_sig64 softfloat_normSubnormalF64Sig(uint_fast64_t);
 
 float64_t softfloat_roundPackToF64(bool, int_fast16_t, uint_fast64_t);
@@ -137,9 +150,7 @@ float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );
 
 float64_t softfloat_addMagsF64(uint_fast64_t, uint_fast64_t, bool);
 float64_t softfloat_subMagsF64(uint_fast64_t, uint_fast64_t, bool);
-float64_t
- softfloat_mulAddF64(
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
@@ -154,22 +165,17 @@ float64_t
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
 
-struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
+struct exp32_sig64 {
+    int_fast32_t exp;
+    uint64_t sig;
+};
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig(uint_fast64_t);
 
-extFloat80_t
- softfloat_roundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
-extFloat80_t
- softfloat_normRoundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
+extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
 
-extFloat80_t
- softfloat_addMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
-extFloat80_t
- softfloat_subMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
+extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
@@ -180,67 +186,35 @@ extFloat80_t
 
 #define isNaNF128UI(a64, a0) (((~(a64)&UINT64_C(0x7FFF000000000000)) == 0) && (a0 || ((a64)&UINT64_C(0x0000FFFFFFFFFFFF))))
 
-struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
-struct exp32_sig128
- softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
+struct exp32_sig128 {
+    int_fast32_t exp;
+    struct uint128 sig;
+};
+struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t);
 
-float128_t
- softfloat_roundPackToF128(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t );
-float128_t
- softfloat_normRoundPackToF128(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t );
+float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t);
+float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t);
 
-float128_t
- softfloat_addMagsF128(
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
-float128_t
- softfloat_subMagsF128(
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
-float128_t
- softfloat_mulAddF128(
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast8_t
- );
+float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
+float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
 
 #else
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
 
-bool
- softfloat_tryPropagateNaNExtF80M(
-     const struct extFloat80M *,
-     const struct extFloat80M *,
-     struct extFloat80M *
- );
+bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*);
 void softfloat_invalidExtF80M(struct extFloat80M*);
 
 int softfloat_normExtF80SigM(uint64_t*);
 
-void
- softfloat_roundPackMToExtF80M(
-     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
-void
- softfloat_normRoundPackMToExtF80M(
-     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
+void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
 
-void
- softfloat_addExtF80M(
-     const struct extFloat80M *,
-     const struct extFloat80M *,
-     struct extFloat80M *,
-     bool
- );
+void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool);
 
-int
- softfloat_compareNonnormExtF80M(
-     const struct extFloat80M *, const struct extFloat80M * );
+int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*);
 
 /*----------------------------------------------------------------------------
  *----------------------------------------------------------------------------*/
@@ -251,9 +225,7 @@ int
 
 bool softfloat_isNaNF128M(const uint32_t*);
 
-bool
- softfloat_tryPropagateNaNF128M(
-     const uint32_t *, const uint32_t *, uint32_t * );
+bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*);
 void softfloat_invalidF128M(uint32_t*);
 
 int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*);
@@ -261,18 +233,9 @@ int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * );
 void softfloat_roundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*);
 void softfloat_normRoundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*);
 
-void
- softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool );
-void
- softfloat_mulAddF128M(
-     const uint32_t *,
-     const uint32_t *,
-     const uint32_t *,
-     uint32_t *,
-     uint_fast8_t
- );
+void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool);
+void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t);
 
 #endif
 
 #endif
-

softfloat/source/include/opts-GCC.h

@@ -39,57 +39,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifdef INLINE
 
-#include <stdint.h>
 #include "primitiveTypes.h"
+#include <stdint.h>
 
 #ifdef SOFTFLOAT_BUILTIN_CLZ
 
-INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
-    { return a ? __builtin_clz( a ) - 16 : 16; }
+INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; }
 #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
 
-INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
-    { return a ? __builtin_clz( a ) : 32; }
+INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; }
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 
-INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
-    { return a ? __builtin_clzll( a ) : 64; }
+INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; }
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 
 #endif
 
 #ifdef SOFTFLOAT_INTRINSIC_INT128
 
-INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = (unsigned __int128)a * ((uint_fast64_t)b << 32);
     return uZ.s;
 }
 #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
 
-INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = (unsigned __int128)a * b;
     return uZ.s;
 }
 #define softfloat_mul64To128 softfloat_mul64To128
 
 INLINE
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
-{
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
+    union {
+        unsigned __int128 ui;
+        struct uint128 s;
+    } uZ;
     uZ.ui = ((unsigned __int128)a64 << 64 | a0) * b;
     return uZ.s;
 }
 #define softfloat_mul128By32 softfloat_mul128By32
 
 INLINE
-void
- softfloat_mul128To256M(
-     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
-{
+void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) {
     unsigned __int128 z0, mid1, mid, z128;
     z0 = (unsigned __int128)a0 * b0;
     mid1 = (unsigned __int128)a64 * b0;
@@ -111,4 +111,3 @@ void
 #endif
 
 #endif
-

softfloat/source/include/primitiveTypes.h

@@ -42,13 +42,27 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifdef SOFTFLOAT_FAST_INT64
 
 #ifdef LITTLEENDIAN
-struct uint128 { uint64_t v0, v64; };
-struct uint64_extra { uint64_t extra, v; };
-struct uint128_extra { uint64_t extra; struct uint128 v; };
+struct uint128 {
+    uint64_t v0, v64;
+};
+struct uint64_extra {
+    uint64_t extra, v;
+};
+struct uint128_extra {
+    uint64_t extra;
+    struct uint128 v;
+};
 #else
-struct uint128 { uint64_t v64, v0; };
-struct uint64_extra { uint64_t v, extra; };
-struct uint128_extra { struct uint128 v; uint64_t extra; };
+struct uint128 {
+    uint64_t v64, v0;
+};
+struct uint64_extra {
+    uint64_t v, extra;
+};
+struct uint128_extra {
+    struct uint128 v;
+    uint64_t extra;
+};
 #endif
 
 #endif
@@ -67,7 +81,8 @@ struct uint128_extra { struct uint128 v; uint64_t extra; };
 #define indexMultiwordLo(total, n) 0
 #define indexMultiwordHiBut(total, n) (n)
 #define indexMultiwordLoBut(total, n) 0
-#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 }
+#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+    { v0, v1, v2, v3 }
 #else
 #define wordIncr -1
 #define indexWord(total, n) ((total)-1 - (n))
@@ -78,8 +93,8 @@ struct uint128_extra { struct uint128 v; uint64_t extra; };
 #define indexMultiwordLo(total, n) ((total) - (n))
 #define indexMultiwordHiBut(total, n) 0
 #define indexMultiwordLoBut(total, n) (n)
-#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 }
+#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+    { v3, v2, v1, v0 }
 #endif
 
 #endif
-

softfloat/source/include/primitives.h

@@ -37,9 +37,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef primitives_h
 #define primitives_h 1
 
+#include "primitiveTypes.h"
 #include <stdbool.h>
 #include <stdint.h>
-#include "primitiveTypes.h"
 
 #ifndef softfloat_shortShiftRightJam64
 /*----------------------------------------------------------------------------
@@ -50,8 +50,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
-    { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
+uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist) { return a >> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); }
 #else
 uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist);
 #endif
@@ -68,10 +67,8 @@ uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
-{
-    return
-        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
+INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) {
+    return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0);
 }
 #else
 uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist);
@@ -89,10 +86,8 @@ uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
-{
-    return
-        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
+INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) {
+    return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0);
 }
 #else
 uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist);
@@ -112,8 +107,7 @@ extern const uint_least8_t softfloat_countLeadingZeros8[256];
 | 'a'.  If 'a' is zero, 16 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
-{
+INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) {
     uint_fast8_t count = 8;
     if(0x100 <= a) {
         count = 0;
@@ -133,8 +127,7 @@ uint_fast8_t softfloat_countLeadingZeros16( uint16_t a );
 | 'a'.  If 'a' is zero, 32 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
-{
+INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) {
     uint_fast8_t count = 0;
     if(a < 0x10000) {
         count = 16;
@@ -222,8 +215,7 @@ uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
 INLINE
-bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return (a64 == b64) && (a0 == b0); }
+bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); }
 #else
 bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
@@ -237,8 +229,7 @@ bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
+bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
 bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
@@ -252,8 +243,7 @@ bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
+bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
 bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
@@ -266,17 +256,14 @@ bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
- softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
+struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
     struct uint128 z;
     z.v64 = a64 << dist | a0 >> (-dist & 63);
     z.v0 = a0 << dist;
     return z;
 }
 #else
-struct uint128
- softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
+struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
 #endif
 #endif
 
@@ -287,17 +274,14 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
- softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
+struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
     struct uint128 z;
     z.v64 = a64 >> dist;
     z.v0 = a64 << (-dist & 63) | a0 >> dist;
     return z;
 }
 #else
-struct uint128
- softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
+struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
 #endif
 #endif
 
@@ -308,19 +292,14 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra
- softfloat_shortShiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast8_t dist )
-{
+struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) {
     struct uint64_extra z;
     z.v = a >> dist;
     z.extra = a << (-dist & 63) | (extra != 0);
     return z;
 }
 #else
-struct uint64_extra
- softfloat_shortShiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast8_t dist );
+struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist);
 #endif
 #endif
 
@@ -334,22 +313,15 @@ struct uint64_extra
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128
- softfloat_shortShiftRightJam128(
-     uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
+struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
     uint_fast8_t negDist = -dist;
     struct uint128 z;
     z.v64 = a64 >> dist;
-    z.v0 =
-        a64<<(negDist & 63) | a0>>dist
-            | ((uint64_t) (a0<<(negDist & 63)) != 0);
+    z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0);
     return z;
 }
 #else
-struct uint128
- softfloat_shortShiftRightJam128(
-     uint64_t a64, uint64_t a0, uint_fast8_t dist );
+struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
 #endif
 #endif
 
@@ -360,10 +332,7 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128_extra
- softfloat_shortShiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
-{
+struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) {
     uint_fast8_t negDist = -dist;
     struct uint128_extra z;
     z.v.v64 = a64 >> dist;
@@ -372,9 +341,7 @@ struct uint128_extra
     return z;
 }
 #else
-struct uint128_extra
- softfloat_shortShiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist );
+struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist);
 #endif
 #endif
 
@@ -397,10 +364,7 @@ struct uint128_extra
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra
- softfloat_shiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast32_t dist )
-{
+struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) {
     struct uint64_extra z;
     if(dist < 64) {
         z.v = a >> dist;
@@ -413,9 +377,7 @@ struct uint64_extra
     return z;
 }
 #else
-struct uint64_extra
- softfloat_shiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast32_t dist );
+struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist);
 #endif
 #endif
 
@@ -430,8 +392,7 @@ struct uint64_extra
 | greater than 128, the result will be either 0 or 1, depending on whether the
 | original 128 bits are all zeros.
 *----------------------------------------------------------------------------*/
-struct uint128
- softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist );
+struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist);
 #endif
 
 #ifndef softfloat_shiftRightJam128Extra
@@ -452,9 +413,7 @@ struct uint128
 | is modified as described above and returned in the 'extra' field of the
 | result.)
 *----------------------------------------------------------------------------*/
-struct uint128_extra
- softfloat_shiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist );
+struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist);
 #endif
 
 #ifndef softfloat_shiftRightJam256M
@@ -470,9 +429,7 @@ struct uint128_extra
 | is greater than 256, the stored result will be either 0 or 1, depending on
 | whether the original 256 bits are all zeros.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shiftRightJam256M(
-     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr );
+void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr);
 #endif
 
 #ifndef softfloat_add128
@@ -483,17 +440,14 @@ void
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
+struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
     struct uint128 z;
     z.v0 = a0 + b0;
     z.v64 = a64 + b64 + (z.v0 < a0);
     return z;
 }
 #else
-struct uint128
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
 #endif
 
@@ -505,9 +459,7 @@ struct uint128
 | an array of four 64-bit elements that concatenate in the platform's normal
 | endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_add256M(
-     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
+void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
 #endif
 
 #ifndef softfloat_sub128
@@ -518,9 +470,7 @@ void
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
+struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
     struct uint128 z;
     z.v0 = a0 - b0;
     z.v64 = a64 - b64;
@@ -528,8 +478,7 @@ struct uint128
     return z;
 }
 #else
-struct uint128
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
 #endif
 
@@ -542,9 +491,7 @@ struct uint128
 | 64-bit elements that concatenate in the platform's normal endian order to
 | form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_sub256M(
-     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
+void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
 #endif
 
 #ifndef softfloat_mul64ByShifted32To128
@@ -552,8 +499,7 @@ void
 | Returns the 128-bit product of 'a', 'b', and 2^32.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
-{
+INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
     uint_fast64_t mid;
     struct uint128 z;
     mid = (uint_fast64_t)(uint32_t)a * b;
@@ -581,8 +527,7 @@ struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
-{
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
     struct uint128 z;
     uint_fast64_t mid;
     uint_fast32_t carry;
@@ -605,9 +550,7 @@ struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b );
 | Argument 'zPtr' points to an array of four 64-bit elements that concatenate
 | in the platform's normal endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_mul128To256M(
-     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr );
+void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr);
 #endif
 
 #else
@@ -638,8 +581,7 @@ int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr );
 | Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
 | concatenate in the platform's normal endian order to form a 128-bit integer.
 *----------------------------------------------------------------------------*/
-int_fast8_t
- softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr );
+int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
 #endif
 
 #ifndef softfloat_shortShiftLeft64To96M
@@ -652,19 +594,14 @@ int_fast8_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-void
- softfloat_shortShiftLeft64To96M(
-     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
-{
+void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr) {
     zPtr[indexWord(3, 0)] = (uint32_t)a << dist;
     a >>= 32 - dist;
     zPtr[indexWord(3, 2)] = a >> 32;
     zPtr[indexWord(3, 1)] = a;
 }
 #else
-void
- softfloat_shortShiftLeft64To96M(
-     uint64_t a, uint_fast8_t dist, uint32_t *zPtr );
+void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr);
 #endif
 #endif
 
@@ -678,13 +615,7 @@ void
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shortShiftLeftM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint_fast8_t dist,
-     uint32_t *zPtr
- );
+void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_shortShiftLeft96M
@@ -722,13 +653,7 @@ void
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shiftLeftM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
+void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_shiftLeft96M
@@ -765,13 +690,7 @@ void
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shortShiftRightM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint_fast8_t dist,
-     uint32_t *zPtr
- );
+void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_shortShiftRight128M
@@ -801,9 +720,7 @@ void
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shortShiftRightJamM(
-     uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * );
+void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*);
 #endif
 
 #ifndef softfloat_shortShiftRightJam160M
@@ -825,13 +742,7 @@ void
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shiftRightM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
+void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_shiftRight96M
@@ -856,13 +767,7 @@ void
 | is greater than N, the stored result will be either 0 or 1, depending on
 | whether the original N bits are all zeros.
 *----------------------------------------------------------------------------*/
-void
- softfloat_shiftRightJamM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
+void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_shiftRightJam96M
@@ -898,13 +803,7 @@ void
 | elements that concatenate in the platform's normal endian order to form an
 | N-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_addM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint32_t *zPtr
- );
+void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_add96M
@@ -940,14 +839,7 @@ void
 | points to a 'size_words'-long array of 32-bit elements that concatenate in
 | the platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-uint_fast8_t
- softfloat_addCarryM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint_fast8_t carry,
-     uint32_t *zPtr
- );
+uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_addComplCarryM
@@ -956,14 +848,8 @@ uint_fast8_t
 | the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed
 | before the addition.
 *----------------------------------------------------------------------------*/
-uint_fast8_t
- softfloat_addComplCarryM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint_fast8_t carry,
-     uint32_t *zPtr
- );
+uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry,
+                                      uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_addComplCarry96M
@@ -1052,13 +938,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
 | array of 32-bit elements that concatenate in the platform's normal endian
 | order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_subM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint32_t *zPtr
- );
+void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_sub96M
@@ -1104,9 +984,7 @@ void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr );
 | Argument 'zPtr' points to an array of eight 32-bit elements that concatenate
 | to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_mul128MTo256M(
-     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr );
+void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_remStepMBy32
@@ -1119,15 +997,8 @@ void
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
- softfloat_remStepMBy32(
-     uint_fast8_t size_words,
-     const uint32_t *remPtr,
-     uint_fast8_t dist,
-     const uint32_t *bPtr,
-     uint32_t q,
-     uint32_t *zPtr
- );
+void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q,
+                            uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_remStep96MBy32
@@ -1157,4 +1028,3 @@ void
 #endif
 
 #endif
-

softfloat/source/include/softfloat.h

@@ -34,7 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-
 /*============================================================================
 | Note:  If SoftFloat is made available as a general library for programs to
 | use, it is strongly recommended that a platform-specific version of this
@@ -42,13 +41,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | eliminates all dependencies on compile-time macros.
 *============================================================================*/
 
-
 #ifndef softfloat_h
 #define softfloat_h 1
 
+#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
-#include "softfloat_types.h"
 
 #ifndef THREAD_LOCAL
 #define THREAD_LOCAL
@@ -58,10 +56,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Software floating-point underflow tininess-detection mode.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum {
-    softfloat_tininess_beforeRounding = 0,
-    softfloat_tininess_afterRounding  = 1
-};
+enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 };
 
 /*----------------------------------------------------------------------------
 | Software floating-point rounding mode.  (Mode "odd" is supported only if
@@ -288,9 +283,7 @@ float16_t extF80M_to_f16( const extFloat80_t * );
 float32_t extF80M_to_f32(const extFloat80_t*);
 float64_t extF80M_to_f64(const extFloat80_t*);
 void extF80M_to_f128M(const extFloat80_t*, float128_t*);
-void
- extF80M_roundToInt(
-     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
+void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*);
 void extF80M_add(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
 void extF80M_sub(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
 void extF80M_mul(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
@@ -353,10 +346,7 @@ void f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * );
 void f128M_add(const float128_t*, const float128_t*, float128_t*);
 void f128M_sub(const float128_t*, const float128_t*, float128_t*);
 void f128M_mul(const float128_t*, const float128_t*, float128_t*);
-void
- f128M_mulAdd(
-     const float128_t *, const float128_t *, const float128_t *, float128_t *
- );
+void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*);
 void f128M_div(const float128_t*, const float128_t*, float128_t*);
 void f128M_rem(const float128_t*, const float128_t*, float128_t*);
 void f128M_sqrt(const float128_t*, float128_t*);
@@ -369,4 +359,3 @@ bool f128M_lt_quiet( const float128_t *, const float128_t * );
 bool f128M_isSignalingNaN(const float128_t*);
 
 #endif
-

softfloat/source/include/softfloat_types.h

@@ -47,10 +47,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | the types below may, if desired, be defined as aliases for the native types
 | (typically 'float' and 'double', and possibly 'long double').
 *----------------------------------------------------------------------------*/
-typedef struct { uint16_t v; } float16_t;
-typedef struct { uint32_t v; } float32_t;
-typedef struct { uint64_t v; } float64_t;
-typedef struct { uint64_t v[2]; } float128_t;
+typedef struct {
+    uint16_t v;
+} float16_t;
+typedef struct {
+    uint32_t v;
+} float32_t;
+typedef struct {
+    uint64_t v;
+} float64_t;
+typedef struct {
+    uint64_t v[2];
+} float128_t;
 
 /*----------------------------------------------------------------------------
 | The format of an 80-bit extended floating-point number in memory.  This
@@ -58,9 +66,15 @@ typedef struct { uint64_t v[2]; } float128_t;
 | named 'signif'.
 *----------------------------------------------------------------------------*/
 #ifdef LITTLEENDIAN
-struct extFloat80M { uint64_t signif; uint16_t signExp; };
+struct extFloat80M {
+    uint64_t signif;
+    uint16_t signExp;
+};
 #else
-struct extFloat80M { uint16_t signExp; uint64_t signif; };
+struct extFloat80M {
+    uint16_t signExp;
+    uint64_t signif;
+};
 #endif
 
 /*----------------------------------------------------------------------------
@@ -78,4 +92,3 @@ struct extFloat80M { uint16_t signExp; uint64_t signif; };
 typedef struct extFloat80M extFloat80_t;
 
 #endif
-

src-gen/.gitignore

@@ -0,0 +1,3 @@
+/iss
+/vm
+/sysc

src/iss/arch/hwl.h

@@ -0,0 +1,122 @@
+/*******************************************************************************
+ * Copyright (C) 2022 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_HWL_H
+#define _RISCV_HART_M_P_HWL_H
+
+#include "riscv_hart_common.h"
+#include <iss/vm_types.h>
+
+namespace iss {
+namespace arch {
+
+template <typename BASE> class hwl : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = hwl<BASE>;
+    using reg_t = typename BASE::reg_t;
+
+    hwl(feature_config cfg = feature_config{});
+    virtual ~hwl() = default;
+
+protected:
+    iss::status read_custom_csr_reg(unsigned addr, reg_t& val) override;
+    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
+};
+
+template <typename BASE>
+inline hwl<BASE>::hwl(feature_config cfg)
+: BASE(cfg) {
+    for(unsigned addr = 0x800; addr < 0x803; ++addr) {
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+    for(unsigned addr = 0x804; addr < 0x807; ++addr) {
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+}
+
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t& val) {
+    switch(addr) {
+    case 0x800:
+        val = this->reg.lpstart0;
+        break;
+    case 0x801:
+        val = this->reg.lpend0;
+        break;
+    case 0x802:
+        val = this->reg.lpcount0;
+        break;
+    case 0x804:
+        val = this->reg.lpstart1;
+        break;
+    case 0x805:
+        val = this->reg.lpend1;
+        break;
+    case 0x806:
+        val = this->reg.lpcount1;
+        break;
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+    switch(addr) {
+    case 0x800:
+        this->reg.lpstart0 = val;
+        break;
+    case 0x801:
+        this->reg.lpend0 = val;
+        break;
+    case 0x802:
+        this->reg.lpcount0 = val;
+        break;
+    case 0x804:
+        this->reg.lpstart1 = val;
+        break;
+    case 0x805:
+        this->reg.lpend1 = val;
+        break;
+    case 0x806:
+        this->reg.lpcount1 = val;
+        break;
+    }
+    return iss::Ok;
+}
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -35,26 +35,48 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
-#include "iss/arch_if.h"
 #include <cstdint>
+#include <elfio/elfio.hpp>
+#include <fmt/format.h>
+#include <iss/arch_if.h>
+#include <iss/log_categories.h>
+#include <string>
+#include <unordered_map>
+#include <util/logging.h>
+
+#if defined(__GNUC__)
+#define likely(x) ::__builtin_expect(!!(x), 1)
+#define unlikely(x) ::__builtin_expect(!!(x), 0)
+#else
+#define likely(x) x
+#define unlikely(x) x
+#endif
 
 namespace iss {
 namespace arch {
 
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
 
+enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
+
 enum riscv_csr {
     /* user-level CSR */
     // User Trap Setup
     ustatus = 0x000,
     uie = 0x004,
     utvec = 0x005,
+    utvt = 0x007, // CLIC
     // User Trap Handling
     uscratch = 0x040,
     uepc = 0x041,
     ucause = 0x042,
     utval = 0x043,
     uip = 0x044,
+    uxnti = 0x045,        // CLIC
+    uintstatus = 0xCB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh = 0x047,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw = 0x048,  // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
     // User Floating-Point CSRs
     fflags = 0x001,
     frm = 0x002,
@@ -112,11 +134,10 @@ enum riscv_csr {
     mtval = 0x343,
     mip = 0x344,
     mxnti = 0x345,        // CLIC
-    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus = 0xFB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh = 0x347,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
     mscratchcsw = 0x348,  // MRW Conditional scratch swap on priv mode change (CLIC)
     mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
-    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
@@ -164,10 +185,10 @@ enum riscv_csr {
     // Debug Mode Registers
     dcsr = 0x7B0,
     dpc = 0x7B1,
-    dscratch = 0x7B2
+    dscratch0 = 0x7B2,
+    dscratch1 = 0x7B3
 };
 
-
 enum {
     PGSHIFT = 12,
     PTE_PPN_SHIFT = 10,
@@ -185,7 +206,7 @@ enum {
 
 template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
 
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4 };
 
 enum {
     ISA_A = 1,
@@ -211,6 +232,17 @@ struct vm_info {
     bool is_active() { return levels; }
 };
 
+struct feature_config {
+    uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
+    unsigned clic_num_irq{16};
+    unsigned clic_num_trigger{0};
+    uint64_t tcm_base{0x10000000};
+    uint64_t tcm_size{0x8000};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+};
+
 class trap_load_access_fault : public trap_access {
 public:
     trap_load_access_fault(uint64_t badaddr)
@@ -236,7 +268,105 @@ public:
     trap_store_page_fault(uint64_t badaddr)
     : trap_access(15 << 16, badaddr) {}
 };
+
+inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t* const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch(offs & 0x3) {
+    case 0:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + i);
+        break;
+    case 1:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 1 + i);
+        break;
+    case 2:
+        for(auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 2 + i);
+        break;
+    case 3:
+        *data = *(reg_ptr + 3);
+        break;
     }
 }
 
+inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch(offs & 0x3) {
+    case 0:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + i) = *(data + i);
+        break;
+    case 1:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + 1 + i) = *(data + i);
+        break;
+    case 2:
+        for(auto i = 0U; i < length; ++i)
+            *(reg_ptr + 2 + i) = *(data + i);
+        break;
+    case 3:
+        *(reg_ptr + 3) = *data;
+        break;
+    }
+}
+struct riscv_hart_common {
+    riscv_hart_common(){};
+    ~riscv_hart_common(){};
+    std::unordered_map<std::string, uint64_t> symbol_table;
+
+    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
+        if(!symbol_table.empty())
+            return symbol_table;
+        FILE* fp = fopen(name.c_str(), "r");
+        if(fp) {
+            std::array<char, 5> buf;
+            auto n = fread(buf.data(), 1, 4, fp);
+            fclose(fp);
+            if(n != 4)
+                throw std::runtime_error("input file has insufficient size");
+            buf[4] = 0;
+            if(strcmp(buf.data() + 1, "ELF") == 0) {
+                // Create elfio reader
+                ELFIO::elfio reader;
+                // Load ELF data
+                if(!reader.load(name))
+                    throw std::runtime_error("could not process elf file");
+                // check elf properties
+                if(reader.get_type() != ET_EXEC)
+                    throw std::runtime_error("wrong elf type in file");
+                if(reader.get_machine() != EM_RISCV)
+                    throw std::runtime_error("wrong elf machine in file");
+                const auto sym_sec = reader.sections[".symtab"];
+                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
+                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
+                    auto sym_no = symbols.get_symbols_num();
+                    std::string name;
+                    ELFIO::Elf64_Addr value = 0;
+                    ELFIO::Elf_Xword size = 0;
+                    unsigned char bind = 0;
+                    unsigned char type = 0;
+                    ELFIO::Elf_Half section = 0;
+                    unsigned char other = 0;
+                    for(auto i = 0U; i < sym_no; ++i) {
+                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                        if(name != "") {
+                            this->symbol_table[name] = value;
+#ifndef NDEBUG
+                            CPPLOG(DEBUG) << "Found Symbol " << name;
+#endif
+                        }
+                    }
+                }
+                return symbol_table;
+            }
+            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
+        } else
+            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    };
+};
+
+} // namespace arch
+} // namespace iss
+
 #endif

src/iss/arch/tgc5c.cpp

@@ -30,28 +30,29 @@
  *
  *******************************************************************************/
 
+// clang-format off
+#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
 
-tgc_c::tgc_c() {
-    reg.icount = 0;
-}
+tgc5c::tgc5c()  = default;
 
-tgc_c::~tgc_c() = default;
+tgc5c::~tgc5c() = default;
 
-void tgc_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
+void tgc5c::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
@@ -59,11 +60,11 @@ void tgc_c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t *tgc_c::get_regs_base_ptr() {
+uint8_t *tgc5c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
+tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
 }
-
+// clang-format on

src/iss/arch/tgc_mapper.h

@@ -0,0 +1,57 @@
+#ifndef _ISS_ARCH_TGC_MAPPER_H
+#define _ISS_ARCH_TGC_MAPPER_H
+
+#include "riscv_hart_m_p.h"
+#include "tgc5c.h"
+using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
+#ifdef CORE_TGC5A
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5a.h>
+using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
+#endif
+#ifdef CORE_TGC5B
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5b.h>
+using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
+#endif
+#ifdef CORE_TGC5C_XRB_NN
+#include "hwl.h"
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5c_xrb_nn.h>
+using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
+#endif
+#ifdef CORE_TGC5D
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d.h>
+using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5D_XRB_MAC
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d_xrb_mac.h>
+using tgc5d_xrb_mac_plat_type =
+    iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac,
+                               (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5D_XRB_NN
+#include "hwl.h"
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d_xrb_nn.h>
+using tgc5d_xrb_nn_plat_type =
+    iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn,
+                                              (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
+#endif
+#ifdef CORE_TGC5E
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5e.h>
+using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5X
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5x.h>
+using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+#endif
+
+#endif

src/iss/arch/wt_cache.h

@@ -0,0 +1,171 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_WT_CACHE_H
+#define _RISCV_HART_M_P_WT_CACHE_H
+
+#include <iss/vm_types.h>
+#include <map>
+#include <memory>
+#include <util/ities.h>
+#include <vector>
+
+namespace iss {
+namespace arch {
+namespace cache {
+
+enum class state { INVALID, VALID };
+struct line {
+    uint64_t tag_addr{0};
+    state st{state::INVALID};
+    std::vector<uint8_t> data;
+    line(unsigned line_sz)
+    : data(line_sz) {}
+};
+struct set {
+    std::vector<line> ways;
+    set(unsigned ways_count, line const& l)
+    : ways(ways_count, l) {}
+};
+struct cache {
+    std::vector<set> sets;
+
+    cache(unsigned size, unsigned line_sz, unsigned ways) {
+        line const ref_line{line_sz};
+        set const ref_set{ways, ref_line};
+        sets.resize(size / (ways * line_sz), ref_set);
+    }
+};
+
+struct wt_policy {
+    bool is_cacheline_hit(cache& c);
+};
+} // namespace cache
+
+// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
+template <typename BASE> class wt_cache : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = wt_cache<BASE>;
+    using reg_t = typename BASE::reg_t;
+    using mem_read_f = typename BASE::mem_read_f;
+    using mem_write_f = typename BASE::mem_write_f;
+    using phys_addr_t = typename BASE::phys_addr_t;
+
+    wt_cache(feature_config cfg = feature_config{});
+    virtual ~wt_cache() = default;
+
+    unsigned size{4096};
+    unsigned line_sz{64};
+    unsigned ways{1};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+
+protected:
+    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t* const);
+    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const* const);
+    std::function<mem_read_f> cache_mem_rd_delegate;
+    std::function<mem_write_f> cache_mem_wr_delegate;
+    std::unique_ptr<cache::cache> dcache_ptr;
+    std::unique_ptr<cache::cache> icache_ptr;
+    size_t get_way_select() { return 0; }
+};
+
+template <typename BASE>
+inline wt_cache<BASE>::wt_cache(feature_config cfg)
+: BASE(cfg)
+, io_address{cfg.io_address}
+, io_addr_mask{cfg.io_addr_mask} {
+    auto cb = base_class::replace_mem_access(
+        [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l, d); },
+        [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l, d); });
+    cache_mem_rd_delegate = cb.first;
+    cache_mem_wr_delegate = cb.second;
+}
+
+template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+    if(!icache_ptr) {
+        icache_ptr.reset(new cache::cache(size, line_sz, ways));
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    }
+    if((a.val & io_addr_mask) != io_address) {
+        auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
+        auto tag_addr = a.val >> util::ilog2(line_sz);
+        auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr];
+        for(auto& cl : set.ways) {
+            if(cl.st == cache::state::VALID && cl.tag_addr == tag_addr) {
+                auto start_addr = a.val & (line_sz - 1);
+                for(auto i = 0U; i < l; ++i)
+                    d[i] = cl.data[start_addr + i];
+                return iss::Ok;
+            }
+        }
+        auto& cl = set.ways[get_way_select()];
+        phys_addr_t cl_addr{a};
+        cl_addr.val = tag_addr << util::ilog2(line_sz);
+        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
+        cl.tag_addr = tag_addr;
+        cl.st = cache::state::VALID;
+        auto start_addr = a.val & (line_sz - 1);
+        for(auto i = 0U; i < l; ++i)
+            d[i] = cl.data[start_addr + i];
+        return iss::Ok;
+    } else
+        return cache_mem_rd_delegate(a, l, d);
+}
+
+template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+    if(!dcache_ptr)
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    auto res = cache_mem_wr_delegate(a, l, d);
+    if(res == iss::Ok && ((a.val & io_addr_mask) != io_address)) {
+        auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
+        auto tag_addr = a.val >> util::ilog2(line_sz);
+        auto& set = dcache_ptr->sets[set_addr];
+        for(auto& cl : set.ways) {
+            if(cl.st == cache::state::VALID && cl.tag_addr == tag_addr) {
+                auto start_addr = a.val & (line_sz - 1);
+                for(auto i = 0U; i < l; ++i)
+                    cl.data[start_addr + i] = d[i];
+                break;
+            }
+        }
+    }
+    return res;
+}
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/debugger/riscv_target_adapter.h

@@ -84,8 +84,7 @@ public:
      target byte order. If  register is not available
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
-    status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
-                                std::vector<uint8_t> &avail_buf) override;
+    status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -103,8 +102,8 @@ public:
 
     status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
 
-    status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             size_t &num, bool &done) override;
+    status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
+                             bool& done) override;
 
     status current_thread_query(rp_thread_ref& thread) override;
 
@@ -120,12 +119,11 @@ public:
 
     status packetsize_query(std::string& out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                            std::function<void(unsigned)> stop_callback) override;
+    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string& out_buf) override;
 
@@ -158,9 +156,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  * set if all threads are processed.
  */
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
-                                                     bool &done) {
+status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result,
+                                                     size_t max_num, size_t& num, bool& done) {
     if(first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -176,9 +173,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
     return Ok;
 }
 
-template <typename ARCH>
-status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
-    LOG(TRACE) << "reading target registers";
+template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
+    CPPLOG(TRACE) << "reading target registers";
     // return idx<0?:;
     data.clear();
     avail.clear();
@@ -214,19 +210,32 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg = arch::traits<ARCH>::X0;
     auto* reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
+    bool e_ext = arch::traits<ARCH>::PC < 32;
     for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+        if(e_ext && reg_no > 15) {
+            if(reg_no == 32) {
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+                std::copy(iter, iter + reg_width, reg_base);
+            } else {
+                const uint64_t zero_val = 0;
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+                auto iter = (uint8_t*)&zero_val;
+                std::copy(iter, iter + reg_width, reg_base);
+            }
+        } else {
             auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
             auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
             std::copy(iter, iter + reg_width, reg_base);
             iter += 4;
             reg_base += offset;
         }
+    }
     return Ok;
 }
 
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-                                                        std::vector<uint8_t> &avail) {
+status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
     if(reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -247,8 +256,7 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
     return data.size() > 0 ? Ok : Err;
 }
 
-template <typename ARCH>
-status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
     if(reg_no < 65) {
         auto* reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
@@ -278,21 +286,16 @@ status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_th
     return NotSupported;
 }
 
-template <typename ARCH>
-status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
     text = 0;
     data = 0;
     bss = 0;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
-    return NotSupported;
-}
+template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
-    return NotSupported;
-}
+template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
     if(first) {
@@ -303,8 +306,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int
     return Ok;
 }
 
-template <typename ARCH>
-status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
     std::array<char, 20> buf;
     memset(buf.data(), 0, 20);
     sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
@@ -317,30 +319,43 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-               << saddr.val << std::dec;
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
+                      << std::dec;
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
+    }
+}
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if(handle) {
-        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
+            CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
             // TODO: check length of addr range
             target_adapter_base::bp_lut.removeEntry(handle);
-        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
             return Ok;
         }
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Err;
     }
+    }
+}
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
@@ -440,7 +455,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
 </target>
 
  */
-}
-}
+} // namespace debugger
+} // namespace iss
 
 #endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/iss/factory.h

@@ -0,0 +1,106 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_
+
+#include <algorithm>
+#include <functional>
+#include <iss/iss.h>
+#include <memory>
+#include <string>
+#include <unordered_map>
+#include <vector>
+
+namespace iss {
+
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr = std::unique_ptr<iss::vm_if>;
+
+template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port) {
+    using core_type = typename PLAT::core;
+    core_type* lcpu = new PLAT();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_TCC
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+    return {nullptr, nullptr};
+}
+
+class core_factory {
+    using cpu_ptr = std::unique_ptr<iss::arch_if>;
+    using vm_ptr = std::unique_ptr<iss::vm_if>;
+    using base_t = std::tuple<cpu_ptr, vm_ptr>;
+    using create_fn = std::function<base_t(unsigned, void*)>;
+    using registry_t = std::unordered_map<std::string, create_fn>;
+
+    registry_t registry;
+
+    core_factory() = default;
+    core_factory(const core_factory&) = delete;
+    core_factory& operator=(const core_factory&) = delete;
+
+public:
+    static core_factory& instance() {
+        static core_factory bf;
+        return bf;
+    }
+
+    bool register_creator(const std::string& className, create_fn const& fn) {
+        registry[className] = fn;
+        return true;
+    }
+
+    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+        registry_t::const_iterator regEntry = registry.find(className);
+        if(regEntry != registry.end())
+            return regEntry->second(gdb_port, init_data);
+        return {nullptr, nullptr};
+    }
+
+    std::vector<std::string> get_names() {
+        std::vector<std::string> keys{registry.size()};
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+        return keys;
+    }
+};
+
+} // namespace iss
+
+#endif /* _ISS_FACTORY_H_ */

src/iss/plugin/README.md

@@ -0,0 +1,8 @@
+# pctrace
+
+Trace functionality to allow visualizing coverage in lcov and cachegrind tools. Use environment variables NOCOMPRES and REGDUMP to toggle functionality.
+- NOCOMPRES: any value turns off the LZ4 compression
+- REGDUMP: any value switches to tracing the registers instead. Also turns off compression.
+
+Known Bugs: 
+- currently does not work correctly with jit backends, the plugin cant tell if instructions are compressed. Additionaly the cost of instrs that raise a trap is not known. It takes the cost of the instrid -1 (0 at the moment).

src/iss/plugin/cycle_estimate.cpp

@@ -0,0 +1,114 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "cycle_estimate.h"
+#include <iss/plugin/calculator.h>
+#include <yaml-cpp/yaml.h>
+
+#include <fstream>
+#include <iss/arch_if.h>
+#include <util/logging.h>
+
+using namespace std;
+
+iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
+: instr_if(nullptr)
+, config_file_name(config_file_name) {}
+
+iss::plugin::cycle_estimate::~cycle_estimate() = default;
+
+bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    assert(instr_if && "No instrumentation interface available but callback executed");
+    reg_base_ptr = reinterpret_cast<uint32_t*>(vm.get_arch()->get_regs_base_ptr());
+    if(!instr_if)
+        return false;
+    const string core_name = instr_if->core_type_name();
+    if(config_file_name.length() > 0) {
+        std::ifstream is(config_file_name);
+        if(is.is_open()) {
+            try {
+                auto root = YAML::LoadAll(is);
+                if(root.size() != 1) {
+                    CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
+                }
+                for(auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for(auto const& instr : instructions) {
+                        auto idx = instr.second["index"].as<unsigned>();
+                        if(delays.size() <= idx)
+                            delays.resize(idx + 1);
+                        auto& res = delays[idx];
+                        res.is_branch = instr.second["branch"].as<bool>();
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken = delay[0].as<uint64_t>();
+                            res.taken = delay[1].as<uint64_t>();
+                        } else {
+                            try {
+                                res.not_taken = delay.as<uint64_t>();
+                                res.taken = res.not_taken;
+                            } catch(const YAML::BadConversion& e) {
+                                res.f = iss::plugin::calculator(reg_base_ptr, delay.as<std::string>());
+                            }
+                        }
+                    }
+                }
+            } catch(YAML::ParserException& e) {
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
+            return false;
+        }
+    }
+    return true;
+}
+
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
+    size_t instr_id = instr_info.instr_id;
+    auto& entry = instr_id < delays.size() ? delays[instr_id] : illegal_desc;
+    if(instr_info.phase_id == PRE_SYNC) {
+        if(entry.f)
+            current_delay = entry.f(instr_if->get_instr_word());
+    } else {
+        if(!entry.f)
+            current_delay = instr_if->is_branch_taken() ? entry.taken : entry.not_taken;
+        if(current_delay > 1)
+            instr_if->update_last_instr_cycles(current_delay);
+        current_delay = 1;
+    }
+}

src/iss/plugin/cycle_estimate.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,25 +37,23 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
-#include <json/json.h>
+#include <functional>
 #include <string>
 #include <unordered_map>
+#include <vector>
 
 namespace iss {
 
 namespace plugin {
 
-class cycle_estimate: public iss::vm_plugin {
-	BEGIN_BF_DECL(instr_desc, uint32_t)
-		BF_FIELD(taken, 24, 8)
-		BF_FIELD(not_taken, 16, 8)
-		BF_FIELD(size, 0, 16)
-		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
-			this->size=size;
-			this->taken=taken;
-			this->not_taken=not_taken;
-		}
-	END_BF_DECL();
+class cycle_estimate : public vm_plugin {
+    struct instr_desc {
+        size_t size{0};
+        bool is_branch{false};
+        unsigned not_taken{1};
+        unsigned taken{1};
+        std::function<unsigned(uint64_t)> f;
+    };
 
 public:
     cycle_estimate() = delete;
@@ -64,7 +62,7 @@ public:
 
     cycle_estimate(const cycle_estimate&&) = delete;
 
-    cycle_estimate(std::string config_file_name);
+    cycle_estimate(std::string const& config_file_name);
 
     virtual ~cycle_estimate();
 
@@ -74,13 +72,16 @@ public:
 
     bool registration(const char* const version, vm_if& arch) override;
 
-    sync_type get_sync() override { return POST_SYNC; };
+    sync_type get_sync() override { return ALL_SYNC; };
 
-    void callback(instr_info_t instr_info, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;
 
 private:
-    iss::instrumentation_if *arch_instr;
+    iss::instrumentation_if* instr_if{nullptr};
+    uint32_t* reg_base_ptr{nullptr};
+    instr_desc illegal_desc{};
     std::vector<instr_desc> delays;
+    unsigned current_delay{0};
     struct pair_hash {
         size_t operator()(const std::pair<uint64_t, uint64_t>& p) const {
             std::hash<uint64_t> hash;
@@ -88,9 +89,9 @@ private:
         }
     };
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
-    Json::Value root;
+    std::string config_file_name;
 };
-}
-}
+} // namespace plugin
+} // namespace iss
 
 #endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

src/iss/plugin/instruction_count.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,24 +32,47 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "iss/plugin/instruction_count.h"
-#include "iss/instrumentation_if.h"
+#include "instruction_count.h"
+#include <iss/instrumentation_if.h>
+#include <yaml-cpp/yaml.h>
 
+#include <fstream>
 #include <iss/arch_if.h>
 #include <util/logging.h>
-#include <fstream>
 
 iss::plugin::instruction_count::instruction_count(std::string config_file_name) {
     if(config_file_name.length() > 0) {
         std::ifstream is(config_file_name);
         if(is.is_open()) {
             try {
-                is >> root;
-            } catch (Json::RuntimeError &e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                auto root = YAML::LoadAll(is);
+                if(root.size() != 1) {
+                    CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
+                }
+                for(auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for(auto const& instr : instructions) {
+                        instr_delay res;
+                        res.instr_name = instr.first.as<std::string>();
+                        res.size = instr.second["encoding"].as<std::string>().size() - 2; // not counting 0b
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken_delay = delay[0].as<uint64_t>();
+                            res.taken_delay = delay[1].as<uint64_t>();
+                        } else {
+                            res.not_taken_delay = delay.as<uint64_t>();
+                            res.taken_delay = res.not_taken_delay;
+                        }
+                        delays.push_back(std::move(res));
+                    }
+                }
+                rep_counts.resize(delays.size());
+            } catch(YAML::ParserException& e) {
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
         }
     }
 }
@@ -57,39 +80,17 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
 iss::plugin::instruction_count::~instruction_count() {
     size_t idx = 0;
     for(auto it : delays) {
-		if(rep_counts[idx]>0)
-			LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
+        if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0))
+            CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx];
         idx++;
     }
 }
 
 bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
     auto instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-	const std::string  core_name = instr_if->core_type_name();
-    Json::Value &val = root[core_name];
-    if(!val.isNull() && val.isArray()){
-    	delays.reserve(val.size());
-    	for(auto it:val){
-    		auto name = it["name"];
-    		auto size = it["size"];
-    		auto delay = it["delay"];
-    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
-    		if(delay.isUInt()){
-				const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
-				delays.push_back(entry);
-    		} else {
-				const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
-				delays.push_back(entry);
-    		}
-    	}
-    	rep_counts.resize(delays.size());
-    } else {
-        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
-    }
+    if(!instr_if)
+        return false;
     return true;
 }
 
-void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
-	rep_counts[instr_info.instr_id]++;
-}
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) { rep_counts[instr_info.instr_id]++; }

src/iss/plugin/instruction_count.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,8 +36,8 @@
 #define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
 
 #include <iss/vm_plugin.h>
-#include <json/json.h>
 #include <string>
+#include <vector>
 
 namespace iss {
 namespace plugin {
@@ -69,14 +69,13 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;
 
 private:
-    Json::Value root;
     std::vector<instr_delay> delays;
     std::vector<uint64_t> rep_counts;
 };
-}
-}
+} // namespace plugin
+} // namespace iss
 
 #endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

src/iss/semihosting/semihosting.cpp

@@ -0,0 +1,297 @@
+#include "semihosting.h"
+#include <chrono>
+#include <cstdint>
+#include <iss/vm_types.h>
+#include <map>
+#include <stdexcept>
+// explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h
+
+const char* SYS_OPEN_MODES_STRS[] = {"r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b"};
+
+template <typename T> T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len = 4) {
+    uint8_t bytes[4];
+    auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]);
+    // auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+
+    if(res != iss::Ok) {
+        return 0; // TODO THROW ERROR
+    } else
+        return static_cast<T>(bytes[0]) | (static_cast<T>(bytes[1]) << 8) | (static_cast<T>(bytes[2]) << 16) |
+               (static_cast<T>(bytes[3]) << 24);
+}
+
+template <typename T> std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len) {
+    std::vector<uint8_t> buffer(str_len);
+    for(int i = 0; i < str_len; i++) {
+        buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1);
+    }
+    std::string str(buffer.begin(), buffer.end());
+    return str;
+}
+
+template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) {
+    static std::map<T, FILE*> openFiles;
+    static T file_count = 3;
+    static T semihostingErrno;
+
+    switch(static_cast<semihosting_syscalls>(*call_number)) {
+    case semihosting_syscalls::SYS_CLOCK: {
+        auto end = std::chrono::high_resolution_clock::now(); // end measurement
+        auto elapsed = end - timeVar;
+        auto millis = std::chrono::duration_cast<std::chrono::milliseconds>(elapsed).count();
+        *call_number = millis; // TODO get time now
+        break;
+    }
+    case semihosting_syscalls::SYS_CLOSE: {
+        T file_handle = *parameter;
+        if(openFiles.size() <= file_handle && file_handle < 0) {
+            semihostingErrno = EBADF;
+            return;
+        }
+        auto file = openFiles[file_handle];
+        openFiles.erase(file_handle);
+        if(!(file == stdin || file == stdout || file == stderr)) {
+            int i = fclose(file);
+            *call_number = i;
+        } else {
+            *call_number = -1;
+            semihostingErrno = EINTR;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_ELAPSED: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ERRNO: {
+        *call_number = semihostingErrno;
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT: {
+
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT");
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT_EXTENDED: {
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT_EXTENDED");
+        break;
+    }
+    case semihosting_syscalls::SYS_FLEN: {
+        T file_handle = *parameter;
+        auto file = openFiles[file_handle];
+
+        size_t currentPos = ftell(file);
+        if(currentPos < 0)
+            throw std::runtime_error("SYS_FLEN negative value");
+        fseek(file, 0, SEEK_END);
+        size_t length = ftell(file);
+        fseek(file, currentPos, SEEK_SET);
+        *call_number = (T)length;
+        break;
+    }
+    case semihosting_syscalls::SYS_GET_CMDLINE: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_HEAPINFO: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ISERROR: {
+        T value = *parameter;
+        *call_number = (value != 0);
+        break;
+    }
+    case semihosting_syscalls::SYS_ISTTY: {
+        T file_handle = *parameter;
+        *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2);
+        break;
+    }
+    case semihosting_syscalls::SYS_OPEN: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T mode = sh_read_field<T>(arch_if_ptr, 4 + (*parameter));
+        T path_len = sh_read_field<T>(arch_if_ptr, 8 + (*parameter));
+
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        // TODO LOG INFO
+
+        if(mode >= 12) {
+            // TODO throw ERROR
+            return;
+        }
+
+        FILE* file = nullptr;
+        if(path_str == ":tt") {
+            if(mode < 4)
+                file = stdin;
+            else if(mode < 8)
+                file = stdout;
+            else
+                file = stderr;
+        } else {
+            file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]);
+            if(file == nullptr) {
+                // TODO throw error
+                return;
+            }
+        }
+        T file_handle = file_count++;
+        openFiles[file_handle] = file;
+        *call_number = file_handle;
+        break;
+    }
+    case semihosting_syscalls::SYS_READ: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+
+        std::vector<uint8_t> buffer(count);
+        size_t num_read = 0;
+        if(file == stdin) {
+            // when reading from stdin: mimic behaviour from read syscall
+            // and return on newline.
+            while(num_read < count) {
+                char c = fgetc(file);
+                buffer[num_read] = c;
+                num_read++;
+                if(c == '\n')
+                    break;
+            }
+        } else {
+            num_read = fread(buffer.data(), 1, count, file);
+        }
+        buffer.resize(num_read);
+        for(int i = 0; i < num_read; i++) {
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr + i, 1, &buffer[i]);
+            if(res != iss::Ok)
+                return;
+        }
+        *call_number = count - num_read;
+        break;
+    }
+    case semihosting_syscalls::SYS_READC: {
+        uint8_t character = getchar();
+        // character = getchar();
+        /*if(character != iss::Ok)
+            std::cout << "Not OK";
+            return;*/
+        *call_number = character;
+        break;
+    }
+    case semihosting_syscalls::SYS_REMOVE: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        if(remove(path_str.c_str()) < 0)
+            *call_number = -1;
+        break;
+    }
+    case semihosting_syscalls::SYS_RENAME: {
+        T path_str_addr_old = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len_old = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T path_str_addr_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+        T path_len_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 12);
+
+        std::string path_str_old = sh_read_string<T>(arch_if_ptr, path_str_addr_old, path_len_old);
+        std::string path_str_new = sh_read_string<T>(arch_if_ptr, path_str_addr_new, path_len_new);
+        rename(path_str_old.c_str(), path_str_new.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_SEEK: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, *parameter);
+        T pos = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        auto file = openFiles[file_handle];
+
+        int retval = fseek(file, pos, SEEK_SET);
+        if(retval < 0)
+            throw std::runtime_error("SYS_SEEK negative return value");
+
+        break;
+    }
+    case semihosting_syscalls::SYS_SYSTEM: {
+        T cmd_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T cmd_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        std::string cmd = sh_read_string<T>(arch_if_ptr, cmd_addr, cmd_len);
+        system(cmd.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_TICKFREQ: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_TIME: {
+        // returns time in seconds scince 01.01.1970 00:00
+        *call_number = time(NULL);
+        break;
+    }
+    case semihosting_syscalls::SYS_TMPNAM: {
+        T buffer_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T identifier = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        T buffer_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 2);
+
+        if(identifier > 255) {
+            *call_number = -1;
+            return;
+        }
+        std::stringstream ss;
+        ss << "tmp/file-" << std::setfill('0') << std::setw(3) << identifier;
+        std::string filename = ss.str();
+
+        for(int i = 0; i < buffer_len; i++) {
+            uint8_t character = filename[i];
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i, 1, &character);
+            if(res != iss::Ok)
+                return;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+        std::string str = sh_read_string<T>(arch_if_ptr, addr, count);
+        fwrite(&str[0], 1, count, file);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITEC: {
+        uint8_t character;
+        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+        if(res != iss::Ok)
+            return;
+        putchar(character);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE0: {
+        uint8_t character;
+        while(1) {
+            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+            if(res != iss::Ok)
+                return;
+            if(character == 0)
+                break;
+            putchar(character);
+            (*parameter)++;
+        }
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x100: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x1FF: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    default:
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+}
+template class semihosting_callback<uint32_t>;
+template class semihosting_callback<uint64_t>;

src/iss/semihosting/semihosting.h

@@ -0,0 +1,61 @@
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+#include <chrono>
+#include <functional>
+#include <iss/arch_if.h>
+/*
+ * According to:
+ * "Semihosting for AArch32 and AArch64, Release 2.0"
+ * https://static.docs.arm.com/100863/0200/semihosting.pdf
+ * from ARM Ltd.
+ *
+ * The available semihosting operation numbers passed in A0 are allocated
+ * as follows:
+ * - 0x00-0x31 Used by ARM.
+ * - 0x32-0xFF Reserved for future use by ARM.
+ * - 0x100-0x1FF Reserved for user applications. These are not used by ARM.
+ *   However, if you are writing your own SVC operations, you are advised
+ *   to use a different SVC number rather than using the semihosted
+ *   SVC number and these operation type numbers.
+ * - 0x200-0xFFFFFFFF Undefined and currently unused. It is recommended
+ *   that you do not use these.
+ */
+enum class semihosting_syscalls {
+
+    SYS_OPEN = 0x01,
+    SYS_CLOSE = 0x02,
+    SYS_WRITEC = 0x03,
+    SYS_WRITE0 = 0x04,
+    SYS_WRITE = 0x05,
+    SYS_READ = 0x06,
+    SYS_READC = 0x07,
+    SYS_ISERROR = 0x08,
+    SYS_ISTTY = 0x09,
+    SYS_SEEK = 0x0A,
+    SYS_FLEN = 0x0C,
+    SYS_TMPNAM = 0x0D,
+    SYS_REMOVE = 0x0E,
+    SYS_RENAME = 0x0F,
+    SYS_CLOCK = 0x10,
+    SYS_TIME = 0x11,
+    SYS_SYSTEM = 0x12,
+    SYS_ERRNO = 0x13,
+    SYS_GET_CMDLINE = 0x15,
+    SYS_HEAPINFO = 0x16,
+    SYS_EXIT = 0x18,
+    SYS_EXIT_EXTENDED = 0x20,
+    SYS_ELAPSED = 0x30,
+    SYS_TICKFREQ = 0x31,
+    USER_CMD_0x100 = 0x100,
+    USER_CMD_0x1FF = 0x1FF,
+};
+
+template <typename T> struct semihosting_callback {
+    std::chrono::high_resolution_clock::time_point timeVar;
+    semihosting_callback()
+    : timeVar(std::chrono::high_resolution_clock::now()) {}
+    void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter);
+};
+
+template <typename T> using semihosting_cb_t = std::function<void(iss::arch_if*, T*, T*)>;
+#endif

src/main.cpp

@@ -30,34 +30,32 @@
  *
  *******************************************************************************/
 
+#include <array>
+#include <cstdint>
 #include <iostream>
 #include <iss/factory.h>
+#include <iss/semihosting/semihosting.h>
+#include <string>
+#include <unordered_map>
+#include <vector>
 
+#include "iss/arch/tgc_mapper.h"
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
-#include <iss/arch/riscv_hart_m_p.h>
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_B
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_b.h"
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#endif
-#ifdef CORE_TGC_D
-#include "iss/arch/riscv_hart_mu_p.h"
-#include "iss/arch/tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
 #ifdef WITH_LLVM
-#include <iss/llvm/jit_helper.h>
+#include <iss/llvm/jit_init.h>
 #endif
+#include "iss/plugin/cycle_estimate.h"
+#include "iss/plugin/instruction_count.h"
 #include <iss/log_categories.h>
-#include <iss/plugin/cycle_estimate.h>
-#include <iss/plugin/instruction_count.h>
+#ifndef WIN32
+#include <iss/plugin/loader.h>
+#endif
+#if defined(HAS_LUA)
+#include <iss/plugin/lua.h>
+#endif
 
 namespace po = boost::program_options;
-
 int main(int argc, char* argv[]) {
     /*
      *  Define and parse the program options
@@ -67,25 +65,25 @@ int main(int argc, char *argv[]) {
     // clang-format off
     desc.add_options()
         ("help,h", "Print help message")
-        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
-        ("logfile,f", po::value<std::string>(), "Sets default log file.")
+        ("verbose,v", po::value<int>()->default_value(4), "Sets logging verbosity")
+        ("logfile,l", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
         ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
         ("reset,r", po::value<std::string>(), "reset address")
         ("dump-ir", "dump the intermediate representation")
-        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
+        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
-        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
+        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit")
+        ("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
     try {
         po::store(parsed, clim); // can throw
         // --help option
         if(clim.count("help")) {
-            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
+            std::cout << "DBT-RISE-TGC simulator for TGC RISC-V cores" << std::endl << desc << std::endl;
             return 0;
         }
         po::notify(clim); // throws on error, so do after help in case
@@ -99,11 +97,9 @@ int main(int argc, char *argv[]) {
 
     LOGGER(DEFAULT)::print_time() = false;
     LOGGER(connection)::print_time() = false;
-    if (clim.count("verbose")) {
     auto l = logging::as_log_level(clim["verbose"].as<int>());
     LOGGER(DEFAULT)::reporting_level() = l;
     LOGGER(connection)::reporting_level() = l;
-    }
     if(clim.count("logfile")) {
         // configure the connection logger
         auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
@@ -119,53 +115,77 @@ int main(int argc, char *argv[]) {
         iss::init_jit_debug(argc, argv);
 #endif
         bool dump = clim.count("dump-ir");
+        auto& f = iss::core_factory::instance();
         // instantiate the simulator
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
+        semihosting_callback<uint32_t> cb{};
+        semihosting_cb_t<uint32_t> semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) { cb(i, a0, a1); };
         std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgc_c") {
+        if(isa_opt.size() == 0 || isa_opt == "?") {
+            auto list = f.get_names();
+            std::sort(std::begin(list), std::end(list));
+            std::cout << "Available implementations (core|platform|backend):\n  - " << util::join(list, "\n  - ") << std::endl;
+            return 0;
+        } else if(isa_opt.find('|') != std::string::npos) {
             std::tie(cpu, vm) =
-                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#ifdef CORE_TGC_B
-        if (isa_opt == "tgc_b") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_D
-        if (isa_opt == "tgc_d") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-        {
-            LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+                f.create(isa_opt + "|" + clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>(), &semihosting_cb);
+        } else {
+            auto base_isa = isa_opt.substr(0, 5);
+            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
+                isa_opt += "|mu_p_clic_pmp|" + clim["backend"].as<std::string>();
+            } else {
+                isa_opt += "|m_p|" + clim["backend"].as<std::string>();
+            }
+            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
+        }
+        if(!cpu) {
+            CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
+            return 127;
+        }
+        if(!vm) {
+            CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
             return 127;
         }
         if(clim.count("plugin")) {
             for(std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
                 std::string plugin_name = opt_val;
-                std::string filename{"cycles.txt"};
+                std::string arg{""};
                 std::size_t found = opt_val.find('=');
                 if(found != std::string::npos) {
                     plugin_name = opt_val.substr(0, found);
-                    filename = opt_val.substr(found + 1, opt_val.size());
+                    arg = opt_val.substr(found + 1, opt_val.size());
                 }
+#if defined(WITH_PLUGINS)
                 if(plugin_name == "ic") {
-                    auto *ic_plugin = new iss::plugin::instruction_count(filename);
+                    auto* ic_plugin = new iss::plugin::instruction_count(arg);
                     vm->register_plugin(*ic_plugin);
                     plugin_list.push_back(ic_plugin);
                 } else if(plugin_name == "ce") {
-                    auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
+                    auto* ce_plugin = new iss::plugin::cycle_estimate(arg);
                     vm->register_plugin(*ce_plugin);
                     plugin_list.push_back(ce_plugin);
-                } else {
-                    LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+                } else
+#endif
+                {
+#if !defined(WIN32)
+                    std::vector<char const*> a{};
+                    if(arg.length())
+                        a.push_back({arg.c_str()});
+                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                    if(plugin) {
+                        vm->register_plugin(*plugin);
+                        plugin_list.push_back(plugin);
+                    } else
+#endif
+                    {
+                        CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                         return 127;
                     }
                 }
             }
+        }
         if(clim.count("disass")) {
             vm->setDisassEnabled(true);
             LOGGER(disass)::reporting_level() = logging::INFO;
@@ -182,11 +202,13 @@ int main(int argc, char *argv[]) {
         if(clim.count("elf"))
             for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if (start_addr.second) start_address = start_addr.first;
+                if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                    start_address = start_addr.first;
             }
         for(std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if (start_addr.second) start_address = start_addr.first;
+            if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                start_address = start_addr.first;
         }
         if(clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();
@@ -195,12 +217,42 @@ int main(int argc, char *argv[]) {
         vm->reset(start_address);
         auto cycles = clim["instructions"].as<uint64_t>();
         res = vm->start(cycles, dump);
+
+        auto instr_if = vm->get_arch()->get_instrumentation_if();
+        // this assumes a single input file
+        std::unordered_map<std::string, uint64_t> sym_table;
+        if(args.empty())
+            sym_table = instr_if->get_symbol_table(clim["elf"].as<std::vector<std::string>>()[0]);
+        else
+            sym_table = instr_if->get_symbol_table(args[0]);
+        if(sym_table.find("begin_signature") != std::end(sym_table) && sym_table.find("end_signature") != std::end(sym_table)) {
+            auto start_addr = sym_table["begin_signature"];
+            auto end_addr = sym_table["end_signature"];
+            std::array<uint8_t, 4> data;
+            std::ofstream file;
+            std::string filename = fmt::format("{}.signature", isa_opt);
+            std::replace(std::begin(filename), std::end(filename), '|', '_');
+            // default riscof requires this filename
+            filename = "DUT-tgc.signature";
+            file.open(filename, std::ios::out);
+            if(!file.is_open()) {
+                LOG(ERR) << "Error opening file " << filename << std::endl;
+                return 1;
+            }
+            for(auto addr = start_addr; addr < end_addr; addr += data.size()) {
+                vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(),
+                                     data.data()); // FIXME: get space from iss::arch::traits<ARCH>::mem_type_e::MEM
+
+                // TODO : obey Target endianess
+                uint32_t to_print = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
+                file << std::hex << fmt::format("{:08x}", to_print) << std::dec << std::endl;
+            }
+        }
     } catch(std::exception& e) {
-        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
-                   << std::endl;
+        CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
         res = 2;
     }
-    // cleanup to let plugins report of needed
+    // cleanup to let plugins report if needed
     for(auto* p : plugin_list) {
         delete p;
     }

src/plugin/GCOV.cpp

@@ -1,821 +0,0 @@
-//===- GCOV.cpp - LLVM coverage tool --------------------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// GCOV implements the interface to read and write coverage files that use
-// 'gcov' format.
-//
-//===----------------------------------------------------------------------===//
-
-#include "GCOV.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/FileSystem.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/Path.h"
-#include "llvm/Support/raw_ostream.h"
-#include <algorithm>
-#include <system_error>
-
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// GCOVFile implementation.
-
-/// readGCNO - Read GCNO buffer.
-bool GCOVFile::readGCNO(GCOVBuffer &Buffer) {
-  if (!Buffer.readGCNOFormat())
-    return false;
-  if (!Buffer.readGCOVVersion(Version))
-    return false;
-
-  if (!Buffer.readInt(Checksum))
-    return false;
-  while (true) {
-    if (!Buffer.readFunctionTag())
-      break;
-    auto GFun = make_unique<GCOVFunction>(*this);
-    if (!GFun->readGCNO(Buffer, Version))
-      return false;
-    Functions.push_back(std::move(GFun));
-  }
-
-  GCNOInitialized = true;
-  return true;
-}
-
-/// readGCDA - Read GCDA buffer. It is required that readGCDA() can only be
-/// called after readGCNO().
-bool GCOVFile::readGCDA(GCOVBuffer &Buffer) {
-  assert(GCNOInitialized && "readGCDA() can only be called after readGCNO()");
-  if (!Buffer.readGCDAFormat())
-    return false;
-  GCOV::GCOVVersion GCDAVersion;
-  if (!Buffer.readGCOVVersion(GCDAVersion))
-    return false;
-  if (Version != GCDAVersion) {
-    errs() << "GCOV versions do not match.\n";
-    return false;
-  }
-
-  uint32_t GCDAChecksum;
-  if (!Buffer.readInt(GCDAChecksum))
-    return false;
-  if (Checksum != GCDAChecksum) {
-    errs() << "File checksums do not match: " << Checksum
-           << " != " << GCDAChecksum << ".\n";
-    return false;
-  }
-  for (size_t i = 0, e = Functions.size(); i < e; ++i) {
-    if (!Buffer.readFunctionTag()) {
-      errs() << "Unexpected number of functions.\n";
-      return false;
-    }
-    if (!Functions[i]->readGCDA(Buffer, Version))
-      return false;
-  }
-  if (Buffer.readObjectTag()) {
-    uint32_t Length;
-    uint32_t Dummy;
-    if (!Buffer.readInt(Length))
-      return false;
-    if (!Buffer.readInt(Dummy))
-      return false; // checksum
-    if (!Buffer.readInt(Dummy))
-      return false; // num
-    if (!Buffer.readInt(RunCount))
-      return false;
-    Buffer.advanceCursor(Length - 3);
-  }
-  while (Buffer.readProgramTag()) {
-    uint32_t Length;
-    if (!Buffer.readInt(Length))
-      return false;
-    Buffer.advanceCursor(Length);
-    ++ProgramCount;
-  }
-
-  return true;
-}
-
-void GCOVFile::print(raw_ostream &OS) const {
-  for (const auto &FPtr : Functions)
-    FPtr->print(OS);
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVFile content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVFile::dump() const {
-  print(dbgs());
-}
-#endif
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVFile::collectLineCounts(FileInfo &FI) {
-  for (const auto &FPtr : Functions)
-    FPtr->collectLineCounts(FI);
-  FI.setRunCount(RunCount);
-  FI.setProgramCount(ProgramCount);
-}
-
-//===----------------------------------------------------------------------===//
-// GCOVFunction implementation.
-
-/// readGCNO - Read a function from the GCNO buffer. Return false if an error
-/// occurs.
-bool GCOVFunction::readGCNO(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
-  uint32_t Dummy;
-  if (!Buff.readInt(Dummy))
-    return false; // Function header length
-  if (!Buff.readInt(Ident))
-    return false;
-  if (!Buff.readInt(Checksum))
-    return false;
-  if (Version != GCOV::V402) {
-    uint32_t CfgChecksum;
-    if (!Buff.readInt(CfgChecksum))
-      return false;
-    if (Parent.getChecksum() != CfgChecksum) {
-      errs() << "File checksums do not match: " << Parent.getChecksum()
-             << " != " << CfgChecksum << " in (" << Name << ").\n";
-      return false;
-    }
-  }
-  if (!Buff.readString(Name))
-    return false;
-  if (!Buff.readString(Filename))
-    return false;
-  if (!Buff.readInt(LineNumber))
-    return false;
-
-  // read blocks.
-  if (!Buff.readBlockTag()) {
-    errs() << "Block tag not found.\n";
-    return false;
-  }
-  uint32_t BlockCount;
-  if (!Buff.readInt(BlockCount))
-    return false;
-  for (uint32_t i = 0, e = BlockCount; i != e; ++i) {
-    if (!Buff.readInt(Dummy))
-      return false; // Block flags;
-    Blocks.push_back(make_unique<GCOVBlock>(*this, i));
-  }
-
-  // read edges.
-  while (Buff.readEdgeTag()) {
-    uint32_t EdgeCount;
-    if (!Buff.readInt(EdgeCount))
-      return false;
-    EdgeCount = (EdgeCount - 1) / 2;
-    uint32_t BlockNo;
-    if (!Buff.readInt(BlockNo))
-      return false;
-    if (BlockNo >= BlockCount) {
-      errs() << "Unexpected block number: " << BlockNo << " (in " << Name
-             << ").\n";
-      return false;
-    }
-    for (uint32_t i = 0, e = EdgeCount; i != e; ++i) {
-      uint32_t Dst;
-      if (!Buff.readInt(Dst))
-        return false;
-      Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst]));
-      GCOVEdge *Edge = Edges.back().get();
-      Blocks[BlockNo]->addDstEdge(Edge);
-      Blocks[Dst]->addSrcEdge(Edge);
-      if (!Buff.readInt(Dummy))
-        return false; // Edge flag
-    }
-  }
-
-  // read line table.
-  while (Buff.readLineTag()) {
-    uint32_t LineTableLength;
-    // Read the length of this line table.
-    if (!Buff.readInt(LineTableLength))
-      return false;
-    uint32_t EndPos = Buff.getCursor() + LineTableLength * 4;
-    uint32_t BlockNo;
-    // Read the block number this table is associated with.
-    if (!Buff.readInt(BlockNo))
-      return false;
-    if (BlockNo >= BlockCount) {
-      errs() << "Unexpected block number: " << BlockNo << " (in " << Name
-             << ").\n";
-      return false;
-    }
-    GCOVBlock &Block = *Blocks[BlockNo];
-    // Read the word that pads the beginning of the line table. This may be a
-    // flag of some sort, but seems to always be zero.
-    if (!Buff.readInt(Dummy))
-      return false;
-
-    // Line information starts here and continues up until the last word.
-    if (Buff.getCursor() != (EndPos - sizeof(uint32_t))) {
-      StringRef F;
-      // Read the source file name.
-      if (!Buff.readString(F))
-        return false;
-      if (Filename != F) {
-        errs() << "Multiple sources for a single basic block: " << Filename
-               << " != " << F << " (in " << Name << ").\n";
-        return false;
-      }
-      // Read lines up to, but not including, the null terminator.
-      while (Buff.getCursor() < (EndPos - 2 * sizeof(uint32_t))) {
-        uint32_t Line;
-        if (!Buff.readInt(Line))
-          return false;
-        // Line 0 means this instruction was injected by the compiler. Skip it.
-        if (!Line)
-          continue;
-        Block.addLine(Line);
-      }
-      // Read the null terminator.
-      if (!Buff.readInt(Dummy))
-        return false;
-    }
-    // The last word is either a flag or padding, it isn't clear which. Skip
-    // over it.
-    if (!Buff.readInt(Dummy))
-      return false;
-  }
-  return true;
-}
-
-/// readGCDA - Read a function from the GCDA buffer. Return false if an error
-/// occurs.
-bool GCOVFunction::readGCDA(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
-  uint32_t HeaderLength;
-  if (!Buff.readInt(HeaderLength))
-    return false; // Function header length
-
-  uint64_t EndPos = Buff.getCursor() + HeaderLength * sizeof(uint32_t);
-
-  uint32_t GCDAIdent;
-  if (!Buff.readInt(GCDAIdent))
-    return false;
-  if (Ident != GCDAIdent) {
-    errs() << "Function identifiers do not match: " << Ident
-           << " != " << GCDAIdent << " (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t GCDAChecksum;
-  if (!Buff.readInt(GCDAChecksum))
-    return false;
-  if (Checksum != GCDAChecksum) {
-    errs() << "Function checksums do not match: " << Checksum
-           << " != " << GCDAChecksum << " (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t CfgChecksum;
-  if (Version != GCOV::V402) {
-    if (!Buff.readInt(CfgChecksum))
-      return false;
-    if (Parent.getChecksum() != CfgChecksum) {
-      errs() << "File checksums do not match: " << Parent.getChecksum()
-             << " != " << CfgChecksum << " (in " << Name << ").\n";
-      return false;
-    }
-  }
-
-  if (Buff.getCursor() < EndPos) {
-    StringRef GCDAName;
-    if (!Buff.readString(GCDAName))
-      return false;
-    if (Name != GCDAName) {
-      errs() << "Function names do not match: " << Name << " != " << GCDAName
-             << ".\n";
-      return false;
-    }
-  }
-
-  if (!Buff.readArcTag()) {
-    errs() << "Arc tag not found (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t Count;
-  if (!Buff.readInt(Count))
-    return false;
-  Count /= 2;
-
-  // This for loop adds the counts for each block. A second nested loop is
-  // required to combine the edge counts that are contained in the GCDA file.
-  for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) {
-    // The last block is always reserved for exit block
-    if (BlockNo >= Blocks.size()) {
-      errs() << "Unexpected number of edges (in " << Name << ").\n";
-      return false;
-    }
-    if (BlockNo == Blocks.size() - 1)
-      errs() << "(" << Name << ") has arcs from exit block.\n";
-    GCOVBlock &Block = *Blocks[BlockNo];
-    for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End;
-         ++EdgeNo) {
-      if (Count == 0) {
-        errs() << "Unexpected number of edges (in " << Name << ").\n";
-        return false;
-      }
-      uint64_t ArcCount;
-      if (!Buff.readInt64(ArcCount))
-        return false;
-      Block.addCount(EdgeNo, ArcCount);
-      --Count;
-    }
-    Block.sortDstEdges();
-  }
-  return true;
-}
-
-/// getEntryCount - Get the number of times the function was called by
-/// retrieving the entry block's count.
-uint64_t GCOVFunction::getEntryCount() const {
-  return Blocks.front()->getCount();
-}
-
-/// getExitCount - Get the number of times the function returned by retrieving
-/// the exit block's count.
-uint64_t GCOVFunction::getExitCount() const {
-  return Blocks.back()->getCount();
-}
-
-void GCOVFunction::print(raw_ostream &OS) const {
-  OS << "===== " << Name << " (" << Ident << ") @ " << Filename << ":"
-     << LineNumber << "\n";
-  for (const auto &Block : Blocks)
-    Block->print(OS);
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVFunction content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVFunction::dump() const {
-  print(dbgs());
-}
-#endif
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVFunction::collectLineCounts(FileInfo &FI) {
-  // If the line number is zero, this is a function that doesn't actually appear
-  // in the source file, so there isn't anything we can do with it.
-  if (LineNumber == 0)
-    return;
-
-  for (const auto &Block : Blocks)
-    Block->collectLineCounts(FI);
-  FI.addFunctionLine(Filename, LineNumber, this);
-}
-
-//===----------------------------------------------------------------------===//
-// GCOVBlock implementation.
-
-/// ~GCOVBlock - Delete GCOVBlock and its content.
-GCOVBlock::~GCOVBlock() {
-  SrcEdges.clear();
-  DstEdges.clear();
-  Lines.clear();
-}
-
-/// addCount - Add to block counter while storing the edge count. If the
-/// destination has no outgoing edges, also update that block's count too.
-void GCOVBlock::addCount(size_t DstEdgeNo, uint64_t N) {
-  assert(DstEdgeNo < DstEdges.size()); // up to caller to ensure EdgeNo is valid
-  DstEdges[DstEdgeNo]->Count = N;
-  Counter += N;
-  if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges())
-    DstEdges[DstEdgeNo]->Dst.Counter += N;
-}
-
-/// sortDstEdges - Sort destination edges by block number, nop if already
-/// sorted. This is required for printing branch info in the correct order.
-void GCOVBlock::sortDstEdges() {
-  if (!DstEdgesAreSorted) {
-    SortDstEdgesFunctor SortEdges;
-    std::stable_sort(DstEdges.begin(), DstEdges.end(), SortEdges);
-  }
-}
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVBlock::collectLineCounts(FileInfo &FI) {
-  for (uint32_t N : Lines)
-    FI.addBlockLine(Parent.getFilename(), N, this);
-}
-
-void GCOVBlock::print(raw_ostream &OS) const {
-  OS << "Block : " << Number << " Counter : " << Counter << "\n";
-  if (!SrcEdges.empty()) {
-    OS << "\tSource Edges : ";
-    for (const GCOVEdge *Edge : SrcEdges)
-      OS << Edge->Src.Number << " (" << Edge->Count << "), ";
-    OS << "\n";
-  }
-  if (!DstEdges.empty()) {
-    OS << "\tDestination Edges : ";
-    for (const GCOVEdge *Edge : DstEdges)
-      OS << Edge->Dst.Number << " (" << Edge->Count << "), ";
-    OS << "\n";
-  }
-  if (!Lines.empty()) {
-    OS << "\tLines : ";
-    for (uint32_t N : Lines)
-      OS << (N) << ",";
-    OS << "\n";
-  }
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVBlock content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVBlock::dump() const {
-  print(dbgs());
-}
-#endif
-
-//===----------------------------------------------------------------------===//
-// FileInfo implementation.
-
-// Safe integer division, returns 0 if numerator is 0.
-static uint32_t safeDiv(uint64_t Numerator, uint64_t Divisor) {
-  if (!Numerator)
-    return 0;
-  return Numerator / Divisor;
-}
-
-// This custom division function mimics gcov's branch ouputs:
-//   - Round to closest whole number
-//   - Only output 0% or 100% if it's exactly that value
-static uint32_t branchDiv(uint64_t Numerator, uint64_t Divisor) {
-  if (!Numerator)
-    return 0;
-  if (Numerator == Divisor)
-    return 100;
-
-  uint8_t Res = (Numerator * 100 + Divisor / 2) / Divisor;
-  if (Res == 0)
-    return 1;
-  if (Res == 100)
-    return 99;
-  return Res;
-}
-
-namespace {
-struct formatBranchInfo {
-  formatBranchInfo(const GCOV::Options &Options, uint64_t Count, uint64_t Total)
-      : Options(Options), Count(Count), Total(Total) {}
-
-  void print(raw_ostream &OS) const {
-    if (!Total)
-      OS << "never executed";
-    else if (Options.BranchCount)
-      OS << "taken " << Count;
-    else
-      OS << "taken " << branchDiv(Count, Total) << "%";
-  }
-
-  const GCOV::Options &Options;
-  uint64_t Count;
-  uint64_t Total;
-};
-
-static raw_ostream &operator<<(raw_ostream &OS, const formatBranchInfo &FBI) {
-  FBI.print(OS);
-  return OS;
-}
-
-class LineConsumer {
-  std::unique_ptr<MemoryBuffer> Buffer;
-  StringRef Remaining;
-
-public:
-  LineConsumer(StringRef Filename) {
-    ErrorOr<std::unique_ptr<MemoryBuffer>> BufferOrErr =
-        MemoryBuffer::getFileOrSTDIN(Filename);
-    if (std::error_code EC = BufferOrErr.getError()) {
-      errs() << Filename << ": " << EC.message() << "\n";
-      Remaining = "";
-    } else {
-      Buffer = std::move(BufferOrErr.get());
-      Remaining = Buffer->getBuffer();
-    }
-  }
-  bool empty() { return Remaining.empty(); }
-  void printNext(raw_ostream &OS, uint32_t LineNum) {
-    StringRef Line;
-    if (empty())
-      Line = "/*EOF*/";
-    else
-      std::tie(Line, Remaining) = Remaining.split("\n");
-    OS << format("%5u:", LineNum) << Line << "\n";
-  }
-};
-} // end anonymous namespace
-
-/// Convert a path to a gcov filename. If PreservePaths is true, this
-/// translates "/" to "#", ".." to "^", and drops ".", to match gcov.
-static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) {
-  if (!PreservePaths)
-    return sys::path::filename(Filename).str();
-
-  // This behaviour is defined by gcov in terms of text replacements, so it's
-  // not likely to do anything useful on filesystems with different textual
-  // conventions.
-  llvm::SmallString<256> Result("");
-  StringRef::iterator I, S, E;
-  for (I = S = Filename.begin(), E = Filename.end(); I != E; ++I) {
-    if (*I != '/')
-      continue;
-
-    if (I - S == 1 && *S == '.') {
-      // ".", the current directory, is skipped.
-    } else if (I - S == 2 && *S == '.' && *(S + 1) == '.') {
-      // "..", the parent directory, is replaced with "^".
-      Result.append("^#");
-    } else {
-      if (S < I)
-        // Leave other components intact,
-        Result.append(S, I);
-      // And separate with "#".
-      Result.push_back('#');
-    }
-    S = I + 1;
-  }
-
-  if (S < I)
-    Result.append(S, I);
-  return Result.str();
-}
-
-std::string FileInfo::getCoveragePath(StringRef Filename,
-                                      StringRef MainFilename) {
-  if (Options.NoOutput)
-    // This is probably a bug in gcov, but when -n is specified, paths aren't
-    // mangled at all, and the -l and -p options are ignored. Here, we do the
-    // same.
-    return Filename;
-
-  std::string CoveragePath;
-  if (Options.LongFileNames && !Filename.equals(MainFilename))
-    CoveragePath =
-        mangleCoveragePath(MainFilename, Options.PreservePaths) + "##";
-  CoveragePath += mangleCoveragePath(Filename, Options.PreservePaths) + ".gcov";
-  return CoveragePath;
-}
-
-std::unique_ptr<raw_ostream>
-FileInfo::openCoveragePath(StringRef CoveragePath) {
-  if (Options.NoOutput)
-    return llvm::make_unique<raw_null_ostream>();
-
-  std::error_code EC;
-  auto OS = llvm::make_unique<raw_fd_ostream>(CoveragePath, EC,
-                                              sys::fs::F_Text);
-  if (EC) {
-    errs() << EC.message() << "\n";
-    return llvm::make_unique<raw_null_ostream>();
-  }
-  return std::move(OS);
-}
-
-/// print -  Print source files with collected line count information.
-void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename,
-                     StringRef GCNOFile, StringRef GCDAFile) {
-  SmallVector<StringRef, 4> Filenames;
-  for (const auto &LI : LineInfo)
-    Filenames.push_back(LI.first());
-  std::sort(Filenames.begin(), Filenames.end());
-
-  for (StringRef Filename : Filenames) {
-    auto AllLines = LineConsumer(Filename);
-
-    std::string CoveragePath = getCoveragePath(Filename, MainFilename);
-    std::unique_ptr<raw_ostream> CovStream = openCoveragePath(CoveragePath);
-    raw_ostream &CovOS = *CovStream;
-
-    CovOS << "        -:    0:Source:" << Filename << "\n";
-    CovOS << "        -:    0:Graph:" << GCNOFile << "\n";
-    CovOS << "        -:    0:Data:" << GCDAFile << "\n";
-    CovOS << "        -:    0:Runs:" << RunCount << "\n";
-    CovOS << "        -:    0:Programs:" << ProgramCount << "\n";
-
-    const LineData &Line = LineInfo[Filename];
-    GCOVCoverage FileCoverage(Filename);
-    for (uint32_t LineIndex = 0; LineIndex < Line.LastLine || !AllLines.empty();
-         ++LineIndex) {
-      if (Options.BranchInfo) {
-        FunctionLines::const_iterator FuncsIt = Line.Functions.find(LineIndex);
-        if (FuncsIt != Line.Functions.end())
-          printFunctionSummary(CovOS, FuncsIt->second);
-      }
-
-      BlockLines::const_iterator BlocksIt = Line.Blocks.find(LineIndex);
-      if (BlocksIt == Line.Blocks.end()) {
-        // No basic blocks are on this line. Not an executable line of code.
-        CovOS << "        -:";
-        AllLines.printNext(CovOS, LineIndex + 1);
-      } else {
-        const BlockVector &Blocks = BlocksIt->second;
-
-        // Add up the block counts to form line counts.
-        DenseMap<const GCOVFunction *, bool> LineExecs;
-        uint64_t LineCount = 0;
-        for (const GCOVBlock *Block : Blocks) {
-          if (Options.AllBlocks) {
-            // Only take the highest block count for that line.
-            uint64_t BlockCount = Block->getCount();
-            LineCount = LineCount > BlockCount ? LineCount : BlockCount;
-          } else {
-            // Sum up all of the block counts.
-            LineCount += Block->getCount();
-          }
-
-          if (Options.FuncCoverage) {
-            // This is a slightly convoluted way to most accurately gather line
-            // statistics for functions. Basically what is happening is that we
-            // don't want to count a single line with multiple blocks more than
-            // once. However, we also don't simply want to give the total line
-            // count to every function that starts on the line. Thus, what is
-            // happening here are two things:
-            // 1) Ensure that the number of logical lines is only incremented
-            //    once per function.
-            // 2) If there are multiple blocks on the same line, ensure that the
-            //    number of lines executed is incremented as long as at least
-            //    one of the blocks are executed.
-            const GCOVFunction *Function = &Block->getParent();
-            if (FuncCoverages.find(Function) == FuncCoverages.end()) {
-              std::pair<const GCOVFunction *, GCOVCoverage> KeyValue(
-                  Function, GCOVCoverage(Function->getName()));
-              FuncCoverages.insert(KeyValue);
-            }
-            GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
-
-            if (LineExecs.find(Function) == LineExecs.end()) {
-              if (Block->getCount()) {
-                ++FuncCoverage.LinesExec;
-                LineExecs[Function] = true;
-              } else {
-                LineExecs[Function] = false;
-              }
-              ++FuncCoverage.LogicalLines;
-            } else if (!LineExecs[Function] && Block->getCount()) {
-              ++FuncCoverage.LinesExec;
-              LineExecs[Function] = true;
-            }
-          }
-        }
-
-        if (LineCount == 0)
-          CovOS << "    #####:";
-        else {
-          CovOS << format("%9" PRIu64 ":", LineCount);
-          ++FileCoverage.LinesExec;
-        }
-        ++FileCoverage.LogicalLines;
-
-        AllLines.printNext(CovOS, LineIndex + 1);
-
-        uint32_t BlockNo = 0;
-        uint32_t EdgeNo = 0;
-        for (const GCOVBlock *Block : Blocks) {
-          // Only print block and branch information at the end of the block.
-          if (Block->getLastLine() != LineIndex + 1)
-            continue;
-          if (Options.AllBlocks)
-            printBlockInfo(CovOS, *Block, LineIndex, BlockNo);
-          if (Options.BranchInfo) {
-            size_t NumEdges = Block->getNumDstEdges();
-            if (NumEdges > 1)
-              printBranchInfo(CovOS, *Block, FileCoverage, EdgeNo);
-            else if (Options.UncondBranch && NumEdges == 1)
-              printUncondBranchInfo(CovOS, EdgeNo,
-                                    (*Block->dst_begin())->Count);
-          }
-        }
-      }
-    }
-    FileCoverages.push_back(std::make_pair(CoveragePath, FileCoverage));
-  }
-
-  // FIXME: There is no way to detect calls given current instrumentation.
-  if (Options.FuncCoverage)
-    printFuncCoverage(InfoOS);
-  printFileCoverage(InfoOS);
-}
-
-/// printFunctionSummary - Print function and block summary.
-void FileInfo::printFunctionSummary(raw_ostream &OS,
-                                    const FunctionVector &Funcs) const {
-  for (const GCOVFunction *Func : Funcs) {
-    uint64_t EntryCount = Func->getEntryCount();
-    uint32_t BlocksExec = 0;
-    for (const GCOVBlock &Block : Func->blocks())
-      if (Block.getNumDstEdges() && Block.getCount())
-        ++BlocksExec;
-
-    OS << "function " << Func->getName() << " called " << EntryCount
-       << " returned " << safeDiv(Func->getExitCount() * 100, EntryCount)
-       << "% blocks executed "
-       << safeDiv(BlocksExec * 100, Func->getNumBlocks() - 1) << "%\n";
-  }
-}
-
-/// printBlockInfo - Output counts for each block.
-void FileInfo::printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
-                              uint32_t LineIndex, uint32_t &BlockNo) const {
-  if (Block.getCount() == 0)
-    OS << "    $$$$$:";
-  else
-    OS << format("%9" PRIu64 ":", Block.getCount());
-  OS << format("%5u-block %2u\n", LineIndex + 1, BlockNo++);
-}
-
-/// printBranchInfo - Print conditional branch probabilities.
-void FileInfo::printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
-                               GCOVCoverage &Coverage, uint32_t &EdgeNo) {
-  SmallVector<uint64_t, 16> BranchCounts;
-  uint64_t TotalCounts = 0;
-  for (const GCOVEdge *Edge : Block.dsts()) {
-    BranchCounts.push_back(Edge->Count);
-    TotalCounts += Edge->Count;
-    if (Block.getCount())
-      ++Coverage.BranchesExec;
-    if (Edge->Count)
-      ++Coverage.BranchesTaken;
-    ++Coverage.Branches;
-
-    if (Options.FuncCoverage) {
-      const GCOVFunction *Function = &Block.getParent();
-      GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
-      if (Block.getCount())
-        ++FuncCoverage.BranchesExec;
-      if (Edge->Count)
-        ++FuncCoverage.BranchesTaken;
-      ++FuncCoverage.Branches;
-    }
-  }
-
-  for (uint64_t N : BranchCounts)
-    OS << format("branch %2u ", EdgeNo++)
-       << formatBranchInfo(Options, N, TotalCounts) << "\n";
-}
-
-/// printUncondBranchInfo - Print unconditional branch probabilities.
-void FileInfo::printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
-                                     uint64_t Count) const {
-  OS << format("unconditional %2u ", EdgeNo++)
-     << formatBranchInfo(Options, Count, Count) << "\n";
-}
-
-// printCoverage - Print generic coverage info used by both printFuncCoverage
-// and printFileCoverage.
-void FileInfo::printCoverage(raw_ostream &OS,
-                             const GCOVCoverage &Coverage) const {
-  OS << format("Lines executed:%.2f%% of %u\n",
-               double(Coverage.LinesExec) * 100 / Coverage.LogicalLines,
-               Coverage.LogicalLines);
-  if (Options.BranchInfo) {
-    if (Coverage.Branches) {
-      OS << format("Branches executed:%.2f%% of %u\n",
-                   double(Coverage.BranchesExec) * 100 / Coverage.Branches,
-                   Coverage.Branches);
-      OS << format("Taken at least once:%.2f%% of %u\n",
-                   double(Coverage.BranchesTaken) * 100 / Coverage.Branches,
-                   Coverage.Branches);
-    } else {
-      OS << "No branches\n";
-    }
-    OS << "No calls\n"; // to be consistent with gcov
-  }
-}
-
-// printFuncCoverage - Print per-function coverage info.
-void FileInfo::printFuncCoverage(raw_ostream &OS) const {
-  for (const auto &FC : FuncCoverages) {
-    const GCOVCoverage &Coverage = FC.second;
-    OS << "Function '" << Coverage.Name << "'\n";
-    printCoverage(OS, Coverage);
-    OS << "\n";
-  }
-}
-
-// printFileCoverage - Print per-file coverage info.
-void FileInfo::printFileCoverage(raw_ostream &OS) const {
-  for (const auto &FC : FileCoverages) {
-    const std::string &Filename = FC.first;
-    const GCOVCoverage &Coverage = FC.second;
-    OS << "File '" << Coverage.Name << "'\n";
-    printCoverage(OS, Coverage);
-    if (!Options.NoOutput)
-      OS << Coverage.Name << ":creating '" << Filename << "'\n";
-    OS << "\n";
-  }
-}

src/plugin/GCOV.h

@@ -1,460 +0,0 @@
-//===- GCOV.h - LLVM coverage tool ------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This header provides the interface to read and write coverage files that
-// use 'gcov' format.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_PROFILEDATA_GCOV_H
-#define LLVM_PROFILEDATA_GCOV_H
-
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/MapVector.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/iterator.h"
-#include "llvm/ADT/iterator_range.h"
-#include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Support/raw_ostream.h"
-#include <cassert>
-#include <cstddef>
-#include <cstdint>
-#include <memory>
-#include <string>
-#include <utility>
-
-namespace llvm {
-
-class GCOVFunction;
-class GCOVBlock;
-class FileInfo;
-
-namespace GCOV {
-
-enum GCOVVersion { V402, V404, V704 };
-
-/// \brief A struct for passing gcov options between functions.
-struct Options {
-  Options(bool A, bool B, bool C, bool F, bool P, bool U, bool L, bool N)
-      : AllBlocks(A), BranchInfo(B), BranchCount(C), FuncCoverage(F),
-        PreservePaths(P), UncondBranch(U), LongFileNames(L), NoOutput(N) {}
-
-  bool AllBlocks;
-  bool BranchInfo;
-  bool BranchCount;
-  bool FuncCoverage;
-  bool PreservePaths;
-  bool UncondBranch;
-  bool LongFileNames;
-  bool NoOutput;
-};
-
-} // end namespace GCOV
-
-/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific
-/// read operations.
-class GCOVBuffer {
-public:
-  GCOVBuffer(MemoryBuffer *B) : Buffer(B) {}
-
-  /// readGCNOFormat - Check GCNO signature is valid at the beginning of buffer.
-  bool readGCNOFormat() {
-    StringRef File = Buffer->getBuffer().slice(0, 4);
-    if (File != "oncg") {
-      errs() << "Unexpected file type: " << File << ".\n";
-      return false;
-    }
-    Cursor = 4;
-    return true;
-  }
-
-  /// readGCDAFormat - Check GCDA signature is valid at the beginning of buffer.
-  bool readGCDAFormat() {
-    StringRef File = Buffer->getBuffer().slice(0, 4);
-    if (File != "adcg") {
-      errs() << "Unexpected file type: " << File << ".\n";
-      return false;
-    }
-    Cursor = 4;
-    return true;
-  }
-
-  /// readGCOVVersion - Read GCOV version.
-  bool readGCOVVersion(GCOV::GCOVVersion &Version) {
-    StringRef VersionStr = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (VersionStr == "*204") {
-      Cursor += 4;
-      Version = GCOV::V402;
-      return true;
-    }
-    if (VersionStr == "*404") {
-      Cursor += 4;
-      Version = GCOV::V404;
-      return true;
-    }
-    if (VersionStr == "*704") {
-      Cursor += 4;
-      Version = GCOV::V704;
-      return true;
-    }
-    errs() << "Unexpected version: " << VersionStr << ".\n";
-    return false;
-  }
-
-  /// readFunctionTag - If cursor points to a function tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readFunctionTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readBlockTag - If cursor points to a block tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readBlockTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x41' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readEdgeTag - If cursor points to an edge tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readEdgeTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x43' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readLineTag - If cursor points to a line tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readLineTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x45' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readArcTag - If cursor points to an gcda arc tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readArcTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\xa1' ||
-        Tag[3] != '\1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readObjectTag - If cursor points to an object summary tag then increment
-  /// the cursor and return true otherwise return false.
-  bool readObjectTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\xa1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readProgramTag - If cursor points to a program summary tag then increment
-  /// the cursor and return true otherwise return false.
-  bool readProgramTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\xa3') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  bool readInt(uint32_t &Val) {
-    if (Buffer->getBuffer().size() < Cursor + 4) {
-      errs() << "Unexpected end of memory buffer: " << Cursor + 4 << ".\n";
-      return false;
-    }
-    StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    Cursor += 4;
-    Val = *(const uint32_t *)(Str.data());
-    return true;
-  }
-
-  bool readInt64(uint64_t &Val) {
-    uint32_t Lo, Hi;
-    if (!readInt(Lo) || !readInt(Hi))
-      return false;
-    Val = ((uint64_t)Hi << 32) | Lo;
-    return true;
-  }
-
-  bool readString(StringRef &Str) {
-    uint32_t Len = 0;
-    // Keep reading until we find a non-zero length. This emulates gcov's
-    // behaviour, which appears to do the same.
-    while (Len == 0)
-      if (!readInt(Len))
-        return false;
-    Len *= 4;
-    if (Buffer->getBuffer().size() < Cursor + Len) {
-      errs() << "Unexpected end of memory buffer: " << Cursor + Len << ".\n";
-      return false;
-    }
-    Str = Buffer->getBuffer().slice(Cursor, Cursor + Len).split('\0').first;
-    Cursor += Len;
-    return true;
-  }
-
-  uint64_t getCursor() const { return Cursor; }
-  void advanceCursor(uint32_t n) { Cursor += n * 4; }
-
-private:
-  MemoryBuffer *Buffer;
-  uint64_t Cursor = 0;
-};
-
-/// GCOVFile - Collects coverage information for one pair of coverage file
-/// (.gcno and .gcda).
-class GCOVFile {
-public:
-  GCOVFile() = default;
-
-  bool readGCNO(GCOVBuffer &Buffer);
-  bool readGCDA(GCOVBuffer &Buffer);
-  uint32_t getChecksum() const { return Checksum; }
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  bool GCNOInitialized = false;
-  GCOV::GCOVVersion Version;
-  uint32_t Checksum = 0;
-  SmallVector<std::unique_ptr<GCOVFunction>, 16> Functions;
-  uint32_t RunCount = 0;
-  uint32_t ProgramCount = 0;
-};
-
-/// GCOVEdge - Collects edge information.
-struct GCOVEdge {
-  GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D) {}
-
-  GCOVBlock &Src;
-  GCOVBlock &Dst;
-  uint64_t Count = 0;
-};
-
-/// GCOVFunction - Collects function information.
-class GCOVFunction {
-public:
-  using BlockIterator = pointee_iterator<SmallVectorImpl<
-      std::unique_ptr<GCOVBlock>>::const_iterator>;
-
-  GCOVFunction(GCOVFile &P) : Parent(P) {}
-
-  bool readGCNO(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
-  bool readGCDA(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
-  StringRef getName() const { return Name; }
-  StringRef getFilename() const { return Filename; }
-  size_t getNumBlocks() const { return Blocks.size(); }
-  uint64_t getEntryCount() const;
-  uint64_t getExitCount() const;
-
-  BlockIterator block_begin() const { return Blocks.begin(); }
-  BlockIterator block_end() const { return Blocks.end(); }
-  iterator_range<BlockIterator> blocks() const {
-    return make_range(block_begin(), block_end());
-  }
-
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  GCOVFile &Parent;
-  uint32_t Ident = 0;
-  uint32_t Checksum;
-  uint32_t LineNumber = 0;
-  StringRef Name;
-  StringRef Filename;
-  SmallVector<std::unique_ptr<GCOVBlock>, 16> Blocks;
-  SmallVector<std::unique_ptr<GCOVEdge>, 16> Edges;
-};
-
-/// GCOVBlock - Collects block information.
-class GCOVBlock {
-  struct EdgeWeight {
-    EdgeWeight(GCOVBlock *D) : Dst(D) {}
-
-    GCOVBlock *Dst;
-    uint64_t Count = 0;
-  };
-
-  struct SortDstEdgesFunctor {
-    bool operator()(const GCOVEdge *E1, const GCOVEdge *E2) {
-      return E1->Dst.Number < E2->Dst.Number;
-    }
-  };
-
-public:
-  using EdgeIterator = SmallVectorImpl<GCOVEdge *>::const_iterator;
-
-  GCOVBlock(GCOVFunction &P, uint32_t N) : Parent(P), Number(N) {}
-  ~GCOVBlock();
-
-  const GCOVFunction &getParent() const { return Parent; }
-  void addLine(uint32_t N) { Lines.push_back(N); }
-  uint32_t getLastLine() const { return Lines.back(); }
-  void addCount(size_t DstEdgeNo, uint64_t N);
-  uint64_t getCount() const { return Counter; }
-
-  void addSrcEdge(GCOVEdge *Edge) {
-    assert(&Edge->Dst == this); // up to caller to ensure edge is valid
-    SrcEdges.push_back(Edge);
-  }
-
-  void addDstEdge(GCOVEdge *Edge) {
-    assert(&Edge->Src == this); // up to caller to ensure edge is valid
-    // Check if adding this edge causes list to become unsorted.
-    if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
-      DstEdgesAreSorted = false;
-    DstEdges.push_back(Edge);
-  }
-
-  size_t getNumSrcEdges() const { return SrcEdges.size(); }
-  size_t getNumDstEdges() const { return DstEdges.size(); }
-  void sortDstEdges();
-
-  EdgeIterator src_begin() const { return SrcEdges.begin(); }
-  EdgeIterator src_end() const { return SrcEdges.end(); }
-  iterator_range<EdgeIterator> srcs() const {
-    return make_range(src_begin(), src_end());
-  }
-
-  EdgeIterator dst_begin() const { return DstEdges.begin(); }
-  EdgeIterator dst_end() const { return DstEdges.end(); }
-  iterator_range<EdgeIterator> dsts() const {
-    return make_range(dst_begin(), dst_end());
-  }
-
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  GCOVFunction &Parent;
-  uint32_t Number;
-  uint64_t Counter = 0;
-  bool DstEdgesAreSorted = true;
-  SmallVector<GCOVEdge *, 16> SrcEdges;
-  SmallVector<GCOVEdge *, 16> DstEdges;
-  SmallVector<uint32_t, 16> Lines;
-};
-
-class FileInfo {
-  // It is unlikely--but possible--for multiple functions to be on the same
-  // line.
-  // Therefore this typedef allows LineData.Functions to store multiple
-  // functions
-  // per instance. This is rare, however, so optimize for the common case.
-  using FunctionVector = SmallVector<const GCOVFunction *, 1>;
-  using FunctionLines = DenseMap<uint32_t, FunctionVector>;
-  using BlockVector = SmallVector<const GCOVBlock *, 4>;
-  using BlockLines = DenseMap<uint32_t, BlockVector>;
-
-  struct LineData {
-    LineData() = default;
-
-    BlockLines Blocks;
-    FunctionLines Functions;
-    uint32_t LastLine = 0;
-  };
-
-  struct GCOVCoverage {
-    GCOVCoverage(StringRef Name) : Name(Name) {}
-
-    StringRef Name;
-
-    uint32_t LogicalLines = 0;
-    uint32_t LinesExec = 0;
-
-    uint32_t Branches = 0;
-    uint32_t BranchesExec = 0;
-    uint32_t BranchesTaken = 0;
-  };
-
-public:
-  FileInfo(const GCOV::Options &Options) : Options(Options) {}
-
-  void addBlockLine(StringRef Filename, uint32_t Line, const GCOVBlock *Block) {
-    if (Line > LineInfo[Filename].LastLine)
-      LineInfo[Filename].LastLine = Line;
-    LineInfo[Filename].Blocks[Line - 1].push_back(Block);
-  }
-
-  void addFunctionLine(StringRef Filename, uint32_t Line,
-                       const GCOVFunction *Function) {
-    if (Line > LineInfo[Filename].LastLine)
-      LineInfo[Filename].LastLine = Line;
-    LineInfo[Filename].Functions[Line - 1].push_back(Function);
-  }
-
-  void setRunCount(uint32_t Runs) { RunCount = Runs; }
-  void setProgramCount(uint32_t Programs) { ProgramCount = Programs; }
-  void print(raw_ostream &OS, StringRef MainFilename, StringRef GCNOFile,
-             StringRef GCDAFile);
-
-private:
-  std::string getCoveragePath(StringRef Filename, StringRef MainFilename);
-  std::unique_ptr<raw_ostream> openCoveragePath(StringRef CoveragePath);
-  void printFunctionSummary(raw_ostream &OS, const FunctionVector &Funcs) const;
-  void printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
-                      uint32_t LineIndex, uint32_t &BlockNo) const;
-  void printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
-                       GCOVCoverage &Coverage, uint32_t &EdgeNo);
-  void printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
-                             uint64_t Count) const;
-
-  void printCoverage(raw_ostream &OS, const GCOVCoverage &Coverage) const;
-  void printFuncCoverage(raw_ostream &OS) const;
-  void printFileCoverage(raw_ostream &OS) const;
-
-  const GCOV::Options &Options;
-  StringMap<LineData> LineInfo;
-  uint32_t RunCount = 0;
-  uint32_t ProgramCount = 0;
-
-  using FileCoverageList = SmallVector<std::pair<std::string, GCOVCoverage>, 4>;
-  using FuncCoverageMap = MapVector<const GCOVFunction *, GCOVCoverage>;
-
-  FileCoverageList FileCoverages;
-  FuncCoverageMap FuncCoverages;
-};
-
-} // end namespace llvm
-
-#endif // LLVM_SUPPORT_GCOV_H

src/plugin/cycle_estimate.cpp

@@ -1,94 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
-
-#include "iss/plugin/cycle_estimate.h"
-
-#include <iss/arch_if.h>
-#include <util/logging.h>
-#include <fstream>
-
-iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
-: arch_instr(nullptr)
-{
-    if (config_file_name.length() > 0) {
-        std::ifstream is(config_file_name);
-        if (is.is_open()) {
-            try {
-                is >> root;
-            } catch (Json::RuntimeError &e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
-        }
-    }
-}
-
-iss::plugin::cycle_estimate::~cycle_estimate() {
-}
-
-bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
-	arch_instr = vm.get_arch()->get_instrumentation_if();
-	if(!arch_instr) return false;
-	const std::string  core_name = arch_instr->core_type_name();
-    Json::Value &val = root[core_name];
-    if(!val.isNull() && val.isArray()){
-    	delays.reserve(val.size());
-    	for(auto it:val){
-    		auto name = it["name"];
-    		auto size = it["size"];
-    		auto delay = it["delay"];
-    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
-    		if(delay.isUInt()){
-				delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
-    		} else {
-				delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
-    		}
-    	}
-    } else {
-        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
-    }
-	return true;
-
-}
-
-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
-    assert(arch_instr && "No instrumentation interface available but callback executed");
-	auto entry = delays[instr_info.instr_id];
-	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
-    if (taken && entry.taken > 1)
-        arch_instr->set_curr_instr_cycles(entry.taken);
-    else if (entry.not_taken > 1)
-        arch_instr->set_curr_instr_cycles(entry.not_taken);
-}

src/sysc/core_complex.cpp

@@ -31,37 +31,36 @@
  *******************************************************************************/
 
 // clang-format off
-#include "iss/debugger/gdb_session.h"
-#include "iss/debugger/encoderdecoder.h"
-#include "iss/debugger/server.h"
-#include "iss/debugger/target_adapter_if.h"
-#include "iss/iss.h"
-#include "iss/vm_types.h"
-#include "sysc/core_complex.h"
-#ifdef CORE_TGC_B
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_b.h"
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/encoderdecoder.h>
+#include <iss/debugger/server.h>
+#include <iss/debugger/target_adapter_if.h>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include "iss_factory.h"
+#ifndef WIN32
+#include <iss/plugin/loader.h>
 #endif
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_D
-#include "iss/arch/riscv_hart_mu_p.h"
-#include "iss/arch/tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
-#endif
-#include "scc/report.h"
+#include "sc_core_adapter_if.h"
+#include <iss/arch/tgc_mapper.h>
+#include <scc/report.h>
+#include <util/ities.h>
 #include <iostream>
 #include <sstream>
 #include <array>
+#include <numeric>
+#include <iss/plugin/cycle_estimate.h>
+#include <iss/plugin/instruction_count.h>
+
 // clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN)                                                                                                                    \
-if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
+    if(type == STR(CN)) {                                                                                                                  \
+        std::tie(cpu, vm) = create_core<CN##_plat_type>(backend, gdb_port, hart_id);                                                       \
+    } else
 
-#ifdef WITH_SCV
+#ifdef HAS_SCV
 #include <scv.h>
 #else
 #include <scv-tr.h>
@@ -89,136 +88,10 @@ using namespace sc_core;
 
 namespace {
 iss::debugger::encoder_decoder encdec;
-
 std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-}
+} // namespace
 
-template<typename PLAT>
-class core_wrapper_t : public PLAT {
-public:
-    using reg_t       = typename arch::traits<typename PLAT::core>::reg_t;
-    using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
-    using heart_state_t = typename PLAT::hart_state_type;
-    core_wrapper_t(core_complex *owner)
-    : owner(owner) { }
-
-    uint32_t get_mode() { return this->reg.PRIV; }
-
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
-
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
-
-    heart_state_t &get_state() { return this->state; }
-
-    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART) owner->sync(this->reg.icount);
-    }
-
-    sync_type needed_sync() const override { return PRE_SYNC; }
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        if (!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            SCCDEBUG(owner->name())<<"disass: "
-                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
-                << std::setfill(' ') << std::left << instr << s.str();
-        }
-    };
-
-    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
-        }
-    }
-
-    status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
-            // clear MTIP on mtimecmp write
-            if (addr.val == 0x2004000) {
-                reg_t val;
-                this->read_csr(arch::mip, val);
-                if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
-            }
-            return res;
-        }
-    }
-
-    status read_csr(unsigned addr, reg_t &val) override {
-#ifndef CWR_SYSTEMC
-        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret?Ok:Err;
-#else
-		if((addr==arch::time || addr==arch::timeh)){
-			uint64_t time_val = owner->mtime_i.read();
-			if (addr == iss::arch::time) {
-				val = static_cast<reg_t>(time_val);
-			} else if (addr == iss::arch::timeh) {
-				if (sizeof(reg_t) != 4) return iss::Err;
-				val = static_cast<reg_t>(time_val >> 32);
-			}
-			return Ok;
-#endif
-        } else {
-            return PLAT::read_csr(addr, val);
-        }
-    }
-
-    void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        do {
-            sc_core::wait(wfi_evt);
-        } while (this->reg.pending_trap == 0);
-        PLAT::wait_until(flags);
-    }
-
-    void local_irq(short id, bool value) {
-        reg_t mask = 0;
-        switch (id) {
-        case 16: // SW
-            mask = 1 << 3;
-            break;
-        case 17: // timer
-            mask = 1 << 7;
-            break;
-        case 18: // external
-            mask = 1 << 11;
-            break;
-        default:
-            /* do nothing*/
-            break;
-        }
-        if (value) {
-            this->csr[arch::mip] |= mask;
-            wfi_evt.notify();
-        } else
-            this->csr[arch::mip] &= ~mask;
-        this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
-    }
-
-private:
-    core_complex *const owner;
-    sc_event wfi_evt;
-};
-
-int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
-             debugger::target_adapter_if *tgt_adapter) {
+int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter) {
     if(argc > 1) {
         if(strcasecmp(argv[1], "print_time") == 0) {
             std::string t = sc_time_stamp().to_string();
@@ -252,11 +125,15 @@ using vm_ptr= std::unique_ptr<iss::vm_if>;
 
 class core_wrapper {
 public:
-    core_wrapper(core_complex *owner) : owner(owner) { }
+    core_wrapper(core_complex* owner)
+    : owner(owner) {}
 
     void reset(uint64_t addr) { vm->reset(addr); }
-    inline void start(){vm->start();}
-    inline std::pair<uint64_t, bool> load_file(std::string const& name){ return cpu->load_file(name);};
+    inline void start(bool dump = false) { vm->start(std::numeric_limits<uint64_t>::max(), dump); }
+    inline std::pair<uint64_t, bool> load_file(std::string const& name) {
+        iss::arch_if* cc = cpu->get_arch_if();
+        return cc->load_file(name);
+    };
 
     std::function<unsigned(void)> get_mode;
     std::function<uint64_t(void)> get_state;
@@ -264,52 +141,49 @@ public:
     std::function<void(bool)> set_interrupt_execution;
     std::function<void(short, bool)> local_irq;
 
-    template<typename PLAT>
-    std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
-        auto* lcpu = new core_wrapper_t<PLAT>(owner);
-        lcpu->set_mhartid(hart_id);
-        get_mode = [lcpu]() { return lcpu->get_mode(); };
-        get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
-        get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
-        set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
-        local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
-        if(backend == "interp")
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
-#ifdef WITH_LLVM
-        if(backend == "llvm")
-            return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-#ifdef WITH_TCC
-        if(backend == "tcc")
-    s        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-#endif
-        return {nullptr, nullptr};
-    }
-
     void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
-        CREATE_CORE(tgc_c)
-#ifdef CORE_TGC_B
-        CREATE_CORE(tgc_b)
-#endif
-#ifdef CORE_TGC_D
-        CREATE_CORE(tgc_d)
-#endif
-        {
-            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+        auto& f = sysc::iss_factory::instance();
+        if(type.size() == 0 || type == "?") {
+            std::cout << "Available cores: " << util::join(f.get_names(), ", ") << std::endl;
+            sc_core::sc_stop();
+        } else if(type.find('|') != std::string::npos) {
+            std::tie(cpu, vm) = f.create(type + "|" + backend);
+        } else {
+            auto base_isa = type.substr(0, 5);
+            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
+                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
+            } else {
+                std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
             }
-        auto *srv = debugger::server<debugger::gdb_session>::get();
-        if (srv) tgt_adapter = srv->get_target();
-        if (tgt_adapter)
-            tgt_adapter->add_custom_command(
-                {"sysc", [this](int argc, char *argv[], debugger::out_func of,
-                                debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
-                 "SystemC sub-commands: break <time>, print_time"});
+        }
+        if(!cpu) {
+            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend;
+        }
+        if(!vm) {
+            SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend;
+        }
+        auto* sc_cpu_if = reinterpret_cast<sc_core_adapter_if*>(cpu.get());
+        sc_cpu_if->set_mhartid(hart_id);
+        get_mode = [sc_cpu_if]() { return sc_cpu_if->get_mode(); };
+        get_state = [sc_cpu_if]() { return sc_cpu_if->get_state(); };
+        get_interrupt_execution = [sc_cpu_if]() { return sc_cpu_if->get_interrupt_execution(); };
+        set_interrupt_execution = [sc_cpu_if](bool b) { return sc_cpu_if->set_interrupt_execution(b); };
+        local_irq = [sc_cpu_if](short s, bool b) { return sc_cpu_if->local_irq(s, b); };
 
+        auto* srv = debugger::server<debugger::gdb_session>::get();
+        if(srv)
+            tgt_adapter = srv->get_target();
+        if(tgt_adapter)
+            tgt_adapter->add_custom_command({"sysc",
+                                             [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int {
+                                                 return cmd_sysc(argc, argv, of, df, tgt_adapter);
+                                             },
+                                             "SystemC sub-commands: break <time>, print_time"});
     }
 
     core_complex* const owner;
     vm_ptr vm{nullptr};
-    cpu_ptr cpu{nullptr};
+    sc_cpu_ptr cpu{nullptr};
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
 };
 
@@ -327,16 +201,22 @@ SC_HAS_PROCESS(core_complex);// NOLINT
 #ifndef CWR_SYSTEMC
 core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
+, fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
-, write_lut(tlm_dmi_ext())
-{
+, write_lut(tlm_dmi_ext()) {
     init();
 }
 #endif
 
 void core_complex::init() {
     trc = new core_trace();
-    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+    ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+        auto lut_entry = fetch_lut.getEntry(start);
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            fetch_lut.removeEntry(lut_entry);
+        }
+    });
+    dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = read_lut.getEntry(start);
         if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
             read_lut.removeEntry(lut_entry);
@@ -354,8 +234,11 @@ void core_complex::init(){
     sensitive << sw_irq_i;
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
-    SC_METHOD(global_irq_cb);
-    sensitive << global_irq_i;
+    SC_METHOD(ext_irq_cb);
+    sensitive << ext_irq_i;
+    SC_METHOD(local_irq_cb);
+    for(auto pin : local_irq_i)
+        sensitive << pin;
     trc->m_db = scv_tr_db::get_default_db();
 
     SC_METHOD(forward);
@@ -372,6 +255,8 @@ void core_complex::init(){
 core_complex::~core_complex() {
     delete cpu;
     delete trc;
+    for(auto* p : plugin_list)
+        delete p;
 }
 
 void core_complex::trace(sc_trace_file* trf) const {}
@@ -383,10 +268,42 @@ void core_complex::before_end_of_elaboration() {
     cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
     sc_assert(cpu->vm != nullptr);
     cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
+    if(GET_PROP_VALUE(plugins).length()) {
+        auto p = util::split(GET_PROP_VALUE(plugins), ';');
+        for(std::string const& opt_val : p) {
+            std::string plugin_name = opt_val;
+            std::string filename{"cycles.txt"};
+            std::size_t found = opt_val.find('=');
+            if(found != std::string::npos) {
+                plugin_name = opt_val.substr(0, found);
+                filename = opt_val.substr(found + 1, opt_val.size());
+            }
+            if(plugin_name == "ic") {
+                auto* plugin = new iss::plugin::instruction_count(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else if(plugin_name == "ce") {
+                auto* plugin = new iss::plugin::cycle_estimate(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else {
+#ifndef WIN32
+                std::array<char const*, 1> a{{filename.c_str()}};
+                iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                if(plugin) {
+                    cpu->vm->register_plugin(*plugin);
+                    plugin_list.push_back(plugin);
+                } else
+#endif
+                    SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
+            }
+        }
+    }
 }
 
 void core_complex::start_of_simulation() {
-    quantum_keeper.reset();
+    // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
         string s;
@@ -409,8 +326,10 @@ void core_complex::start_of_simulation() {
 }
 
 bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-    if (trc->m_db == nullptr) return false;
-    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
+    if(trc->m_db == nullptr)
+        return false;
+    if(trc->tr_handle.is_active())
+        trc->tr_handle.end_transaction();
     trc->tr_handle = trc->instr_tr_handle->begin_transaction();
     trc->tr_handle.record_attribute("PC", pc);
     trc->tr_handle.record_attribute("INSTR", instr_str);
@@ -431,22 +350,33 @@ void core_complex::forward() {
 
 void core_complex::set_clock_period(sc_core::sc_time period) {
     curr_clk = period;
-    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
+    if(period == SC_ZERO_TIME)
+        cpu->set_interrupt_execution(true);
 }
 
 void core_complex::rst_cb() {
-    if (rst_i.read()) cpu->set_interrupt_execution(true);
+    if(rst_i.read())
+        cpu->set_interrupt_execution(true);
 }
 
-void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
+void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
 
-void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
+void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
 
-void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
+void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+
+void core_complex::local_irq_cb() {
+    for(auto i = 0U; i < local_irq_i.size(); ++i) {
+        if(local_irq_i[i].event()) {
+            cpu->local_irq(16 + i, local_irq_i[i].read());
+        }
+    }
+}
 
 void core_complex::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
+        wait(SC_ZERO_TIME);
         if(rst_i.read()) {
             cpu->reset(GET_PROP_VALUE(reset_address));
             wait(rst_i.negedge_event());
@@ -454,21 +384,26 @@ void core_complex::run() {
         while(curr_clk.read() == SC_ZERO_TIME) {
             wait(curr_clk.value_changed_event());
         }
+        quantum_keeper.reset();
         cpu->set_interrupt_execution(false);
-        cpu->start();
+        cpu->start(dump_ir);
     } while(cpu->get_interrupt_execution());
     sc_stop();
 }
 
 bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
+    auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
+    auto lut_entry = dmi_lut.getEntry(addr);
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        if(is_fetch)
+            ibus_inc += lut_entry.get_read_latency() / curr_clk;
+        else
+            dbus_inc += lut_entry.get_read_latency() / curr_clk;
         return true;
     } else {
+        auto& sckt = is_fetch ? ibus : dbus;
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_READ_COMMAND);
         gp.set_address(addr);
@@ -483,22 +418,31 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        initiator->b_transport(gp, delay);
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
+        auto pre_delay = delay;
+        dbus->b_transport(gp, delay);
+        if(pre_delay > delay) {
+            quantum_keeper.reset();
+        } else {
+            auto incr = (delay - quantum_keeper.get_local_time()) / curr_clk;
+            if(is_fetch)
+                ibus_inc += incr;
+            else
+                dbus_inc += incr;
+        }
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
         if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if (gp.is_dmi_allowed()) {
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
+            if(sckt->get_direct_mem_ptr(gp, dmi_data)) {
                 if(dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
@@ -507,11 +451,10 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
 
 bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        dbus_inc += lut_entry.get_write_latency() / curr_clk;
         return true;
     } else {
         write_buf.resize(length);
@@ -527,20 +470,24 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        initiator->b_transport(gp, delay);
-        quantum_keeper.set(delay);
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
+        auto pre_delay = delay;
+        dbus->b_transport(gp, delay);
+        if(pre_delay > delay)
+            quantum_keeper.reset();
+        else
+            dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
+        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
+                   << (length == 4   ? *(uint32_t*)data
+                       : length == 2 ? *(uint16_t*)data
+                                     : (unsigned)*data);
         if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if (gp.is_dmi_allowed()) {
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+            if(dbus->get_direct_mem_ptr(gp, dmi_data)) {
                 if(dmi_data.is_write_allowed())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@@ -551,33 +498,16 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
 }
 
 bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
     gp.set_data_ptr(data);
     gp.set_data_length(length);
     gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
-    }
+    return dbus->transport_dbg(gp) == length;
 }
 
 bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
@@ -586,8 +516,7 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
     gp.set_data_ptr(write_buf.data());
     gp.set_data_length(length);
     gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
+    return dbus->transport_dbg(gp) == length;
 }
-}
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */

src/sysc/core_complex.h

@@ -33,28 +33,33 @@
 #ifndef _SYSC_CORE_COMPLEX_H_
 #define _SYSC_CORE_COMPLEX_H_
 
-#include <tlm/scc/initiator_mixin.h>
-#include <scc/traceable.h>
 #include <scc/tick2time.h>
+#include <scc/traceable.h>
 #include <scc/utilities.h>
+#include <tlm/scc/initiator_mixin.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
+#define SOCKET_WIDTH 32
 #else
 #include <cci_configuration>
+#define SOCKET_WIDTH scc::LT
 #endif
+#include <memory>
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
-#include <memory>
 
+namespace iss {
+class vm_plugin;
+}
 namespace sysc {
 
 class tlm_dmi_ext : public tlm::tlm_dmi {
 public:
     bool operator==(const tlm_dmi_ext& o) const {
-        return this->get_granted_access() == o.get_granted_access() &&
-               this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
+        return this->get_granted_access() == o.get_granted_access() && this->get_start_address() == o.get_start_address() &&
+               this->get_end_address() == o.get_end_address();
     }
 
     bool operator!=(const tlm_dmi_ext& o) const { return !operator==(o); }
@@ -66,11 +71,13 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
+
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
+    sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};
 
     sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
 
@@ -81,15 +88,17 @@ public:
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 
     cci::cci_param<bool> enable_disass{"enable_disass", false};
 
+    cci::cci_param<bool> disable_dmi{"disable_dmi", false};
+
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
 
     cci::cci_param<std::string> backend{"backend", "interp"};
 
@@ -99,6 +108,8 @@ public:
 
     cci::cci_param<uint32_t> mhartid{"mhartid", 0};
 
+    cci::cci_param<std::string> plugins{"plugins", ""};
+
     core_complex(sc_core::sc_module_name const& name);
 
 #else
@@ -110,9 +121,11 @@ public:
 
     scml_property<bool> enable_disass{"enable_disass", false};
 
+    scml_property<bool> disable_dmi{"disable_dmi", false};
+
     scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
 
-    scml_property<std::string> core_type{"core_type", "tgc_c"};
+    scml_property<std::string> core_type{"core_type", "tgc5c"};
 
     scml_property<std::string> backend{"backend", "interp"};
 
@@ -122,20 +135,23 @@ public:
 
     scml_property<uint32_t> mhartid{"mhartid", 0};
 
+    scml_property<std::string> plugins{"plugins", ""};
+
     core_complex(sc_core::sc_module_name const& name)
     : sc_module(name)
     , local_irq_i{"local_irq_i", 16}
     , elf_file{"elf_file", ""}
     , enable_disass{"enable_disass", false}
     , reset_address{"reset_address", 0ULL}
-    , core_type{"core_type", "tgc_c"}
+    , core_type{"core_type", "tgc5c"}
     , backend{"backend", "interp"}
     , gdb_server_port{"gdb_server_port", 0}
     , dump_ir{"dump_ir", false}
     , mhartid{"mhartid", 0}
+    , plugins{"plugins", ""}
+    , fetch_lut(tlm_dmi_ext())
     , read_lut(tlm_dmi_ext())
-    , write_lut(tlm_dmi_ext())
-    {
+    , write_lut(tlm_dmi_ext()) {
         init();
     }
 
@@ -143,9 +159,15 @@ public:
 
     ~core_complex();
 
+    inline unsigned get_last_bus_cycles() {
+        auto mem_incr = std::max(ibus_inc, dbus_inc);
+        ibus_inc = dbus_inc = 0;
+        return mem_incr > 1 ? mem_incr : 1;
+    }
+
     inline void sync(uint64_t cycle) {
-        auto time = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(time);
+        auto core_inc = curr_clk * (cycle - last_sync_cycle);
+        quantum_keeper.inc(core_inc);
         if(quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
@@ -166,6 +188,7 @@ public:
     bool disass_output(uint64_t pc, const std::string instr);
 
     void set_clock_period(sc_core::sc_time period);
+
 protected:
     void before_end_of_elaboration() override;
     void start_of_simulation() override;
@@ -174,19 +197,23 @@ protected:
     void rst_cb();
     void sw_irq_cb();
     void timer_irq_cb();
-    void global_irq_cb();
+    void ext_irq_cb();
+    void local_irq_cb();
     uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
+    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    uint64_t ibus_inc{0}, dbus_inc{0};
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
+
 private:
     void init();
+    std::vector<iss::vm_plugin*> plugin_list;
 };
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */
 
 #endif /* _SYSC_CORE_COMPLEX_H_ */

src/sysc/iss_factory.h

@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_
+
+#include "sc_core_adapter_if.h"
+#include <algorithm>
+#include <functional>
+#include <iss/iss.h>
+#include <memory>
+#include <string>
+#include <unordered_map>
+#include <vector>
+
+namespace sysc {
+
+using sc_cpu_ptr = std::unique_ptr<sc_core_adapter_if>;
+using vm_ptr = std::unique_ptr<iss::vm_if>;
+
+class iss_factory {
+public:
+    using base_t = std::tuple<sc_cpu_ptr, vm_ptr>;
+    using create_fn = std::function<base_t(unsigned, void*)>;
+    using registry_t = std::unordered_map<std::string, create_fn>;
+
+    iss_factory() = default;
+    iss_factory(const iss_factory&) = delete;
+    iss_factory& operator=(const iss_factory&) = delete;
+
+    static iss_factory& instance() {
+        static iss_factory bf;
+        return bf;
+    }
+
+    bool register_creator(const std::string& className, create_fn const& fn) {
+        registry[className] = fn;
+        return true;
+    }
+
+    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+        registry_t::const_iterator regEntry = registry.find(className);
+        if(regEntry != registry.end())
+            return regEntry->second(gdb_port, init_data);
+        return {nullptr, nullptr};
+    }
+
+    std::vector<std::string> get_names() {
+        std::vector<std::string> keys{registry.size()};
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+        return keys;
+    }
+
+private:
+    registry_t registry;
+};
+
+} // namespace sysc
+
+#endif /* _ISS_FACTORY_H_ */

src/sysc/register_tgc_c.cpp

@@ -0,0 +1,110 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+// clang-format off
+#include "iss_factory.h"
+#include <iss/arch/tgc5c.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include "sc_core_adapter.h"
+#include "core_complex.h"
+#include <array>
+// clang-format on
+
+namespace iss {
+namespace interp {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|interp",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace interp
+#if defined(WITH_LLVM)
+namespace llvm {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|llvm",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace llvm
+#endif
+#if defined(WITH_TCC)
+namespace tcc {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|tcc",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace tcc
+#endif
+#if defined(WITH_ASMJIT)
+namespace asmjit {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|asmjit",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace asmjit
+#endif
+} // namespace iss

src/sysc/sc_core_adapter.h

@@ -0,0 +1,187 @@
+/*
+ * sc_core_adapter.h
+ *
+ *  Created on: Jul 5, 2023
+ *      Author: eyck
+ */
+
+#ifndef _SYSC_SC_CORE_ADAPTER_H_
+#define _SYSC_SC_CORE_ADAPTER_H_
+
+#include "sc_core_adapter_if.h"
+#include <iostream>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <scc/report.h>
+#include <util/ities.h>
+
+namespace sysc {
+template <typename PLAT> class sc_core_adapter : public PLAT, public sc_core_adapter_if {
+public:
+    using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
+    using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
+    using heart_state_t = typename PLAT::hart_state_type;
+    sc_core_adapter(sysc::tgfs::core_complex* owner)
+    : owner(owner) {}
+
+    iss::arch_if* get_arch_if() override { return this; }
+
+    void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
+
+    uint32_t get_mode() override { return this->reg.PRIV; }
+
+    void set_interrupt_execution(bool v) override { this->interrupt_sim = v ? 1 : 0; }
+
+    bool get_interrupt_execution() override { return this->interrupt_sim; }
+
+    uint64_t get_state() override { return this->state.mstatus.backing.val; }
+
+    void notify_phase(iss::arch_if::exec_phase p) override {
+        if(p == iss::arch_if::ISTART && !first) {
+            auto cycle_incr = owner->get_last_bus_cycles();
+            if(cycle_incr > 1)
+                this->instr_if.update_last_instr_cycles(cycle_incr);
+            owner->sync(this->instr_if.get_total_cycles());
+        }
+        first = false;
+    }
+
+    iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
+
+    void disass_output(uint64_t pc, const std::string instr) override {
+        static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
+        if(!owner->disass_output(pc, instr)) {
+            std::stringstream s;
+            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
+              << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
+            SCCDEBUG(owner->name()) << "disass: "
+                                    << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
+                                    << std::setfill(' ') << std::left << instr << s.str();
+        }
+    };
+
+    iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data) override {
+        if(addr.access && iss::access_type::DEBUG)
+            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+        else {
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
+        }
+    }
+
+    iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) override {
+        if(addr.access && iss::access_type::DEBUG)
+            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+        else {
+            auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) || (sizeof(reg_t) == 8 && addr.val == this->tohost);
+            auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) || (sizeof(reg_t) == 64 && addr.val == this->tohost);
+            if(tohost_lower || tohost_upper) {
+                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                    switch(hostvar >> 48) {
+                    case 0:
+                        if(hostvar != 0x1) {
+                            SCCINFO(owner->name())
+                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
+                        } else {
+                            SCCINFO(owner->name())
+                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
+                        }
+                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
+                        break;
+                    default:
+                        break;
+                    }
+                } else if(tohost_lower)
+                    to_host_wr_cnt++;
+                return iss::Ok;
+            } else {
+                auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
+                // clear MTIP on mtimecmp write
+                if(addr.val == 0x2004000) {
+                    reg_t val;
+                    this->read_csr(iss::arch::mip, val);
+                    if(val & (1ULL << 7))
+                        this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
+                }
+                return res;
+            }
+        }
+    }
+
+    iss::status read_csr(unsigned addr, reg_t& val) override {
+#ifndef CWR_SYSTEMC
+        if((addr == iss::arch::time || addr == iss::arch::timeh) && owner->mtime_o.get_interface(0)) {
+            uint64_t time_val;
+            bool ret = owner->mtime_o->nb_peek(time_val);
+            if(addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if(addr == iss::arch::timeh) {
+                if(sizeof(reg_t) != 4)
+                    return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return ret ? iss::Ok : iss::Err;
+#else
+        if((addr == iss::arch::time || addr == iss::arch::timeh)) {
+            uint64_t time_val = owner->mtime_i.read();
+            if(addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if(addr == iss::arch::timeh) {
+                if(sizeof(reg_t) != 4)
+                    return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return iss::Ok;
+#endif
+        } else {
+            return PLAT::read_csr(addr, val);
+        }
+    }
+
+    void wait_until(uint64_t flags) override {
+        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
+        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
+            sc_core::wait(wfi_evt);
+        }
+        PLAT::wait_until(flags);
+    }
+
+    void local_irq(short id, bool value) override {
+        reg_t mask = 0;
+        switch(id) {
+        case 3: // SW
+            mask = 1 << 3;
+            break;
+        case 7: // timer
+            mask = 1 << 7;
+            break;
+        case 11: // external
+            mask = 1 << 11;
+            break;
+        default:
+            if(id > 15)
+                mask = 1 << id;
+            break;
+        }
+        if(value) {
+            this->csr[iss::arch::mip] |= mask;
+            wfi_evt.notify();
+        } else
+            this->csr[iss::arch::mip] &= ~mask;
+        this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+    }
+
+private:
+    sysc::tgfs::core_complex* const owner;
+    sc_core::sc_event wfi_evt;
+    uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
+    unsigned to_host_wr_cnt = 0;
+    bool first{true};
+};
+} // namespace sysc
+#endif /* _SYSC_SC_CORE_ADAPTER_H_ */

src/sysc/sc_core_adapter_if.h

@@ -0,0 +1,30 @@
+/*
+ * sc_core_adapter.h
+ *
+ *  Created on: Jul 5, 2023
+ *      Author: eyck
+ */
+
+#ifndef _SYSC_SC_CORE_ADAPTER_IF_H_
+#define _SYSC_SC_CORE_ADAPTER_IF_H_
+
+#include "core_complex.h"
+#include <iostream>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <scc/report.h>
+#include <util/ities.h>
+
+namespace sysc {
+struct sc_core_adapter_if {
+    virtual iss::arch_if* get_arch_if() = 0;
+    virtual void set_mhartid(unsigned) = 0;
+    virtual uint32_t get_mode() = 0;
+    virtual uint64_t get_state() = 0;
+    virtual bool get_interrupt_execution() = 0;
+    virtual void set_interrupt_execution(bool v) = 0;
+    virtual void local_irq(short id, bool value) = 0;
+    virtual ~sc_core_adapter_if() = default;
+};
+} // namespace sysc
+#endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */

src/vm/fp_functions.cpp

@@ -35,32 +35,24 @@
 #include "fp_functions.h"
 
 extern "C" {
-#include <softfloat.h>
 #include "internals.h"
 #include "specialize.h"
+#include <softfloat.h>
 }
 
 #include <limits>
 
 using this_t = uint8_t*;
 const uint8_t rmm_map[] = {
-        softfloat_round_near_even /*RNE*/,
-        softfloat_round_minMag/*RTZ*/,
-        softfloat_round_min/*RDN*/,
-        softfloat_round_max/*RUP?*/,
-        softfloat_round_near_maxMag /*RMM*/,
-        softfloat_round_max/*RTZ*/,
-        softfloat_round_max/*RTZ*/,
-        softfloat_round_max/*RTZ*/,
+    softfloat_round_near_even /*RNE*/,   softfloat_round_minMag /*RTZ*/, softfloat_round_min /*RDN*/, softfloat_round_max /*RUP?*/,
+    softfloat_round_near_maxMag /*RMM*/, softfloat_round_max /*RTZ*/,    softfloat_round_max /*RTZ*/, softfloat_round_max /*RTZ*/,
 };
 
 const uint32_t quiet_nan32 = 0x7fC00000;
 
 extern "C" {
 
-uint32_t fget_flags(){
-    return softfloat_exceptionFlags&0x1f;
-}
+uint32_t fget_flags() { return softfloat_exceptionFlags & 0x1f; }
 
 uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
     float32_t v1f{v1}, v2f{v2};
@@ -110,7 +102,8 @@ uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
     switch(op) {
     case 0:
         if(nan | snan) {
-            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
+            if(snan)
+                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
             return f32_eq(v1f, v2f) ? 1 : 0;
@@ -160,7 +153,8 @@ uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mod
     softfloat_roundingMode = rmm_map[mode & 0x7];
     softfloat_exceptionFlags = 0;
     float32_t res = softfloat_mulAddF32(v1, v2, v3, op & 0x1);
-    if(op>1) res.v ^= 1ULL<<31;
+    if(op > 1)
+        res.v ^= 1ULL << 31;
     return res.v;
 }
 
@@ -170,11 +164,11 @@ uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
     bool v1_snan = softfloat_isSigNaNF32UI(v1);
     bool v2_snan = softfloat_isSigNaNF32UI(v2);
-    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_snan || v2_snan)
+        softfloat_raiseFlags(softfloat_flag_invalid);
     if(v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
-    else
-        if (v2_nan || v2_snan)
+    else if(v2_nan || v2_snan)
         return v1;
     else {
         if((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
@@ -202,17 +196,10 @@ uint32_t fclass_s( uint32_t v1 ){
     bool isNaN = isNaNF32UI(uiA);
     bool isSNaN = softfloat_isSigNaNF32UI(uiA);
 
-    return
-        (  sign && infOrNaN && fracZero )          << 0 |
-        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
-        (  sign && subnormalOrZero && !fracZero )  << 2 |
-        (  sign && subnormalOrZero && fracZero )   << 3 |
-        ( !sign && infOrNaN && fracZero )          << 7 |
-        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
-        ( !sign && subnormalOrZero && !fracZero )  << 5 |
-        ( !sign && subnormalOrZero && fracZero )   << 4 |
-        ( isNaN &&  isSNaN )                       << 8 |
-        ( isNaN && !isSNaN )                       << 9;
+    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
+           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
+           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
+           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
 }
 
 uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
@@ -287,7 +274,8 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
     switch(op) {
     case 0:
         if(nan | snan) {
-            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
+            if(snan)
+                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
             return f64_eq(v1f, v2f) ? 1 : 0;
@@ -337,7 +325,8 @@ uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mod
     softfloat_roundingMode = rmm_map[mode & 0x7];
     softfloat_exceptionFlags = 0;
     float64_t res = softfloat_mulAddF64(v1, v2, v3, op & 0x1);
-    if(op>1) res.v ^= 1ULL<<63;
+    if(op > 1)
+        res.v ^= 1ULL << 63;
     return res.v;
 }
 
@@ -347,22 +336,19 @@ uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
     bool v1_snan = softfloat_isSigNaNF64UI(v1);
     bool v2_snan = softfloat_isSigNaNF64UI(v2);
-    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_snan || v2_snan)
+        softfloat_raiseFlags(softfloat_flag_invalid);
     if(v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
-    else
-        if (v2_nan || v2_snan)
+    else if(v2_nan || v2_snan)
         return v1;
     else {
         if((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
-                return op == 0 ?
-                        ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
-                        ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
+            return op == 0 ? ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2)
+                           : ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
         } else {
             float64_t v1f{v1}, v2f{v2};
-                return op == 0 ?
-                        (f64_lt(v1f, v2f) ? v1 : v2) :
-                        (f64_lt(v1f, v2f) ? v2 : v1);
+            return op == 0 ? (f64_lt(v1f, v2f) ? v1 : v2) : (f64_lt(v1f, v2f) ? v2 : v1);
         }
     }
 }
@@ -383,17 +369,10 @@ uint64_t fclass_d(uint64_t v1  ){
     bool isNaN = isNaNF64UI(uiA);
     bool isSNaN = softfloat_isSigNaNF64UI(uiA);
 
-    return
-        (  sign && infOrNaN && fracZero )          << 0 |
-        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
-        (  sign && subnormalOrZero && !fracZero )  << 2 |
-        (  sign && subnormalOrZero && fracZero )   << 3 |
-        ( !sign && infOrNaN && fracZero )          << 7 |
-        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
-        ( !sign && subnormalOrZero && !fracZero )  << 5 |
-        ( !sign && subnormalOrZero && fracZero )   << 4 |
-        ( isNaN &&  isSNaN )                       << 8 |
-        ( isNaN && !isSNaN )                       << 9;
+    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
+           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
+           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
+           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
 }
 
 uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
@@ -445,4 +424,3 @@ uint32_t unbox_s(uint64_t v){
         return v & std::numeric_limits<uint32_t>::max();
 }
 }
-

src/vm/instruction_decoder.cpp

@@ -0,0 +1,103 @@
+/*******************************************************************************
+ * Copyright (C) 2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       alex@minres.com - initial implementation
+ ******************************************************************************/
+
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <limits>
+#include <numeric>
+#include <vector>
+#include <vm/instruction_decoder.h>
+
+decoder::decoder(std::vector<generic_instruction_descriptor> instr_list) {
+    for(auto instr : instr_list) {
+        root.instrs.push_back(instr);
+    }
+    populate_decoding_tree(root);
+}
+
+void decoder::populate_decoding_tree(decoding_tree_node& parent) {
+    // create submask
+    parent.submask =
+        std::accumulate(parent.instrs.begin(), parent.instrs.end(), std::numeric_limits<uint32_t>::max(),
+                        [](int current_submask, const generic_instruction_descriptor& instr) { return current_submask & instr.mask; });
+    //  put each instr according to submask&encoding into children
+    for(auto instr : parent.instrs) {
+        bool foundMatch = false;
+        for(auto& child : parent.children) {
+            // use value as identifying trait
+            if(child.value == (instr.value & parent.submask)) {
+                child.instrs.push_back(instr);
+                foundMatch = true;
+            }
+        }
+        if(!foundMatch) {
+            decoding_tree_node child = decoding_tree_node(instr.value & parent.submask);
+            child.instrs.push_back(instr);
+            parent.children.push_back(child);
+        }
+    }
+    parent.instrs.clear();
+    // call populate_decoding_tree for all children
+    if(parent.children.size() > 1)
+        for(auto& child : parent.children) {
+            populate_decoding_tree(child);
+        }
+    else {
+        // sort instrs by value of the mask, so we have the least restrictive mask last
+        std::sort(parent.children[0].instrs.begin(), parent.children[0].instrs.end(),
+                  [](const generic_instruction_descriptor& instr1, const generic_instruction_descriptor& instr2) {
+                      return instr1.mask > instr2.mask;
+                  });
+    }
+}
+uint32_t decoder::decode_instr(uint32_t word) { return _decode_instr(this->root, word); }
+uint32_t decoder::_decode_instr(decoding_tree_node const& node, uint32_t word) {
+    if(!node.children.size()) {
+        if(node.instrs.size() == 1)
+            return node.instrs[0].index;
+        for(auto instr : node.instrs) {
+            if((instr.mask & word) == instr.value)
+                return instr.index;
+        }
+    } else {
+        for(auto child : node.children) {
+            if(child.value == (node.submask & word)) {
+                return _decode_instr(child, word);
+            }
+        }
+    }
+    return std::numeric_limits<uint32_t>::max();
+}

src/vm/instruction_decoder.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,35 +28,36 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- *******************************************************************************/
+ * Contributors:
+ *       alex@minres.com - initial implementation
+ ******************************************************************************/
 
-#ifndef _ISS_FACTORY_H_
-#define _ISS_FACTORY_H_
+#include <cstddef>
+#include <cstdint>
+#include <limits>
+#include <vector>
 
-#include <iss/iss.h>
+struct generic_instruction_descriptor {
+    uint32_t value;
+    uint32_t mask;
+    uint32_t index;
+};
 
-namespace iss {
+struct decoding_tree_node {
+    std::vector<generic_instruction_descriptor> instrs;
+    std::vector<decoding_tree_node> children;
+    uint32_t submask = std::numeric_limits<uint32_t>::max();
+    uint32_t value;
+    decoding_tree_node(uint32_t value)
+    : value(value) {}
+};
+class decoder {
+public:
+    decoder(std::vector<generic_instruction_descriptor> instr_list);
+    uint32_t decode_instr(uint32_t word);
 
-using cpu_ptr = std::unique_ptr<iss::arch_if>;
-using vm_ptr= std::unique_ptr<iss::vm_if>;
-
-template<typename PLAT>
-std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
-    using core_type = typename PLAT::core;
-    core_type* lcpu = new PLAT();
-    if(backend == "interp")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-#ifdef WITH_LLVM
-    if(backend == "llvm")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-#ifdef WITH_LLVM
-    if(backend == "tcc")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-#endif
-    return {nullptr, nullptr};
-}
-
-}
-
-#endif /* _ISS_FACTORY_H_ */
+private:
+    decoding_tree_node root{decoding_tree_node(std::numeric_limits<uint32_t>::max())};
+    void populate_decoding_tree(decoding_tree_node& root);
+    uint32_t _decode_instr(decoding_tree_node const& node, uint32_t word);
+};

src/vm/interp/.gitignore

@@ -1 +0,0 @@
-/vm_tgc_*.cpp