fixes missing namespaces

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output

.gitignore

@@ -30,4 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
+/*.yaml
+/*.json

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
-	path = gen_input/CoreDSL-Instruction-Set-Description
-	url = ../CoreDSL-Instruction-Set-Description.git

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

CMakeLists.txt

@@ -1,20 +1,23 @@
 cmake_minimum_required(VERSION 3.12)
-
-project("riscv" VERSION 1.0.0)
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
-conan_basic_setup()
+find_package(elfio QUIET)
+find_package(Boost COMPONENTS coroutine)
+find_package(jsoncpp)
 
-find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
 if(WITH_LLVM)
-	if(DEFINED ENV{LLVM_HOME})
-		find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-	endif(DEFINED ENV{LLVM_HOME})
-	find_package(LLVM REQUIRED CONFIG)
-	message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-	message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-	llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+    if(DEFINED ENV{LLVM_HOME})
+        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+    endif(DEFINED ENV{LLVM_HOME})
+    find_package(LLVM REQUIRED CONFIG)
+    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
 endif()
 
 #Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
@@ -26,98 +29,195 @@ endif()
 
 add_subdirectory(softfloat)
 
-# library files
-FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
-set(LIB_HEADERS ${RiscVSCHeaders} )
 set(LIB_SOURCES 
-	src/iss/tgf_b.cpp
-	src/iss/tgf_c.cpp
+    src/iss/plugin/instruction_count.cpp
+	src/iss/arch/tgc_c.cpp
+	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
-	src/vm/tcc/vm_tgf_b.cpp
-	src/vm/tcc/vm_tgf_c.cpp
-	src/vm/interp/vm_tgf_b.cpp
-	src/vm/interp/vm_tgf_c.cpp
-    src/plugin/instruction_count.cpp
-    src/plugin/cycle_estimate.cpp
 )
+
+# library files
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+    FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+    foreach(FILEPATH ${GEN_ISS_SOURCES})
+        get_filename_component(CORE ${FILEPATH} NAME_WE)
+        string(TOUPPER ${CORE} CORE)
+        list(APPEND LIB_DEFINES CORE_${CORE})
+    endforeach()
+    message("Defines are ${LIB_DEFINES}")
+endif()
+
+if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
+    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
+endif()
+
 if(WITH_LLVM)
-set(LIB_SOURCES ${LIB_SOURCES}
-	src/vm/llvm/fp_impl.cpp
-	src/vm/llvm/vm_tgf_b.cpp
-	src/vm/llvm/vm_tgf_c.cpp
-)
+	FILE(GLOB LLVM_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
+	)
+	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+endif()
+
+if(WITH_TCC)
+	FILE(GLOB TCC_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
+	)
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
 
 # Define the library
-add_library(riscv SHARED ${LIB_SOURCES})
-target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
-target_include_directories(riscv PUBLIC incl ../external/elfio)
-target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-set_target_properties(riscv PROPERTIES
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
+# list code gen dependencies
+if(TARGET ${CORE_NAME}_cpp)
+    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
+endif()
+
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
+    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
+endif()
+target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
+if(TARGET jsoncpp::jsoncpp)
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
+else()
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
+endif()
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
+endif()
+if(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+if(TARGET lz4::lz4)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
+    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
+endif()
+if(TARGET RapidJSON::RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
+elseif(TARGET RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
+endif()
+
+
+set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
   FRAMEWORK FALSE
-  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )
-
-if(SystemC_FOUND)
-	add_library(riscv_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC) 
-	target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
-	
-	if(SCV_FOUND)   
-	    target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
-	    target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
-	endif()
-	target_link_libraries(riscv_sc PUBLIC riscv scc )
-	if(WITH_LLVM)
-		target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
-	endif()
-	target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
-	set_target_properties(riscv_sc PROPERTIES
-	  VERSION ${PROJECT_VERSION}
-	  FRAMEWORK FALSE
-	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
-	)
-endif()
-
-project("riscv-sim")
-add_executable(riscv-sim src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
-target_include_directories(riscv-sim PRIVATE ../external/libGIS)
-if(WITH_LLVM)
-	target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
-	target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
-endif()
-# Links the target exe against the libraries
-target_link_libraries(riscv-sim riscv)
-target_link_libraries(riscv-sim jsoncpp)
-target_link_libraries(riscv-sim external)
-target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
-if (Tcmalloc_FOUND)
-    target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
-endif(Tcmalloc_FOUND)
-
-install(TARGETS riscv riscv-sim
+install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel   # headers for mac (note the different component -> different package)
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
   INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
-
-
-
+install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
+        DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
+        FILES_MATCHING # install only matched files
+        PATTERN "*.h" # select header files
+        )
+###############################################################################
 #
-# SYSTEM PACKAGING (RPM, TGZ, ...)
-# _____________________________________________________________________________
+###############################################################################
+project(tgc-sim)
+find_package(Boost COMPONENTS program_options thread REQUIRED)
 
-#include(CPackConfig)
+add_executable(${PROJECT_NAME} src/main.cpp)
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
+endif()
 
+foreach(F IN LISTS TGC_SOURCES)
+    if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endif()
+endforeach()
+
+if(WITH_LLVM)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+endif()
+if(WITH_TCC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+endif()
+# Links the target exe against the libraries
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
+endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
+if (Tcmalloc_FOUND)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
+endif(Tcmalloc_FOUND)
+
+install(TARGETS tgc-sim
+  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
+  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+)
+###############################################################################
 #
-# CMAKE PACKAGING (for other CMake projects to use this one easily)
-# _____________________________________________________________________________
+###############################################################################
+if(TARGET scc-sysc)
+	project(dbt-rise-tgc_sc VERSION 1.0.0)
+    add_library(${PROJECT_NAME} 
+    	src/sysc/core_complex.cpp
+    	src/sysc/register_tgc_c.cpp
+    )
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    foreach(F IN LISTS TGC_SOURCES)
+        if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
+            string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        endif()
+    endforeach()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+    if(WITH_LLVM)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    endif()
+    
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
+    set_target_properties(${PROJECT_NAME} PROPERTIES
+      VERSION ${PROJECT_VERSION}
+      FRAMEWORK FALSE
+      PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+    )
+    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+	  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+	  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
+	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+	)    
+endif()
 
-#include(PackageConfigurator)

TGC_C_instr.yaml

@@ -0,0 +1,537 @@
+
+RV32I: 
+  - LUI:
+    encoding: 0b00000000000000000000000000110111
+    mask: 0b00000000000000000000000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - AUIPC:
+    encoding: 0b00000000000000000000000000010111
+    mask: 0b00000000000000000000000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - JAL:
+    encoding: 0b00000000000000000000000001101111
+    mask: 0b00000000000000000000000001111111
+    attributes: [[name:no_cont]]
+    size:   32
+    branch:   true
+    delay:   1
+  - JALR:
+    encoding: 0b00000000000000000000000001100111
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont]]
+    size:   32
+    branch:   true
+    delay:   1
+  - BEQ:
+    encoding: 0b00000000000000000000000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - BNE:
+    encoding: 0b00000000000000000001000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - BLT:
+    encoding: 0b00000000000000000100000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - BGE:
+    encoding: 0b00000000000000000101000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - BLTU:
+    encoding: 0b00000000000000000110000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - BGEU:
+    encoding: 0b00000000000000000111000001100011
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:no_cont], [name:cond]]
+    size:   32
+    branch:   true
+    delay:   [1,1]
+  - LB:
+    encoding: 0b00000000000000000000000000000011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - LH:
+    encoding: 0b00000000000000000001000000000011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - LW:
+    encoding: 0b00000000000000000010000000000011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - LBU:
+    encoding: 0b00000000000000000100000000000011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - LHU:
+    encoding: 0b00000000000000000101000000000011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SB:
+    encoding: 0b00000000000000000000000000100011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SH:
+    encoding: 0b00000000000000000001000000100011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SW:
+    encoding: 0b00000000000000000010000000100011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - ADDI:
+    encoding: 0b00000000000000000000000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
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+    encoding: 0b00000000000000000010000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SLTIU:
+    encoding: 0b00000000000000000011000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
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+    encoding: 0b00000000000000000100000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - ORI:
+    encoding: 0b00000000000000000110000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - ANDI:
+    encoding: 0b00000000000000000111000000010011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SLLI:
+    encoding: 0b00000000000000000001000000010011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SRLI:
+    encoding: 0b00000000000000000101000000010011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SRAI:
+    encoding: 0b01000000000000000101000000010011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - ADD:
+    encoding: 0b00000000000000000000000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SUB:
+    encoding: 0b01000000000000000000000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SLL:
+    encoding: 0b00000000000000000001000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SLT:
+    encoding: 0b00000000000000000010000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SLTU:
+    encoding: 0b00000000000000000011000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - XOR:
+    encoding: 0b00000000000000000100000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SRL:
+    encoding: 0b00000000000000000101000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - SRA:
+    encoding: 0b01000000000000000101000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - OR:
+    encoding: 0b00000000000000000110000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - AND:
+    encoding: 0b00000000000000000111000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - FENCE:
+    encoding: 0b00000000000000000000000000001111
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - ECALL:
+    encoding: 0b00000000000000000000000001110011
+    mask: 0b11111111111111111111111111111111
+    attributes: [[name:no_cont]]
+    size:   32
+    branch:   false
+    delay:   1
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+    encoding: 0b00000000000100000000000001110011
+    mask: 0b11111111111111111111111111111111
+    attributes: [[name:no_cont]]
+    size:   32
+    branch:   false
+    delay:   1
+  - MRET:
+    encoding: 0b00110000001000000000000001110011
+    mask: 0b11111111111111111111111111111111
+    attributes: [[name:no_cont]]
+    size:   32
+    branch:   false
+    delay:   1
+  - WFI:
+    encoding: 0b00010000010100000000000001110011
+    mask: 0b11111111111111111111111111111111
+    size:   32
+    branch:   false
+    delay:   1
+Zicsr: 
+  - CSRRW:
+    encoding: 0b00000000000000000001000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - CSRRS:
+    encoding: 0b00000000000000000010000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - CSRRC:
+    encoding: 0b00000000000000000011000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - CSRRWI:
+    encoding: 0b00000000000000000101000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - CSRRSI:
+    encoding: 0b00000000000000000110000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - CSRRCI:
+    encoding: 0b00000000000000000111000001110011
+    mask: 0b00000000000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+Zifencei: 
+  - FENCE_I:
+    encoding: 0b00000000000000000001000000001111
+    mask: 0b00000000000000000111000001111111
+    attributes: [[name:flush]]
+    size:   32
+    branch:   false
+    delay:   1
+RV32M: 
+  - MUL:
+    encoding: 0b00000010000000000000000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - MULH:
+    encoding: 0b00000010000000000001000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - MULHSU:
+    encoding: 0b00000010000000000010000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - MULHU:
+    encoding: 0b00000010000000000011000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - DIV:
+    encoding: 0b00000010000000000100000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - DIVU:
+    encoding: 0b00000010000000000101000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - REM:
+    encoding: 0b00000010000000000110000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+  - REMU:
+    encoding: 0b00000010000000000111000000110011
+    mask: 0b11111110000000000111000001111111
+    size:   32
+    branch:   false
+    delay:   1
+RV32IC: 
+  - CADDI4SPN:
+    encoding: 0b0000000000000000
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CLW:
+    encoding: 0b0100000000000000
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CSW:
+    encoding: 0b1100000000000000
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CADDI:
+    encoding: 0b0000000000000001
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CNOP:
+    encoding: 0b0000000000000001
+    mask: 0b1110111110000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CJAL:
+    encoding: 0b0010000000000001
+    mask: 0b1110000000000011
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   true
+    delay:   1
+  - CLI:
+    encoding: 0b0100000000000001
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CLUI:
+    encoding: 0b0110000000000001
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CADDI16SP:
+    encoding: 0b0110000100000001
+    mask: 0b1110111110000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CSRLI:
+    encoding: 0b1000000000000001
+    mask: 0b1111110000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CSRAI:
+    encoding: 0b1000010000000001
+    mask: 0b1111110000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CANDI:
+    encoding: 0b1000100000000001
+    mask: 0b1110110000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CSUB:
+    encoding: 0b1000110000000001
+    mask: 0b1111110001100011
+    size:   16
+    branch:   false
+    delay:   1
+  - CXOR:
+    encoding: 0b1000110000100001
+    mask: 0b1111110001100011
+    size:   16
+    branch:   false
+    delay:   1
+  - COR:
+    encoding: 0b1000110001000001
+    mask: 0b1111110001100011
+    size:   16
+    branch:   false
+    delay:   1
+  - CAND:
+    encoding: 0b1000110001100001
+    mask: 0b1111110001100011
+    size:   16
+    branch:   false
+    delay:   1
+  - CJ:
+    encoding: 0b1010000000000001
+    mask: 0b1110000000000011
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   true
+    delay:   1
+  - CBEQZ:
+    encoding: 0b1100000000000001
+    mask: 0b1110000000000011
+    attributes: [[name:no_cont], [name:cond]]
+    size:   16
+    branch:   true
+    delay:   [1,1]
+  - CBNEZ:
+    encoding: 0b1110000000000001
+    mask: 0b1110000000000011
+    attributes: [[name:no_cont], [name:cond]]
+    size:   16
+    branch:   true
+    delay:   [1,1]
+  - CSLLI:
+    encoding: 0b0000000000000010
+    mask: 0b1111000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CLWSP:
+    encoding: 0b0100000000000010
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CMV:
+    encoding: 0b1000000000000010
+    mask: 0b1111000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CJR:
+    encoding: 0b1000000000000010
+    mask: 0b1111000001111111
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   true
+    delay:   1
+  - CADD:
+    encoding: 0b1001000000000010
+    mask: 0b1111000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - CJALR:
+    encoding: 0b1001000000000010
+    mask: 0b1111000001111111
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   true
+    delay:   1
+  - CEBREAK:
+    encoding: 0b1001000000000010
+    mask: 0b1111111111111111
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   false
+    delay:   1
+  - CSWSP:
+    encoding: 0b1100000000000010
+    mask: 0b1110000000000011
+    size:   16
+    branch:   false
+    delay:   1
+  - DII:
+    encoding: 0b0000000000000000
+    mask: 0b1111111111111111
+    attributes: [[name:no_cont]]
+    size:   16
+    branch:   false
+    delay:   1
+

contrib/.gitignore

@@ -0,0 +1,3 @@
+/results
+/cwr
+/*.xml

contrib/README.md

@@ -0,0 +1,43 @@
+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```

contrib/build.tcl

@@ -0,0 +1,30 @@
+namespace eval Specification {
+    proc buildproc { args } {
+        global env
+        variable installDir
+        variable compiler
+        variable compiler [::scsh::get_backend_compiler]
+        #  set target $machine
+        set target [::scsh::machine]
+        set linkerOptions ""
+        set preprocessorOptions ""
+        set libversion $compiler
+        switch -exact -- $target {
+            "linux" {
+            	set install_dir $::env(TGFS_INSTALL_ROOT)
+                set incldir "${install_dir}/include"
+                set libdir "${install_dir}/lib64"
+                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
+                # Set the Linker paths.
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
+            }
+            default {
+               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
+               return
+            }
+        }
+        ::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
+        ::scsh::cwr_append_ipsimbld_opts linker       "$linkerOptions"
+    }
+    ::scsh::add_build_callback [namespace current]::buildproc
+}

contrib/tgc_import.cc

@@ -0,0 +1,4 @@
+
+#include "sysc/core_complex.h"
+
+void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }

contrib/tgc_import.tcl

@@ -0,0 +1,50 @@
+#############################################################################
+#
+#############################################################################
+proc getScriptDirectory {} {
+    set dispScriptFile [file normalize [info script]]
+    set scriptFolder [file dirname $dispScriptFile]
+    return $scriptFolder
+}
+    set hardware /HARDWARE/HW/HW
+
+set scriptDir [getScriptDirectory]
+set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
+set clocks clk_i
+set resets rst_i
+set model_prefix "i_"
+set model_postfix ""
+
+::pct::new_project
+::pct::open_library TLM2_PL
+::pct::clear_systemc_defines
+::pct::clear_systemc_include_path
+::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
+::pct::set_import_protocol_generation_flag false
+::pct::set_update_existing_encaps_flag true
+::pct::set_dynamic_port_arrays_flag true
+::pct::set_import_scml_properties_flag true
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
+
+# Set Port Protocols correctly
+set block ${top_design_name}
+foreach clock ${clocks} {
+	::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
+}
+foreach reset ${resets} {
+    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
+}
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+
+# Set compile settings and look
+set block SYSTEM_LIBRARY:${top_design_name}
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
+::pct::set_background_color_rgb $block 255 255 255 255
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
+
+# export the result as component
+::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/tgc_import_tb.tcl

@@ -0,0 +1,71 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
+::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
+::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
+::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
+::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
+::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml

gen_input/.gitignore

@@ -1 +1,2 @@
 /src-gen/
+/CoreDSL-Instruction-Set-Description

gen_input/TGC_C.core_desc

@@ -0,0 +1,13 @@
+import "ISA/RV32I.core_desc"
+import "ISA/RVM.core_desc"
+import "ISA/RVC.core_desc"
+
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned int MARCHID_VAL = 0x80000003;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,28 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGF_B provides RV32I {
-	constants {
-        XLEN:=32;
-        PCLEN:=32;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGF_C provides RV32I, RV32M, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000001000100000100;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}

gen_input/minres_rv.core_desc

@@ -1,74 +0,0 @@
-import "RV32I.core_desc"
-import "RV64I.core_desc"
-import "RVM.core_desc"
-import "RVA.core_desc"
-import "RVC.core_desc"
-import "RVF.core_desc"
-import "RVD.core_desc"
-
-
-Core MNRV32 provides RV32I, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
-    constants {
-        XLEN:=32;
-        FLEN:=64;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64I provides RV64I {
-    constants {
-        XLEN:=64;
-        PCLEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b10000000000001000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
-    constants {
-        XLEN:=64;
-        FLEN:=64;
-        PCLEN:=64;
-        MUL_LEN:=128;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-

gen_input/templates/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,41 +29,48 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
- 
+<% 
+def getRegisterSizes(){
+	def regs = registers.collect{it.size}
+	regs[-1]=64 // correct for NEXT_PC
+	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    return regs
+}
+%>
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgf_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_names;
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
-tgf_c::tgf_c() {
-    reg.icount = 0;
-}
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
-tgf_c::~tgf_c() = default;
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
-void tgf_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
     reg.trap_state=0;
-    reg.machine_state=0x3;
     reg.icount=0;
 }
 
-uint8_t *tgf_c::get_regs_base_ptr() {
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
     return phys_addr_t(pc); // change logical address to physical address
 }
 

gen_input/templates/CORENAME.h.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,47 +29,33 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+<%
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
+def getRegisterSizes(){
+    def regs = registers.collect{nativeTypeSize(it.size)}
+    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    return regs
+}
+def getRegisterOffsets(){
+    def offset = 0
+    def offsets = []
+    getRegisterSizes().each { size ->
+        offsets<<offset
+        offset+=size/8
     }
+    return offsets
 }
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
+def byteSize(int size){
+    if(size<=8) return 8;
+    if(size<=16) return 16;
+    if(size<=32) return 32;
+    if(size<=64) return 64;
+    return 128;
 }
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
+def getCString(def val){
+    return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
@@ -87,43 +73,23 @@ struct ${coreDef.name.toLowerCase()};
 
 template <> struct traits<${coreDef.name.toLowerCase()}> {
 
-	constexpr static char const* const core_type = "${coreDef.name}";
+    constexpr static char const* const core_type = "${coreDef.name}";
     
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
+    static constexpr std::array<const char*, ${registers.size}> reg_names{
+        {"${registers.collect{it.name}.join('", "')}"}};
  
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
+    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
+        {"${registers.collect{it.alias}.join('", "')}"}};
 
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
+    enum reg_e {
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     };
 
-    using reg_t = uint${regDataWidth}_t;
+    using reg_t = uint${addrDataWidth}_t;
 
     using addr_t = uint${addrDataWidth}_t;
 
@@ -133,17 +99,22 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+        {${getRegisterSizes().join(',')}}};
 
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+        {${getRegisterOffsets().join(',')}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
+        ${instr.instruction.name} = ${index},<%}%>
+        MAX_OPCODE
+    };
 };
 
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -159,14 +130,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
     inline uint64_t get_icount() { return reg.icount; }
 
@@ -188,33 +151,31 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
 
+#pragma pack(push, 1)
+    struct ${coreDef.name}_regs {<%
+        registers.each { reg -> if(reg.size>0) {%> 
+        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
+        }}%>
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;
 <%
-def fcsr = allRegs.find {it.name=='FCSR'}
+def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+    uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
+    void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}      
 <%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
 <%}%>
 };
 

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -0,0 +1,12 @@
+{
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  :   "${instr.name}",
+			"size"  :   ${instr.length},
+			"encoding": "${instr.encoding}",
+            "mask":     "${instr.mask}",
+			"branch":   ${instr.modifiesPC},
+			"delay" :   ${instr.isConditional?"[1,1]":"1"}
+		}<%}%>
+	]
+}

gen_input/templates/CORENAME_decoder.cpp.gtl

@@ -0,0 +1,86 @@
+#include "${coreDef.name.toLowerCase()}.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
+}};
+
+}
+
+template<>
+struct instruction_decoder<${coreDef.name.toLowerCase()}> {
+    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) < bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
+    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
+}
+
+}
+}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -0,0 +1,20 @@
+<% def getInstructionGroups() {
+    def instrGroups = [:]
+    instructions.each {
+        def groupName = it['instruction'].eContainer().name
+        if(!instrGroups.containsKey(groupName)) {
+            instrGroups[groupName]=[]
+        }
+        instrGroups[groupName]+=it;
+    }
+    instrGroups
+}%><%getInstructionGroups().each{name, instrList -> %>
+${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
+  - ${it.instruction.name}:
+    encoding: ${it.encoding}
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}%>
+    size:   ${it.length}
+    branch:   ${it.modifiesPC}
+    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
+

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -0,0 +1,343 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+<%
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+}
+%>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/interp/vm_base.h>
+#include <util/logging.h>
+#include <sstream>
+#include <boost/coroutine2/all.hpp>
+#include <functional>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace interp {
+namespace ${coreDef.name.toLowerCase()} {
+using namespace iss::arch;
+using namespace iss::debugger;
+using namespace std::placeholders;
+
+template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super       = typename iss::interp::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t      = typename super::addr_t;
+    using reg_t       = typename traits::reg_t;
+    using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
+    
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (super::tgt_adapter == nullptr)
+            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return super::tgt_adapter;
+    }
+
+protected:
+    using this_class = vm_impl<ARCH>;
+    using compile_ret_t = virt_addr_t;
+    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
+
+    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
+
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
+    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum {
+        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
+        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
+    };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    inline void raise(uint16_t trap_id, uint16_t cause){
+        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
+        this->core.reg.trap_state = trap_val;
+        this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
+    }
+
+    inline void leave(unsigned lvl){
+        this->core.leave_trap(lvl);
+    }
+
+    inline void wait(unsigned type){
+        this->core.wait_until(type);
+    }
+
+    using yield_t = boost::coroutines2::coroutine<void>::push_type;
+    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
+    std::vector<coro_t> spawn_blocks;
+
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }
+    
+    inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
+             if(*it){
+                 (*it)();
+                 ++it;
+             } else
+                 spawn_blocks.erase(it);
+    }
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
+    }};
+
+    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
+    iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
+        auto phys_pc = this->core.v2p(pc);
+        //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
+        //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
+        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
+        //} else {
+            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
+        //}
+        return iss::Ok;
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    unsigned id=0;
+    for (auto instr : instr_descr) {
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
+    }
+}
+
+inline bool is_count_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
+}
+
+inline bool is_jump_to_self_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
+}
+
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
+template <typename ARCH>
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
+    auto pc=start;
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto& trap_state = this->core.reg.trap_state;
+    auto& icount =  this->core.reg.icount;
+    auto& cycle =  this->core.reg.cycle;
+    auto& instret =  this->core.reg.instret;
+    auto& instr =  this->core.reg.instruction;
+    // we fetch at max 4 byte, alignment is 2
+    auto *const data = reinterpret_cast<uint8_t*>(&instr);
+
+    while(!this->core.should_stop() &&
+            !(is_count_limit_enabled(cond) && icount >= icount_limit)){
+        if(fetch_ins(pc, data)!=iss::Ok){
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+        } else {
+            if (is_jump_to_self_enabled(cond) &&
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto inst_id = decode_inst_id(instr);
+            // pre execution stuff
+             this->core.reg.last_branch = 0;
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
+            case arch::traits<ARCH>::opcode_e::${instr.name}: {
+                <%instr.fields.eachLine{%>${it}
+                <%}%>if(this->disass_enabled){
+                    /* generate console output when executing the command */<%instr.disass.eachLine{%>
+                    ${it}<%}%>
+                }
+                // used registers<%instr.usedVariables.each{ k,v->
+                if(v.isArray) {%>
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+                <%}}%>// calculate next pc value
+                *NEXT_PC = *PC + ${instr.length/8};
+                // execute instruction<%instr.behavior.eachLine{%>
+                ${it}<%}%>
+                TRAP_${instr.name}:break;
+            }// @suppress("No break at end of case")<%}%>
+            default: {
+                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                raise(0,  2);
+            }
+            }
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
+            // trap check
+            if(trap_state!=0){
+                super::core.enter_trap(trap_state, pc.val, instr);
+            } else {
+                icount++;
+                instret++;
+            }
+            cycle++;
+            pc.val=*NEXT_PC;
+            this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.reg.trap_state =  this->core.reg.pending_trap;
+        }
+    }
+    return pc;
+}
+
+}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace interp
+} // namespace iss
+
+#include <iss/factory.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+namespace iss {
+namespace {
+std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
+		return iss::dummy.data();
+	}
+}

gen_input/templates/interp/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/interp/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl

@@ -1,247 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2020 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include "../fp_functions.h"
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/interp/vm_base.h>
-#include <util/logging.h>
-#include <sstream>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace interp {
-namespace ${coreDef.name.toLowerCase()} {
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
-public:
-    using super = typename iss::interp::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-    using reg_t = typename traits<ARCH>::reg_t;
-    using iss::interp::vm_base<ARCH>::get_reg;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (super::tgt_adapter == nullptr)
-            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return super::tgt_adapter;
-    }
-
-protected:
-    using this_class = vm_impl<ARCH>;
-    using compile_ret_t = virt_addr_t;
-    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
-
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
-
-    virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
-
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    std::array<compile_func *, 4> qlut;
-
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
-
-    void raise_trap(uint16_t trap_id, uint16_t cause){
-        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
-    }
-
-    void leave_trap(unsigned lvl){
-        this->core.leave_trap(lvl);
-        auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
-        this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
-    }
-
-    void wait(unsigned type){
-        this->core.wait_until(type);
-    }
-
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
-        ${it}<%}%>
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        return pc;
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
-    auto pc=start;
-    while(pred){
-        auto paddr = this->core.v2p(pc);
-        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-            if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-            if ((insn & 0x3) == 0x3) // this is a 32bit instruction
-                if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        } else {
-            if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        }
-        if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-        auto lut_val = extract_fields(insn);
-        auto f = qlut[insn & 0x3][lut_val];
-        if (!f)
-            f = &this_class::illegal_intruction;
-        pc = (this->*f)(pc, insn);
-    }
-    return pc;
-}
-
-} // namespace mnrv32
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace interp
-} // namespace iss

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -30,10 +30,10 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -31,7 +31,6 @@
  *******************************************************************************/
 
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -55,10 +54,12 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
     using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
+    using mem_type_e  = typename traits::mem_type_e;    
     using addr_t      = typename super::addr_t;
     using tu_builder  = typename super::tu_builder;
 
@@ -82,7 +83,7 @@ protected:
     using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
     void setup_module(std::string m) override {
         super::setup_module(m);
@@ -104,10 +105,10 @@ protected:
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
         switch(reg_num){
-        case traits<ARCH>::NEXT_PC:
+        case traits::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
-        case traits<ARCH>::PC:
+        case traits::PC:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
@@ -123,7 +124,7 @@ protected:
     // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
     enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
     enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
 
     std::array<compile_func, LUT_SIZE> lut;
 
@@ -170,6 +171,12 @@ protected:
         }
         return lut_val;
     }
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }    
 
 private:
     /****************************************************************************
@@ -185,13 +192,28 @@ private:
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
  
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+        tu("${instr.name}_{:#010x}:", pc.val);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
+            ${it}<%}%>
+        }
+        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
+        pc=pc+ ${instr.length/8};
+        gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu.open_scope();<%instr.behavior.eachLine{%>
         ${it}<%}%>
+        tu.close_scope();
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);
+        return returnValue;
     }
     <%}%>
     /****************************************************************************
@@ -233,20 +255,20 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&insn;
     paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
         auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
+//    }
     if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
@@ -260,13 +282,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@@ -274,8 +296,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
     tu("return *next_pc;");
 }
 
@@ -287,5 +309,32 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-}
+} // namesapce tcc
 } // namespace iss
+
+#include <iss/factory.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+namespace iss {
+namespace {
+std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+extern "C" {
+	bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
+		return iss::dummy.data();
+	}
+}

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

incl/iss/arch/riscv_hart_m_p.h

@@ -1,944 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial implementation
- ******************************************************************************/
-
-#ifndef _RISCV_CORE_H_
-#define _RISCV_CORE_H_
-
-#include "iss/arch/traits.h"
-#include "iss/arch_if.h"
-#include "iss/instrumentation_if.h"
-#include "iss/log_categories.h"
-#include "iss/vm_if.h"
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <array>
-#include <elfio/elfio.hpp>
-#include <fmt/format.h>
-#include <iomanip>
-#include <sstream>
-#include <type_traits>
-#include <unordered_map>
-#include <util/bit_field.h>
-#include <util/ities.h>
-#include <util/sparse_array.h>
-
-#if defined(__GNUC__)
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#else
-#define likely(x) x
-#define unlikely(x) x
-#endif
-
-namespace iss {
-namespace arch {
-
-enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
-
-enum riscv_csr {
-    /* user-level CSR */
-    // User Trap Setup
-    ustatus = 0x000,
-    uie = 0x004,
-    utvec = 0x005,
-    // User Trap Handling
-    uscratch = 0x040,
-    uepc = 0x041,
-    ucause = 0x042,
-    utval = 0x043,
-    uip = 0x044,
-    // User Floating-Point CSRs
-    fflags = 0x001,
-    frm = 0x002,
-    fcsr = 0x003,
-    // User Counter/Timers
-    cycle = 0xC00,
-    time = 0xC01,
-    instret = 0xC02,
-    hpmcounter3 = 0xC03,
-    hpmcounter4 = 0xC04,
-    /*...*/
-    hpmcounter31 = 0xC1F,
-    cycleh = 0xC80,
-    timeh = 0xC81,
-    instreth = 0xC82,
-    hpmcounter3h = 0xC83,
-    hpmcounter4h = 0xC84,
-    /*...*/
-    hpmcounter31h = 0xC9F,
-    /* supervisor-level CSR */
-    // Supervisor Trap Setup
-    sstatus = 0x100,
-    sedeleg = 0x102,
-    sideleg = 0x103,
-    sie = 0x104,
-    stvec = 0x105,
-    scounteren = 0x106,
-    // Supervisor Trap Handling
-    sscratch = 0x140,
-    sepc = 0x141,
-    scause = 0x142,
-    stval = 0x143,
-    sip = 0x144,
-    // Supervisor Protection and Translation
-    satp = 0x180,
-    /* machine-level CSR */
-    // Machine Information Registers
-    mvendorid = 0xF11,
-    marchid = 0xF12,
-    mimpid = 0xF13,
-    mhartid = 0xF14,
-    // Machine Trap Setup
-    mstatus = 0x300,
-    misa = 0x301,
-    medeleg = 0x302,
-    mideleg = 0x303,
-    mie = 0x304,
-    mtvec = 0x305,
-    mcounteren = 0x306,
-    // Machine Trap Handling
-    mscratch = 0x340,
-    mepc = 0x341,
-    mcause = 0x342,
-    mtval = 0x343,
-    mip = 0x344,
-    // Machine Protection and Translation
-    pmpcfg0 = 0x3A0,
-    pmpcfg1 = 0x3A1,
-    pmpcfg2 = 0x3A2,
-    pmpcfg3 = 0x3A3,
-    pmpaddr0 = 0x3B0,
-    pmpaddr1 = 0x3B1,
-    /*...*/
-    pmpaddr15 = 0x3BF,
-    // Machine Counter/Timers
-    mcycle = 0xB00,
-    minstret = 0xB02,
-    mhpmcounter3 = 0xB03,
-    mhpmcounter4 = 0xB04,
-    /*...*/
-    mhpmcounter31 = 0xB1F,
-    mcycleh = 0xB80,
-    minstreth = 0xB82,
-    mhpmcounter3h = 0xB83,
-    mhpmcounter4h = 0xB84,
-    /*...*/
-    mhpmcounter31h = 0xB9F,
-    // Machine Counter Setup
-    mhpmevent3 = 0x323,
-    mhpmevent4 = 0x324,
-    /*...*/
-    mhpmevent31 = 0x33F,
-    // Debug/Trace Registers (shared with Debug Mode)
-    tselect = 0x7A0,
-    tdata1 = 0x7A1,
-    tdata2 = 0x7A2,
-    tdata3 = 0x7A3,
-    // Debug Mode Registers
-    dcsr = 0x7B0,
-    dpc = 0x7B1,
-    dscratch = 0x7B2
-};
-
-namespace {
-
-std::array<const char *, 16> trap_str = {{""
-                                          "Instruction address misaligned", // 0
-                                          "Instruction access fault",       // 1
-                                          "Illegal instruction",            // 2
-                                          "Breakpoint",                     // 3
-                                          "Load address misaligned",        // 4
-                                          "Load access fault",              // 5
-                                          "Store/AMO address misaligned",   // 6
-                                          "Store/AMO access fault",         // 7
-                                          "Environment call from U-mode",   // 8
-                                          "Environment call from S-mode",   // 9
-                                          "Reserved",                       // a
-                                          "Environment call from M-mode",   // b
-                                          "Instruction page fault",         // c
-                                          "Load page fault",                // d
-                                          "Reserved",                       // e
-                                          "Store/AMO page fault"}};
-std::array<const char *, 12> irq_str = {
-    {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-     "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-     "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
-enum {
-    PGSHIFT = 12,
-    PTE_PPN_SHIFT = 10,
-    // page table entry (PTE) fields
-    PTE_V = 0x001,   // Valid
-    PTE_R = 0x002,   // Read
-    PTE_W = 0x004,   // Write
-    PTE_X = 0x008,   // Execute
-    PTE_U = 0x010,   // User
-    PTE_G = 0x020,   // Global
-    PTE_A = 0x040,   // Accessed
-    PTE_D = 0x080,   // Dirty
-    PTE_SOFT = 0x300 // Reserved for Software
-};
-
-template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
-
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
-
-enum {
-    ISA_A = 1,
-    ISA_B = 1 << 1,
-    ISA_C = 1 << 2,
-    ISA_D = 1 << 3,
-    ISA_E = 1 << 4,
-    ISA_F = 1 << 5,
-    ISA_G = 1 << 6,
-    ISA_I = 1 << 8,
-    ISA_M = 1 << 12,
-    ISA_N = 1 << 13,
-    ISA_Q = 1 << 16,
-    ISA_S = 1 << 18,
-    ISA_U = 1 << 20
-};
-
-class trap_load_access_fault : public trap_access {
-public:
-    trap_load_access_fault(uint64_t badaddr)
-    : trap_access(5 << 16, badaddr) {}
-};
-class illegal_instruction_fault : public trap_access {
-public:
-    illegal_instruction_fault(uint64_t badaddr)
-    : trap_access(2 << 16, badaddr) {}
-};
-} // namespace
-
-template <typename BASE> class riscv_hart_m_p : public BASE {
-public:
-    using super = BASE;
-    using this_class = riscv_hart_m_p<BASE>;
-    using phys_addr_t = typename super::phys_addr_t;
-    using reg_t = typename super::reg_t;
-    using addr_t = typename super::addr_t;
-
-    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
-    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
-
-    // primary template
-    template <class T, class Enable = void> struct hart_state {};
-    // specialization 32bit
-    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
-    public:
-        BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        BF_FIELD(SD, 31, 1);
-        // Trap SRET
-        BF_FIELD(TSR, 22, 1);
-        // Timeout Wait
-        BF_FIELD(TW, 21, 1);
-        // Trap Virtual Memory
-        BF_FIELD(TVM, 20, 1);
-        // Make eXecutable Readable
-        BF_FIELD(MXR, 19, 1);
-        // permit Supervisor User Memory access
-        BF_FIELD(SUM, 18, 1);
-        // Modify PRiVilege
-        BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        BF_FIELD(XS, 15, 2);
-        // floating-point unit status Off/Initial/Clean/Dirty
-        BF_FIELD(FS, 13, 2);
-        // machine previous privilege
-        BF_FIELD(MPP, 11, 2);
-        // supervisor previous privilege
-        BF_FIELD(SPP, 8, 1);
-        // previous machine interrupt-enable
-        BF_FIELD(MPIE, 7, 1);
-        // previous supervisor interrupt-enable
-        BF_FIELD(SPIE, 5, 1);
-        // previous user interrupt-enable
-        BF_FIELD(UPIE, 4, 1);
-        // machine interrupt-enable
-        BF_FIELD(MIE, 3, 1);
-        // supervisor interrupt-enable
-        BF_FIELD(SIE, 1, 1);
-        // user interrupt-enable
-        BF_FIELD(UIE, 0, 1);
-        END_BF_DECL();
-
-        mstatus_t mstatus;
-
-        static const reg_t mstatus_reset_val = 0;
-
-        void write_mstatus(T val) {
-            auto mask = get_mask();
-            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
-            mstatus = new_val;
-        }
-
-        T satp;
-
-        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
-
-        static constexpr uint32_t get_mask() {
-            return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
-        }
-    };
-
-    constexpr reg_t get_irq_mask() {
-        return 0b101110111011; // only machine mode is supported
-    }
-
-    riscv_hart_m_p();
-    virtual ~riscv_hart_m_p() = default;
-
-    void reset(uint64_t address) override;
-
-    std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
-
-    iss::status read(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, uint8_t *const data) override;
-    iss::status write(const address_type type, const access_type access, const uint32_t space,
-            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
-
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
-
-    const reg_t& get_mhartid() const { return mhartid_reg;	}
-	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->reg.icount);
-    };
-
-    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
- 
-protected:
-    struct riscv_instrumentation_if : public iss::instrumentation_if {
-
-        riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
-        : arch(arch) {}
-        /**
-         * get the name of this architecture
-         *
-         * @return the name of this architecture
-         */
-        const std::string core_type_name() const override { return traits<BASE>::core_type; }
-
-        virtual uint64_t get_pc() { return arch.get_pc(); };
-
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
-
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
-
-        riscv_hart_m_p<BASE> &arch;
-    };
-
-    friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }
-
-    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
-    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
-
-    virtual iss::status read_csr(unsigned addr, reg_t &val);
-    virtual iss::status write_csr(unsigned addr, reg_t val);
-
-    hart_state<reg_t> state;
-    uint64_t cycle_offset;
-    reg_t fault_data;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
-    riscv_instrumentation_if instr_if;
-
-    using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
-    using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
-    using csr_page_type = typename csr_type::page_type;
-    mem_type mem;
-    csr_type csr;
-    std::stringstream uart_buf;
-    std::unordered_map<reg_t, uint64_t> ptw;
-    std::unordered_map<uint64_t, uint8_t> atomic_reservation;
-    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
-    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
-
-private:
-    iss::status read_cycle(unsigned addr, reg_t &val);
-    iss::status read_time(unsigned addr, reg_t &val);
-    iss::status read_status(unsigned addr, reg_t &val);
-    iss::status write_status(unsigned addr, reg_t val);
-    iss::status read_ie(unsigned addr, reg_t &val);
-    iss::status write_ie(unsigned addr, reg_t val);
-    iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ip(unsigned addr, reg_t val);
-    iss::status read_hartid(unsigned addr, reg_t &val);
-
-    reg_t mhartid_reg{0xF};
-
-protected:
-    void check_interrupt();
-};
-
-template <typename BASE>
-riscv_hart_m_p<BASE>::riscv_hart_m_p()
-: state()
-, cycle_offset(0)
-, instr_if(*this) {
-    csr[misa] = hart_state<reg_t>::get_misa();
-    uart_buf.str("");
-    // read-only registers
-    csr_wr_cb[misa] = nullptr;
-    for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
-    for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
-    // special handling
-    csr_rd_cb[time] = &riscv_hart_m_p<BASE>::read_time;
-    csr_wr_cb[time] = nullptr;
-    csr_rd_cb[timeh] = &riscv_hart_m_p<BASE>::read_time;
-    csr_wr_cb[timeh] = nullptr;
-    csr_rd_cb[mcycle] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[mcycleh] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[minstret] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[minstreth] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[mstatus] = &riscv_hart_m_p<BASE>::read_status;
-    csr_wr_cb[mstatus] = &riscv_hart_m_p<BASE>::write_status;
-    csr_rd_cb[mip] = &riscv_hart_m_p<BASE>::read_ip;
-    csr_wr_cb[mip] = &riscv_hart_m_p<BASE>::write_ip;
-    csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
-    csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
-    csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
-}
-
-template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
-    FILE *fp = fopen(name.c_str(), "r");
-    if (fp) {
-        std::array<char, 5> buf;
-        auto n = fread(buf.data(), 1, 4, fp);
-        if (n != 4) throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if (!reader.load(name)) throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if (reader.get_class() != ELFCLASS32)
-                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
-            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
-            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
-            for (const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                if (fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
-                            traits<BASE>::MEM, pseg->get_physical_address(),
-                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
-                    if (res != iss::Ok)
-                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
-                                   << pseg->get_physical_address();
-                }
-            }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-            }
-
-            return std::make_pair(reader.get_entry(), true);
-        }
-        throw std::runtime_error("memory load file is not a valid elf file");
-    }
-    throw std::runtime_error("memory load file not found");
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, uint8_t *const data) {
-#ifndef NDEBUG
-    if (access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
-    } else if(access && iss::access_type::FETCH){
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
-    } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
-   }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto res = type==iss::address_type::PHYSICAL?
-                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                return iss::Err;
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            return iss::Ok;
-        } break;
-        case traits<BASE>::RES: {
-            auto it = atomic_reservation.find(addr);
-            if (it != atomic_reservation.end() && it->second != 0) {
-                memset(data, 0xff, length);
-                atomic_reservation.erase(addr);
-            } else
-                memset(data, 0, length);
-        } break;
-        default:
-            return iss::Err; // assert("Not supported");
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        return iss::Err;
-    }
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
-        const uint64_t addr, const unsigned length, const uint8_t *const data) {
-#ifndef NDEBUG
-    const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
-    switch (length) {
-    case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
-                   << ") @addr 0x" << std::hex << addr;
-        break;
-    default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
-    }
-#endif
-    try {
-        switch (space) {
-        case traits<BASE>::MEM: {
-            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
-                fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto res = type==iss::address_type::PHYSICAL?
-                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok))
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
-                return res;
-            } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
-                return iss::Err;
-            }
-
-            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
-            if ((paddr.val + length) > mem.size()) return iss::Err;
-            switch (paddr.val) {
-            case 0x10013000: // UART0 base, TXFIFO reg
-            case 0x10023000: // UART1 base, TXFIFO reg
-                uart_buf << (char)data[0];
-                if (((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-                    // '"<<uart_buf.str()<<"'";
-                    std::cout << uart_buf.str();
-                    uart_buf.str("");
-                }
-                return iss::Ok;
-            case 0x10008000: { // HFROSC base, hfrosccfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-                return iss::Ok;
-            }
-            case 0x10008008: { // HFROSC base, pllcfg reg
-                auto &p = mem(paddr.val / mem.page_size);
-                auto offs = paddr.val & mem.page_addr_mask;
-                std::copy(data, data + length, p.data() + offs);
-                auto &x = *(p.data() + offs + 3);
-                x |= 0x80; // set pll lock upon writing
-                return iss::Ok;
-            } break;
-            default: {}
-            }
-        } break;
-        case traits<BASE>::CSR: {
-            if (length != sizeof(reg_t)) return iss::Err;
-            return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
-        } break;
-        case traits<BASE>::FENCE: {
-            if ((addr + length) > mem.size()) return iss::Err;
-            switch (addr) {
-            case 2:
-            case 3: {
-                ptw.clear();
-                auto tvm = state.mstatus.TVM;
-                return iss::Ok;
-            }
-            }
-        } break;
-        case traits<BASE>::RES: {
-            atomic_reservation[addr] = data[0];
-        } break;
-        default:
-            return iss::Err;
-        }
-        return iss::Ok;
-    } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
-        return iss::Err;
-    }
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_rd_cb.find(addr);
-    if (it == csr_rd_cb.end()) {
-        val = csr[addr & csr.page_addr_mask];
-        return iss::Ok;
-    }
-    rd_csr_f f = it->second;
-    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
-    return (this->*f)(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
-    if (addr >= csr.size()) return iss::Err;
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.machine_state < req_priv_lvl)
-        throw illegal_instruction_fault(this->fault_data);
-    if((addr&0xc00)==0xc00)
-        throw illegal_instruction_fault(this->fault_data);
-    auto it = csr_wr_cb.find(addr);
-    if (it == csr_wr_cb.end()) {
-        csr[addr & csr.page_addr_mask] = val;
-        return iss::Ok;
-    }
-    wr_csr_f f = it->second;
-    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
-    return (this->*f)(addr, val);
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
-    if (addr == mcycle) {
-        val = static_cast<reg_t>(cycle_val);
-    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(cycle_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
-    if (addr == time) {
-        val = static_cast<reg_t>(time_val);
-    } else if (addr == timeh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(time_val >> 32);
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
-    val = state.mstatus & hart_state<reg_t>::get_mask();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
-    state.write_mstatus(val);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
-    val = csr[mie];
-    val &= csr[mideleg];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
-    val = mhartid_reg;
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    csr[mie] = (csr[mie] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
-    val = csr[mip];
-    val &= csr[mideleg];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
-    auto mask = get_irq_mask();
-    mask &= ~(1 << 7); // MTIP is read only
-    csr[mip] = (csr[mip] & ~mask) | (val & mask);
-    check_interrupt();
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
-    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->reg.icount > 30000) data[3] |= 0x80;
-    } break;
-    default: {
-        const auto &p = mem(paddr.val / mem.page_size);
-        auto offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
-    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
-        if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
-            uart_buf.str("");
-        }
-        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
-    default: {
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-        // tohost handling in case of riscv-test
-        if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4));
-            auto tohost_lower =
-                (traits<BASE>::XLEN == 32 && paddr.val == tohost);
-            if (tohost_lower || tohost_upper) {
-                uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
-                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
-                    switch (hostvar >> 48) {
-                    case 0:
-                        if (hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
-                        } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
-                        }
-                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
-                        this->interrupt_sim=hostvar;
-                        break;
-                        //throw(iss::simulation_stopped(hostvar));
-                    case 0x0101: {
-                        char c = static_cast<char>(hostvar & 0xff);
-                        if (c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
-                            uart_buf.str("");
-                        } else
-                            uart_buf << c;
-                        to_host_wr_cnt = 0;
-                    } break;
-                    default:
-                        break;
-                    }
-                } else if (tohost_lower)
-                    to_host_wr_cnt++;
-            } else if (traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) {
-                uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
-                *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-            }
-        }
-    }
-    }
-    return iss::Ok;
-}
-
-template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
-    BASE::reset(address);
-    state.mstatus = hart_state<reg_t>::mstatus_reset_val;
-}
-
-template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
-    auto ideleg = csr[mideleg];
-    // Multiple simultaneous interrupts and traps at the same privilege level are
-    // handled in the following decreasing priority order:
-    // external interrupts, software interrupts, timer interrupts, then finally
-    // any synchronous traps.
-    auto ena_irq = csr[mip] & csr[mie];
-
-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
-    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
-
-    if (enabled_interrupts != 0) {
-        int res = 0;
-        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
-    }
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
-    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
-    // calculate and write mcause val
-    auto trap_id = bit_sub<0, 16>(flags);
-    auto cause = bit_sub<16, 15>(flags);
-    if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
-    // calculate effective privilege level
-    if (trap_id == 0) { // exception
-        // store ret addr in xepc register
-        csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
-        csr[mtval] = fault_data;
-        fault_data = 0;
-    } else {
-        csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
-        this->reg.pending_trap = 0;
-    }
-    csr[mcause] = (trap_id << 31) + cause;
-    // update mstatus
-    // xPP field of mstatus is written with the active privilege mode at the time
-    // of the trap; the x PIE field of mstatus
-    // is written with the value of the active interrupt-enable bit at the time of
-    // the trap; and the x IE field of mstatus
-    // is cleared
-    // store the actual privilege level in yPP and store interrupt enable flags
-    state.mstatus.MPP = PRIV_M;
-    state.mstatus.MPIE = state.mstatus.MIE;
-    state.mstatus.MIE = false;
-
-    // get trap vector
-    auto ivec = csr[mtvec];
-    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
-    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x1UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.machine_state = PRIV_M;
-    this->reg.trap_state = 0;
-    std::array<char, 32> buffer;
-    sprintf(buffer.data(), "0x%016lx", addr);
-    if((flags&0xffffffff) != 0xffffffff)
-    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
-                       << " at address " << buffer.data() << " occurred";
-    return this->reg.NEXT_PC;
-}
-
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    auto cur_priv = this->reg.machine_state;
-    auto inst_priv = flags & 0x3;
-    auto status = state.mstatus;
-
-    // pop the relevant lower-privilege interrupt enable and privilege mode stack
-    // clear respective yIE
-    if (inst_priv == PRIV_M) {
-        this->reg.machine_state = state.mstatus.MPP;
-        state.mstatus.MPP = 0; // clear mpp to U mode
-        state.mstatus.MIE = state.mstatus.MPIE;
-    } else {
-    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
-    }
-
-    // sets the pc to the value stored in the x epc register.
-    this->reg.NEXT_PC = csr[mepc];
-    CLOG(INFO, disass) << "Executing xRET";
-    return this->reg.NEXT_PC;
-}
-
-} // namespace arch
-} // namespace iss
-
-#endif /* _RISCV_CORE_H_ */

incl/iss/arch/tgf_b.h

@@ -1,252 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-
-#ifndef _TGF_B_H_
-#define _TGF_B_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgf_b;
-
-template <> struct traits<tgf_b> {
-
-	constexpr static char const* const core_type = "TGF_B";
-    
-  	static constexpr std::array<const char*, 33> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
- 
-  	static constexpr std::array<const char*, 33> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
-
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-        X29,
-        X30,
-        X31,
-        PC,
-        NUM_REGS,
-        NEXT_PC=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT,
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-};
-
-struct tgf_b: public arch_if {
-
-    using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
-    using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
-    using reg_t =  typename traits<tgf_b>::reg_t;
-    using addr_t = typename traits<tgf_b>::addr_t;
-
-    tgf_b();
-    ~tgf_b();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct TGF_B_regs {
-        uint32_t X0 = 0;
-        uint32_t X1 = 0;
-        uint32_t X2 = 0;
-        uint32_t X3 = 0;
-        uint32_t X4 = 0;
-        uint32_t X5 = 0;
-        uint32_t X6 = 0;
-        uint32_t X7 = 0;
-        uint32_t X8 = 0;
-        uint32_t X9 = 0;
-        uint32_t X10 = 0;
-        uint32_t X11 = 0;
-        uint32_t X12 = 0;
-        uint32_t X13 = 0;
-        uint32_t X14 = 0;
-        uint32_t X15 = 0;
-        uint32_t X16 = 0;
-        uint32_t X17 = 0;
-        uint32_t X18 = 0;
-        uint32_t X19 = 0;
-        uint32_t X20 = 0;
-        uint32_t X21 = 0;
-        uint32_t X22 = 0;
-        uint32_t X23 = 0;
-        uint32_t X24 = 0;
-        uint32_t X25 = 0;
-        uint32_t X26 = 0;
-        uint32_t X27 = 0;
-        uint32_t X28 = 0;
-        uint32_t X29 = 0;
-        uint32_t X30 = 0;
-        uint32_t X31 = 0;
-        uint32_t PC = 0;
-        uint32_t NEXT_PC = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGF_B_H_ */

incl/iss/arch/tgf_c.h

@@ -1,252 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-
-#ifndef _TGF_C_H_
-#define _TGF_C_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgf_c;
-
-template <> struct traits<tgf_c> {
-
-	constexpr static char const* const core_type = "TGF_C";
-    
-  	static constexpr std::array<const char*, 33> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
- 
-  	static constexpr std::array<const char*, 33> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
-
-    enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-        X29,
-        X30,
-        X31,
-        PC,
-        NUM_REGS,
-        NEXT_PC=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT,
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-};
-
-struct tgf_c: public arch_if {
-
-    using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
-    using reg_t =  typename traits<tgf_c>::reg_t;
-    using addr_t = typename traits<tgf_c>::addr_t;
-
-    tgf_c();
-    ~tgf_c();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct TGF_C_regs {
-        uint32_t X0 = 0;
-        uint32_t X1 = 0;
-        uint32_t X2 = 0;
-        uint32_t X3 = 0;
-        uint32_t X4 = 0;
-        uint32_t X5 = 0;
-        uint32_t X6 = 0;
-        uint32_t X7 = 0;
-        uint32_t X8 = 0;
-        uint32_t X9 = 0;
-        uint32_t X10 = 0;
-        uint32_t X11 = 0;
-        uint32_t X12 = 0;
-        uint32_t X13 = 0;
-        uint32_t X14 = 0;
-        uint32_t X15 = 0;
-        uint32_t X16 = 0;
-        uint32_t X17 = 0;
-        uint32_t X18 = 0;
-        uint32_t X19 = 0;
-        uint32_t X20 = 0;
-        uint32_t X21 = 0;
-        uint32_t X22 = 0;
-        uint32_t X23 = 0;
-        uint32_t X24 = 0;
-        uint32_t X25 = 0;
-        uint32_t X26 = 0;
-        uint32_t X27 = 0;
-        uint32_t X28 = 0;
-        uint32_t X29 = 0;
-        uint32_t X30 = 0;
-        uint32_t X31 = 0;
-        uint32_t PC = 0;
-        uint32_t NEXT_PC = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGF_C_H_ */

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-include(Common)
+#include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -49,7 +49,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
+#ifdef __GNUC__
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
+#endif
 #include "opts-GCC.h"
 

src-gen/.gitignore

@@ -0,0 +1,2 @@
+/iss
+/vm

src/iss/.gitignore

@@ -0,0 +1 @@
+/tgc_*.cpp

src/iss/arch/hwl.h

@@ -0,0 +1,100 @@
+/*******************************************************************************
+ * Copyright (C) 2022 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_HWL_H
+#define _RISCV_HART_M_P_HWL_H
+
+#include <iss/vm_types.h>
+
+namespace iss {
+namespace arch {
+
+template <typename BASE> class hwl : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = hwl<BASE>;
+    using reg_t = typename BASE::reg_t;
+
+    hwl();
+    virtual ~hwl() = default;
+
+protected:
+    iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
+    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
+};
+
+
+template<typename BASE>
+inline hwl<BASE>::hwl() {
+    for (unsigned addr = 0x800; addr < 0x803; ++addr){
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+    for (unsigned addr = 0x804; addr < 0x807; ++addr){
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+}
+
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
+    switch(addr){
+    case 0x800: val = this->reg.lpstart0; break;
+    case 0x801: val = this->reg.lpend0;   break;
+    case 0x802: val = this->reg.lpcount0; break;
+    case 0x804: val = this->reg.lpstart1; break;
+    case 0x805: val = this->reg.lpend1;   break;
+    case 0x806: val = this->reg.lpcount1; break;
+    }
+    return iss::Ok;
+}
+
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+    switch(addr){
+    case 0x800: this->reg.lpstart0 = val; break;
+    case 0x801: this->reg.lpend0   = val; break;
+    case 0x802: this->reg.lpcount0 = val; break;
+    case 0x804: this->reg.lpstart1 = val; break;
+    case 0x805: this->reg.lpend1   = val; break;
+    case 0x806: this->reg.lpcount1 = val; break;
+    }
+    return iss::Ok;
+}
+
+} // namespace arch
+} // namespace iss
+
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -0,0 +1,302 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_COMMON
+#define _RISCV_HART_COMMON
+
+#include "iss/arch_if.h"
+#include <cstdint>
+
+namespace iss {
+namespace arch {
+
+enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
+
+enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
+
+enum riscv_csr {
+    /* user-level CSR */
+    // User Trap Setup
+    ustatus = 0x000,
+    uie = 0x004,
+    utvec = 0x005,
+    utvt = 0x007, //CLIC
+    // User Trap Handling
+    uscratch = 0x040,
+    uepc = 0x041,
+    ucause = 0x042,
+    utval = 0x043,
+    uip = 0x044,
+    uxnti = 0x045, //CLIC
+    uintstatus   = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh   = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw  = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
+    // User Floating-Point CSRs
+    fflags = 0x001,
+    frm = 0x002,
+    fcsr = 0x003,
+    // User Counter/Timers
+    cycle = 0xC00,
+    time = 0xC01,
+    instret = 0xC02,
+    hpmcounter3 = 0xC03,
+    hpmcounter4 = 0xC04,
+    /*...*/
+    hpmcounter31 = 0xC1F,
+    cycleh = 0xC80,
+    timeh = 0xC81,
+    instreth = 0xC82,
+    hpmcounter3h = 0xC83,
+    hpmcounter4h = 0xC84,
+    /*...*/
+    hpmcounter31h = 0xC9F,
+    /* supervisor-level CSR */
+    // Supervisor Trap Setup
+    sstatus = 0x100,
+    sedeleg = 0x102,
+    sideleg = 0x103,
+    sie = 0x104,
+    stvec = 0x105,
+    scounteren = 0x106,
+    // Supervisor Trap Handling
+    sscratch = 0x140,
+    sepc = 0x141,
+    scause = 0x142,
+    stval = 0x143,
+    sip = 0x144,
+    // Supervisor Protection and Translation
+    satp = 0x180,
+    /* machine-level CSR */
+    // Machine Information Registers
+    mvendorid = 0xF11,
+    marchid = 0xF12,
+    mimpid = 0xF13,
+    mhartid = 0xF14,
+    // Machine Trap Setup
+    mstatus = 0x300,
+    misa = 0x301,
+    medeleg = 0x302,
+    mideleg = 0x303,
+    mie = 0x304,
+    mtvec = 0x305,
+    mcounteren = 0x306,
+    mtvt = 0x307, //CLIC
+    // Machine Trap Handling
+    mscratch = 0x340,
+    mepc = 0x341,
+    mcause = 0x342,
+    mtval = 0x343,
+    mip = 0x344,
+    mxnti = 0x345, //CLIC
+    mintstatus   = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh   = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
+    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    // Physical Memory Protection
+    pmpcfg0 = 0x3A0,
+    pmpcfg1 = 0x3A1,
+    pmpcfg2 = 0x3A2,
+    pmpcfg3 = 0x3A3,
+    pmpaddr0 = 0x3B0,
+    pmpaddr1 = 0x3B1,
+    pmpaddr2 = 0x3B2,
+    pmpaddr3 = 0x3B3,
+    pmpaddr4 = 0x3B4,
+    pmpaddr5 = 0x3B5,
+    pmpaddr6 = 0x3B6,
+    pmpaddr7 = 0x3B7,
+    pmpaddr8 = 0x3B8,
+    pmpaddr9 = 0x3B9,
+    pmpaddr10 = 0x3BA,
+    pmpaddr11 = 0x3BB,
+    pmpaddr12 = 0x3BC,
+    pmpaddr13 = 0x3BD,
+    pmpaddr14 = 0x3BE,
+    pmpaddr15 = 0x3BF,
+    // Machine Counter/Timers
+    mcycle = 0xB00,
+    minstret = 0xB02,
+    mhpmcounter3 = 0xB03,
+    mhpmcounter4 = 0xB04,
+    /*...*/
+    mhpmcounter31 = 0xB1F,
+    mcycleh = 0xB80,
+    minstreth = 0xB82,
+    mhpmcounter3h = 0xB83,
+    mhpmcounter4h = 0xB84,
+    /*...*/
+    mhpmcounter31h = 0xB9F,
+    // Machine Counter Setup
+    mhpmevent3 = 0x323,
+    mhpmevent4 = 0x324,
+    /*...*/
+    mhpmevent31 = 0x33F,
+    // Debug/Trace Registers (shared with Debug Mode)
+    tselect = 0x7A0,
+    tdata1 = 0x7A1,
+    tdata2 = 0x7A2,
+    tdata3 = 0x7A3,
+    // Debug Mode Registers
+    dcsr = 0x7B0,
+    dpc = 0x7B1,
+    dscratch0 = 0x7B2,
+    dscratch1 = 0x7B3
+};
+
+
+enum {
+    PGSHIFT = 12,
+    PTE_PPN_SHIFT = 10,
+    // page table entry (PTE) fields
+    PTE_V = 0x001,   // Valid
+    PTE_R = 0x002,   // Read
+    PTE_W = 0x004,   // Write
+    PTE_X = 0x008,   // Execute
+    PTE_U = 0x010,   // User
+    PTE_G = 0x020,   // Global
+    PTE_A = 0x040,   // Accessed
+    PTE_D = 0x080,   // Dirty
+    PTE_SOFT = 0x300 // Reserved for Software
+};
+
+template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
+
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
+
+enum {
+    ISA_A = 1,
+    ISA_B = 1 << 1,
+    ISA_C = 1 << 2,
+    ISA_D = 1 << 3,
+    ISA_E = 1 << 4,
+    ISA_F = 1 << 5,
+    ISA_G = 1 << 6,
+    ISA_I = 1 << 8,
+    ISA_M = 1 << 12,
+    ISA_N = 1 << 13,
+    ISA_Q = 1 << 16,
+    ISA_S = 1 << 18,
+    ISA_U = 1 << 20
+};
+
+struct vm_info {
+    int levels;
+    int idxbits;
+    int ptesize;
+    uint64_t ptbase;
+    bool is_active() { return levels; }
+};
+
+struct feature_config {
+    uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
+    unsigned clic_num_irq{16};
+    unsigned clic_num_trigger{0};
+    uint64_t tcm_base{0x10000000};
+    uint64_t tcm_size{0x8000};
+};
+
+class trap_load_access_fault : public trap_access {
+public:
+    trap_load_access_fault(uint64_t badaddr)
+    : trap_access(5 << 16, badaddr) {}
+};
+class illegal_instruction_fault : public trap_access {
+public:
+    illegal_instruction_fault(uint64_t badaddr)
+    : trap_access(2 << 16, badaddr) {}
+};
+class trap_instruction_page_fault : public trap_access {
+public:
+    trap_instruction_page_fault(uint64_t badaddr)
+    : trap_access(12 << 16, badaddr) {}
+};
+class trap_load_page_fault : public trap_access {
+public:
+    trap_load_page_fault(uint64_t badaddr)
+    : trap_access(13 << 16, badaddr) {}
+};
+class trap_store_page_fault : public trap_access {
+public:
+    trap_store_page_fault(uint64_t badaddr)
+    : trap_access(15 << 16, badaddr) {}
+};
+
+inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 1 + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 2 + i);
+    break;
+    case 3:
+        *data = *(reg_ptr + 3);
+    break;
+    }
+}
+
+inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + i) = *(data + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 1 + i) = *(data + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 2 + i) = *(data + i);
+    break;
+    case 3:
+        *(reg_ptr + 3) = *data ;
+    break;
+    }
+}
+
+}
+}
+
+#endif

src/iss/arch/tgc_c.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,41 +29,41 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
- 
+
+#include "tgc_c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgf_b.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_names;
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
-tgf_b::tgf_b() {
-    reg.icount = 0;
-}
+tgc_c::tgc_c()  = default;
 
-tgf_b::~tgf_b() = default;
+tgc_c::~tgc_c() = default;
 
-void tgf_b::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgf_b>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_b>::reg_t),0));
+void tgc_c::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
     reg.trap_state=0;
-    reg.machine_state=0x3;
     reg.icount=0;
 }
 
-uint8_t *tgf_b::get_regs_base_ptr() {
+uint8_t *tgc_c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgf_b::phys_addr_t tgf_b::virt2phys(const iss::addr_t &pc) {
+tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
     return phys_addr_t(pc); // change logical address to physical address
 }
 

src/iss/arch/tgc_c.h

@@ -0,0 +1,270 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _TGC_C_H_
+#define _TGC_C_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgc_c;
+
+template <> struct traits<tgc_c> {
+
+    constexpr static char const* const core_type = "TGC_C";
+    
+    static constexpr std::array<const char*, 36> reg_names{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
+ 
+    static constexpr std::array<const char*, 36> reg_aliases{
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
+
+    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
+
+    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, FENCE, RES, CSR };
+    
+    enum class opcode_e {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        ECALL = 38,
+        EBREAK = 39,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MUL = 49,
+        MULH = 50,
+        MULHSU = 51,
+        MULHU = 52,
+        DIV = 53,
+        DIVU = 54,
+        REM = 55,
+        REMU = 56,
+        CADDI4SPN = 57,
+        CLW = 58,
+        CSW = 59,
+        CADDI = 60,
+        CNOP = 61,
+        CJAL = 62,
+        CLI = 63,
+        CLUI = 64,
+        CADDI16SP = 65,
+        __reserved_clui = 66,
+        CSRLI = 67,
+        CSRAI = 68,
+        CANDI = 69,
+        CSUB = 70,
+        CXOR = 71,
+        COR = 72,
+        CAND = 73,
+        CJ = 74,
+        CBEQZ = 75,
+        CBNEZ = 76,
+        CSLLI = 77,
+        CLWSP = 78,
+        CMV = 79,
+        CJR = 80,
+        __reserved_cmv = 81,
+        CADD = 82,
+        CJALR = 83,
+        CEBREAK = 84,
+        CSWSP = 85,
+        DII = 86,
+        MAX_OPCODE
+    };
+};
+
+struct tgc_c: public arch_if {
+
+    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
+    using reg_t =  typename traits<tgc_c>::reg_t;
+    using addr_t = typename traits<tgc_c>::addr_t;
+
+    tgc_c();
+    ~tgc_c();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+
+#pragma pack(push, 1)
+    struct TGC_C_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t X16 = 0; 
+        uint32_t X17 = 0; 
+        uint32_t X18 = 0; 
+        uint32_t X19 = 0; 
+        uint32_t X20 = 0; 
+        uint32_t X21 = 0; 
+        uint32_t X22 = 0; 
+        uint32_t X23 = 0; 
+        uint32_t X24 = 0; 
+        uint32_t X25 = 0; 
+        uint32_t X26 = 0; 
+        uint32_t X27 = 0; 
+        uint32_t X28 = 0; 
+        uint32_t X29 = 0; 
+        uint32_t X30 = 0; 
+        uint32_t X31 = 0; 
+        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0; 
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGC_C_H_ */

src/iss/arch/tgc_c_decoder.cpp

@@ -0,0 +1,175 @@
+#include "tgc_c.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<tgc_c>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, 90> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */
+    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
+    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
+    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
+    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
+    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
+    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
+    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
+    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
+    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
+    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
+    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
+    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
+    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
+    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
+    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
+    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
+    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
+    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
+    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
+    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
+    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
+    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
+    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
+    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
+    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
+    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
+    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
+    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
+    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
+    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
+    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
+    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
+    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
+    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
+    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
+    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
+    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
+    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
+    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
+    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
+    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
+    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
+    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
+    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
+    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
+    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
+    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
+    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
+    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
+    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
+    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
+    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
+    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
+    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
+    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
+    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
+    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
+    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
+    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
+    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
+    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
+    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
+    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
+    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
+    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
+    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
+    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
+    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
+    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
+    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
+    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
+    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
+    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
+    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
+    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
+    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
+    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
+    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
+    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
+    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
+    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
+    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
+    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
+    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
+    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
+    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
+    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
+    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
+    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
+    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
+}};
+
+}
+
+template<>
+struct instruction_decoder<tgc_c> {
+    using opcode_e = traits<tgc_c>::opcode_e;
+    using code_word_t=traits<tgc_c>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) > bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
+    return std::make_unique<instruction_decoder<tgc_c>>();
+}
+
+}
+}

src/iss/arch/tgc_mapper.h

@@ -0,0 +1,50 @@
+#ifndef _ISS_ARCH_TGC_MAPPER_H
+#define _ISS_ARCH_TGC_MAPPER_H
+
+#include "riscv_hart_m_p.h"
+#include "tgc_c.h"
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_A
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_a.h>
+using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
+#endif
+#ifdef CORE_TGC_B
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_b.h>
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#endif
+#ifdef CORE_TGC_C_XRB_NN
+#include "riscv_hart_m_p.h"
+#include "hwl.h"
+#include <iss/arch/tgc_c_xrb_nn.h>
+using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
+#endif
+#ifdef CORE_TGC_D
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_d.h>
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_d_xrb_mac.h>
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+#include "riscv_hart_mu_p.h"
+#include "hwl.h"
+#include <iss/arch/tgc_d_xrb_nn.h>
+using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
+#endif
+#ifdef CORE_TGC_E
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_e.h>
+using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_X
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc_x.h>
+using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+#endif
+
+#endif

src/iss/arch/wt_cache.h

@@ -0,0 +1,172 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_WT_CACHE_H
+#define _RISCV_HART_M_P_WT_CACHE_H
+
+#include <iss/vm_types.h>
+#include <util/ities.h>
+#include <vector>
+#include <map>
+#include <memory>
+
+namespace iss {
+namespace arch {
+namespace cache {
+
+enum class state { INVALID, VALID};
+struct line {
+    uint64_t tag_addr{0};
+    state st{state::INVALID};
+    std::vector<uint8_t> data;
+    line(unsigned line_sz):  data(line_sz) {}
+};
+struct set {
+    std::vector<line> ways;
+    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
+};
+struct cache {
+    std::vector<set> sets;
+
+    cache(unsigned size, unsigned line_sz, unsigned ways) {
+        line const ref_line{line_sz};
+        set const ref_set{ways, ref_line};
+        sets.resize(size/(ways*line_sz), ref_set);
+    }
+};
+
+struct wt_policy {
+    bool is_cacheline_hit(cache& c );
+};
+}
+
+// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
+template <typename BASE> class wt_cache : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = wt_cache<BASE>;
+    using reg_t = typename BASE::reg_t;
+    using mem_read_f = typename BASE::mem_read_f;
+    using mem_write_f = typename BASE::mem_write_f;
+    using phys_addr_t = typename BASE::phys_addr_t;
+
+    wt_cache();
+    virtual ~wt_cache() = default;
+
+    unsigned size{4096};
+    unsigned line_sz{32};
+    unsigned ways{1};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+protected:
+    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
+    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
+    std::function<mem_read_f> cache_mem_rd_delegate;
+    std::function<mem_write_f> cache_mem_wr_delegate;
+    std::unique_ptr<cache::cache> dcache_ptr;
+    std::unique_ptr<cache::cache> icache_ptr;
+    size_t get_way_select() {
+        return 0;
+    }
+};
+
+
+template<typename BASE>
+inline wt_cache<BASE>::wt_cache() {
+    auto cb = base_class::replace_mem_access(
+            [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
+            [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
+    cache_mem_rd_delegate = cb.first;
+    cache_mem_wr_delegate = cb.second;
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+    if(!icache_ptr) {
+        icache_ptr.reset(new cache::cache(size, line_sz, ways));
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    }
+    if((a.val&io_addr_mask) != io_address) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    d[i] = cl.data[start_addr+i];
+                return iss::Ok;
+            }
+        }
+        auto& cl = set.ways[get_way_select()];
+        phys_addr_t cl_addr{a};
+        cl_addr.val=tag_addr<<util::ilog2(line_sz);
+        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
+        cl.tag_addr=tag_addr;
+        cl.st=cache::state::VALID;
+        auto start_addr = a.val&(line_sz-1);
+        for(auto i = 0U; i<l; ++i)
+            d[i] = cl.data[start_addr+i];
+        return iss::Ok;
+    } else
+        return cache_mem_rd_delegate(a, l, d);
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+    if(!dcache_ptr)
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    auto res = cache_mem_wr_delegate(a, l, d);
+    if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = dcache_ptr->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    cl.data[start_addr+i] = d[i];
+                break;
+            }
+        }
+    }
+    return res;
+}
+
+
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/debugger/riscv_target_adapter.h

@@ -85,7 +85,7 @@ public:
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
     status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
-                                std::vector<uint8_t> &avail_buf) override;
+            std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -104,7 +104,7 @@ public:
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
     status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             size_t &num, bool &done) override;
+            size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -120,12 +120,12 @@ public:
 
     status packetsize_query(std::string &out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
     status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                            std::function<void(unsigned)> stop_callback) override;
+            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
@@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  */
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
-                                                     bool &done) {
+        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+        bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -183,7 +183,8 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
     data.clear();
     avail.clear();
     const uint8_t *reg_base = core->get_regs_base_ptr();
-    for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
+    auto start_reg=arch::traits<ARCH>::X0;
+    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
         for (size_t j = 0; j < reg_width; ++j) {
@@ -192,40 +193,54 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
         }
     }
     // work around fill with F type registers
-//    if (arch::traits<ARCH>::NUM_REGS < 65) {
-//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-//            for (size_t j = 0; j < reg_width; ++j) {
-//                data.push_back(0x0);
-//                avail.push_back(0x00);
-//            }
-//            // if(arch::traits<ARCH>::XLEN < 64)
-//            //     for(unsigned j=0; j<4; ++j){
-//            //         data.push_back(0x0);
-//            //         avail.push_back(0x00);
-//            //     }
-//        }
-//    }
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
+    //                data.push_back(0x0);
+    //                avail.push_back(0x00);
+    //            }
+    //            // if(arch::traits<ARCH>::XLEN < 64)
+    //            //     for(unsigned j=0; j<4; ++j){
+    //            //         data.push_back(0x0);
+    //            //         avail.push_back(0x00);
+    //            //     }
+    //        }
+    //    }
     return Ok;
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
-    auto reg_count = arch::traits<ARCH>::NUM_REGS;
+    auto start_reg=arch::traits<ARCH>::X0;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
-        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
-        std::copy(iter, iter + reg_width, reg_base);
-        iter += 4;
-        reg_base += offset;
+    bool e_ext = arch::traits<ARCH>::PC<32;
+    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+        if(e_ext && reg_no>15){
+            if(reg_no==32){
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+                std::copy(iter, iter + reg_width, reg_base);
+            } else {
+                const uint64_t zero_val=0;
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+                auto iter = (uint8_t*)&zero_val;
+                std::copy(iter, iter + reg_width, reg_base);
+            }
+        } else {
+            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            std::copy(iter, iter + reg_width, reg_base);
+            iter += 4;
+            reg_base += offset;
+        }
     }
     return Ok;
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-                                                        std::vector<uint8_t> &avail) {
+        std::vector<uint8_t> &avail) {
     if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -316,34 +331,48 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
-    target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-               << saddr.val << std::dec;
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Ok;
-}
-
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
-    if (handle) {
-        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
-        // TODO: check length of addr range
-        target_adapter_base::bp_lut.removeEntry(handle);
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+        target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
+        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+                << saddr.val << std::dec;
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Err;
+    }
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+        if (handle) {
+            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                    << std::dec;
+            // TODO: check length of addr range
+            target_adapter_base::bp_lut.removeEntry(handle);
+            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            return Ok;
+        }
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        return Err;
+    }
+    }
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                                                    std::function<void(unsigned)> stop_callback) {
+        std::function<void(unsigned)> stop_callback) {
     auto *reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@@ -354,42 +383,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
     const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
-                          "<target><architecture>riscv:rv32</architecture>"
-                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
-                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"  </feature>\n"
-                          "</target>"};
+        "<target><architecture>riscv:rv32</architecture>"
+        //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+        //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+        //"  </feature>\n"
+        "</target>"};
     out_buf = res;
     return Ok;
 }

src/iss/factory.h

@@ -0,0 +1,110 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_
+
+#include <iss/iss.h>
+#include <memory>
+#include <unordered_map>
+#include <functional>
+#include <string>
+#include <algorithm>
+#include <vector>
+
+namespace iss {
+
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+
+template<typename PLAT>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
+    using core_type = typename PLAT::core;
+    core_type* lcpu = new PLAT();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_TCC
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+    return {nullptr, nullptr};
+}
+
+
+class core_factory {
+    using cpu_ptr = std::unique_ptr<iss::arch_if>;
+    using vm_ptr= std::unique_ptr<iss::vm_if>;
+    using base_t = std::tuple<cpu_ptr, vm_ptr>;
+    using create_fn = std::function<base_t(unsigned, void*) >;
+    using registry_t = std::unordered_map<std::string, create_fn> ;
+
+    registry_t registry;
+
+    core_factory() = default;
+    core_factory(const core_factory &) = delete;
+    core_factory & operator=(const core_factory &) = delete;
+
+public:
+    static core_factory & instance() { static core_factory bf; return bf; }
+
+    bool register_creator(const std::string &, create_fn const&);
+
+    base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
+
+    std::vector<std::string> get_names() {
+        std::vector<std::string> keys{registry.size()};
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
+            return p.first;
+        });
+        return keys;
+    }
+};
+
+inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
+    registry[className] = fn;
+    return true;
+}
+
+inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
+    registry_t::const_iterator regEntry = registry.find(className);
+    if (regEntry != registry.end())
+        return regEntry->second(gdb_port, data);
+    return {nullptr, nullptr};
+}
+
+}
+
+#endif /* _ISS_FACTORY_H_ */

src/iss/plugin/cycle_estimate.cpp

@@ -0,0 +1,118 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "cycle_estimate.h"
+
+#include <iss/arch_if.h>
+#include <util/logging.h>
+#include <rapidjson/document.h>
+#include <rapidjson/istreamwrapper.h>
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
+#include <rapidjson/ostreamwrapper.h>
+#include <rapidjson/error/en.h>
+#include <fstream>
+
+using namespace rapidjson;
+using namespace std;
+
+iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
+: instr_if(nullptr)
+, config_file_name(config_file_name)
+{
+}
+
+iss::plugin::cycle_estimate::~cycle_estimate() {
+}
+
+bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    if(!instr_if) return false;
+    const string  core_name = instr_if->core_type_name();
+    if (config_file_name.length() > 0) {
+        ifstream is(config_file_name);
+        if (is.is_open()) {
+            try {
+                IStreamWrapper isw(is);
+                Document d;
+                ParseResult ok = d.ParseStream(isw);
+                if(ok) {
+                    Value& val = d[core_name.c_str()];
+                    if(val.IsArray()){
+                        delays.reserve(val.Size());
+                        for (auto it = val.Begin(); it != val.End(); ++it) {
+                            auto& name = (*it)["name"];
+                            auto& size = (*it)["size"];
+                            auto& delay = (*it)["delay"];
+                            auto& branch = (*it)["branch"];
+                            if(delay.IsArray()) {
+                                auto dt = delay[0].Get<unsigned>();
+                                auto dnt = delay[1].Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
+                            } else if(delay.Is<unsigned>()) {
+                                auto d = delay.Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
+                            } else
+                                throw runtime_error("JSON parse error");
+                       }
+                    } else {
+                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
+                        return false;
+                   }
+                } else {
+                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
+                    return false;
+               }
+            } catch (runtime_error &e) {
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            LOG(ERR) << "Could not open input file " << config_file_name;
+            return false;
+        }
+    }
+    return true;
+
+}
+
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
+    assert(instr_if && "No instrumentation interface available but callback executed");
+    auto entry = delays[instr_info.instr_id];
+    bool taken = instr_if->is_branch_taken();
+    if (taken && (entry.taken > 1))
+        instr_if->update_last_instr_cycles(entry.taken);
+    else if (entry.not_taken > 1)
+        instr_if->update_last_instr_cycles(entry.not_taken);
+}

src/iss/plugin/cycle_estimate.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,23 +37,25 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
-#include <json/json.h>
 #include <string>
 #include <unordered_map>
+#include <vector>
 
 namespace iss {
 
 namespace plugin {
 
-class cycle_estimate: public iss::vm_plugin {
+class cycle_estimate: public vm_plugin {
 	BEGIN_BF_DECL(instr_desc, uint32_t)
 		BF_FIELD(taken, 24, 8)
 		BF_FIELD(not_taken, 16, 8)
-		BF_FIELD(size, 0, 16)
-		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
+        BF_FIELD(is_branch, 8, 8)
+        BF_FIELD(size, 0, 8)
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
 			this->size=size;
 			this->taken=taken;
 			this->not_taken=not_taken;
+			this->is_branch=branch;
 		}
 	END_BF_DECL();
 
@@ -64,7 +66,7 @@ public:
 
     cycle_estimate(const cycle_estimate &&) = delete;
 
-    cycle_estimate(std::string config_file_name);
+    cycle_estimate(std::string const& config_file_name);
 
     virtual ~cycle_estimate();
 
@@ -79,7 +81,7 @@ public:
     void callback(instr_info_t instr_info) override;
 
 private:
-    iss::instrumentation_if *arch_instr;
+    iss::instrumentation_if *instr_if;
     std::vector<instr_desc> delays;
     struct pair_hash {
         size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
@@ -88,7 +90,7 @@ private:
         }
     };
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
-    Json::Value root;
+    std::string config_file_name;
 };
 }
 }

src/iss/plugin/instruction_count.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,8 +32,8 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "iss/plugin/instruction_count.h"
-#include "iss/instrumentation_if.h"
+#include "instruction_count.h"
+#include <iss/instrumentation_if.h>
 
 #include <iss/arch_if.h>
 #include <util/logging.h>
@@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
             try {
                 is >> root;
             } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
         }
     }
 }
@@ -85,7 +85,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
     	}
     	rep_counts.resize(delays.size());
     } else {
-        LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
     }
 	return true;
 }

src/iss/plugin/instruction_count.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -69,7 +69,7 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t instr_info) override;
+    void callback(instr_info_t) override;
 
 private:
     Json::Value root;

src/iss/plugin/pctrace.cpp

@@ -0,0 +1,214 @@
+/*******************************************************************************