add clic CSRs
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@ -104,12 +104,19 @@ enum riscv_csr {
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mie = 0x304,
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mtvec = 0x305,
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mcounteren = 0x306,
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mtvt = 0x307, //CLIC
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// Machine Trap Handling
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mscratch = 0x340,
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mepc = 0x341,
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mcause = 0x342,
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mtval = 0x343,
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mip = 0x344,
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mxnti = 0x345, //CLIC
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mintstatus = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
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mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
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mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
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mintthresh = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
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mclicbase = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
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// Physical Memory Protection
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pmpcfg0 = 0x3A0,
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pmpcfg1 = 0x3A1,
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@ -66,7 +66,7 @@
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namespace iss {
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namespace arch {
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enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N};
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enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};
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template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
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protected:
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@ -406,6 +406,22 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
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csr_rd_cb[medeleg] = &this_class::read_reg;
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csr_wr_cb[medeleg] = &this_class::write_reg;
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}
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if(FEAT & FEAT_CLIC) {
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csr_rd_cb[mtvt] = &this_class::read_reg;
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csr_wr_cb[mtvt] = &this_class::write_reg;
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csr_rd_cb[mxnti] = &this_class::read_reg;
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csr_wr_cb[mxnti] = &this_class::write_reg;
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csr_rd_cb[mintstatus] = &this_class::read_reg;
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csr_wr_cb[mintstatus] = &this_class::write_reg;
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csr_rd_cb[mscratchcsw] = &this_class::read_reg;
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csr_wr_cb[mscratchcsw] = &this_class::write_reg;
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csr_rd_cb[mscratchcswl] = &this_class::read_reg;
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csr_wr_cb[mscratchcswl] = &this_class::write_reg;
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csr_rd_cb[mintthresh] = &this_class::read_reg;
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csr_wr_cb[mintthresh] = &this_class::write_reg;
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csr_rd_cb[mclicbase] = &this_class::read_reg;
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csr_wr_cb[mclicbase] = &this_class::write_reg;
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}
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}
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template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
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