DBT-RISE/DBT-RISE-TGC
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correct trap ids of access faults

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This commit is contained in:
Eyck Jentzsch 2021-08-20 09:02:56 +02:00
parent c409e7b7ca
commit 9c8b72693e
1 changed files with 2 additions and 2 deletions
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4
incl/iss/arch/riscv_hart_mu_p.h
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@ -600,7 +600,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31) | (1 << 16); // issue trap 1
this->reg.trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
return iss::Err;
}
}
@ -695,7 +695,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31) | (1 << 16); // issue trap 1
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 1
return iss::Err;
}
}