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DBT-RISE-TGC
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regenerated sources and and add opcode enum to headers 

Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
This commit is contained in:
Eyck Jentzsch 2021-03-01 06:26:33 +00:00
parent 1668df0531
commit 9534d58d01
17 changed files with 361 additions and 609 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit 3cfac1d86f6532140a04cdfc1501f1b8f3729632
Subproject commit 89763fcb973838a634e48ee05dca28782807b344

2
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -33,7 +33,7 @@
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=64 // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
return regs
}
%>

37
gen_input/templates/interp/CORENAME.h.gtl
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,22 +29,23 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
<%
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=pc.size // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
def regs = registers.collect{nativeTypeSize(it.size)}
regs+=[32,32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
return regs
}
def getRegisterOffsets(){
def regs = registers.collect{it.offset}
def offs= regs[-1]
// append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT offsets starting with NEXT_PC size
[pc.size/8, 4, 4, 4, 4].each{ sz ->
regs+=offs+sz
offs+=sz
def offset = 0
def offsets = []
getRegisterSizes().each { size ->
offsets<<offset
offset+=size/8
}
return regs
return offsets
}
def byteSize(int size){
if(size<=8) return 8;
@ -81,15 +82,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
registers.each { reg -> %>
${reg.name},<%
}%>
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
enum reg_e {
${registers.collect{it.name}.join(', ')}, NUM_REGS,
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT
};
@ -168,7 +164,6 @@ protected:
registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%>
uint${byteSize(pc.size)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;

13
gen_input/templates/interp/vm_CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* Copyright (C) 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -149,13 +149,14 @@ protected:
this->core.leave_trap(lvl);
auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
this->template get_reg<uint32_t>(traits::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
}
void wait(unsigned type){
this->core.wait_until(type);
}
template<typename T>
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
@ -196,17 +197,15 @@ private:
// prepare execution
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction
<%instr.behavior.eachLine{%>${it}
<%}%>// post execution stuff<% if(instr.modifiesPC) { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);<% } else { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + ${instr.length/8};<% } %>
<%}%>// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);

2
incl/iss/arch/riscv_hart_m_p.h
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@ -302,7 +302,7 @@ public:
void write_mstatus(T val) {
auto mask = get_mask();
auto new_val = (mstatus.st.value & ~mask) | (val & mask);
auto new_val = (mstatus.storage.val & ~mask) | (val & mask);
mstatus = new_val;
}

57
incl/iss/arch/tgf_b.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -48,56 +48,19 @@ template <> struct traits<tgf_b> {
constexpr static char const* const core_type = "TGF_B";
static constexpr std::array<const char*, 35> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
static constexpr std::array<const char*, 35> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3};
constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
PRIV,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT
};
@ -111,11 +74,11 @@ template <> struct traits<tgf_b> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 40> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 38> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -257,8 +220,8 @@ protected:
uint32_t X30 = 0;
uint32_t X31 = 0;
uint32_t PC = 0;
uint32_t NEXT_PC = 0;
uint8_t PRIV = 0;
uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;

57
incl/iss/arch/tgf_c.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -48,56 +48,19 @@ template <> struct traits<tgf_c> {
constexpr static char const* const core_type = "TGF_C";
static constexpr std::array<const char*, 35> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
static constexpr std::array<const char*, 35> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
PRIV,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT
};
@ -111,11 +74,11 @@ template <> struct traits<tgf_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 40> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 38> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -293,8 +256,8 @@ protected:
uint32_t X30 = 0;
uint32_t X31 = 0;
uint32_t PC = 0;
uint32_t NEXT_PC = 0;
uint8_t PRIV = 0;
uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;

2
incl/iss/plugin/cycle_estimate.h
View File

@ -76,7 +76,7 @@ public:
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t instr_info) override;
void callback(instr_info_t instr_info, exec_info const&) override;
private:
iss::instrumentation_if *arch_instr;

2
incl/iss/plugin/instruction_count.h
View File

@ -69,7 +69,7 @@ public:
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t instr_info) override;
void callback(instr_info_t, exec_info const&) override;
private:
Json::Value root;

4
src/iss/tgf_b.cpp
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@ -41,8 +41,8 @@ using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
tgf_b::tgf_b() {
reg.icount = 0;

4
src/iss/tgf_c.cpp
View File

@ -41,8 +41,8 @@ using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
tgf_c::tgf_c() {
reg.icount = 0;

2
src/plugin/cycle_estimate.cpp
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@ -83,7 +83,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
}
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
assert(arch_instr && "No instrumentation interface available but callback executed");
auto entry = delays[instr_info.instr_id];
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);

2
src/plugin/instruction_count.cpp
View File

@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
return true;
}
void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
rep_counts[instr_info.instr_id]++;
}

281
src/vm/interp/vm_tgf_b.cpp
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File diff suppressed because it is too large Load Diff

473
src/vm/interp/vm_tgf_c.cpp
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File diff suppressed because it is too large Load Diff

12
src/vm/tcc/vm_tgf_b.cpp
View File

@ -377,7 +377,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
gen_trap_check(tu);
@ -424,7 +423,6 @@ private:
new_pc_val,
tu.l_not(tu.constant(0x1, 32U))), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
tu.close_scope();
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
@ -466,7 +464,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
gen_trap_check(tu);
@ -507,7 +504,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
gen_trap_check(tu);
@ -552,7 +548,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
gen_trap_check(tu);
@ -597,7 +592,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
gen_trap_check(tu);
@ -638,7 +632,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
gen_trap_check(tu);
@ -679,7 +672,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
gen_trap_check(tu);
@ -1621,7 +1613,6 @@ private:
tu.constant(1, 64U),
tu.trunc(tu.constant(imm, 32U), 32));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
gen_trap_check(tu);
@ -2055,13 +2046,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
tu("leave_trap(core_ptr, {});", lvl);
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@ -2070,7 +2059,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry:");
tu("enter_trap(core_ptr, *trap_state, *pc);");
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
tu("return *next_pc;");
}

18
src/vm/tcc/vm_tgf_c.cpp
View File

@ -449,7 +449,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
gen_trap_check(tu);
@ -487,7 +486,6 @@ private:
new_pc_val,
tu.l_not(tu.constant(0x1, 32U))), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
gen_trap_check(tu);
@ -528,7 +526,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
gen_trap_check(tu);
@ -569,7 +566,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
gen_trap_check(tu);
@ -614,7 +610,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
gen_trap_check(tu);
@ -659,7 +654,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
gen_trap_check(tu);
@ -700,7 +694,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
gen_trap_check(tu);
@ -741,7 +734,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
gen_trap_check(tu);
@ -1683,7 +1675,6 @@ private:
tu.constant(1, 64U),
tu.trunc(tu.constant(imm, 32U), 32));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
gen_trap_check(tu);
@ -2562,7 +2553,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
gen_trap_check(tu);
@ -2868,7 +2858,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 76);
gen_trap_check(tu);
@ -2908,7 +2897,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 77);
gen_trap_check(tu);
@ -2948,7 +2936,6 @@ private:
auto is_cont_v = tu.choose(
tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
tu.constant(0U, 32), tu.constant(1U, 32));
tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);
gen_trap_check(tu);
@ -3055,7 +3042,6 @@ private:
tu.open_scope();
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 82);
gen_trap_check(tu);
@ -3108,7 +3094,6 @@ private:
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 84);
gen_trap_check(tu);
@ -3247,13 +3232,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
tu("leave_trap(core_ptr, {});", lvl);
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
}
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@ -3262,7 +3245,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("trap_entry:");
tu("enter_trap(core_ptr, *trap_state, *pc);");
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
tu("return *next_pc;");
}