DBT-RISE
/
DBT-RISE-TGC
13
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

add read misa callback

This commit is contained in:
Stanislaw Kaushanski 2021-04-09 11:20:51 +02:00
parent 2f4cfb68dc
commit ef02dba8c5
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
incl/iss/arch/riscv_hart_m_p.h
View File

@ -309,8 +309,6 @@ public:
T satp;
static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
static constexpr uint32_t get_mask() {
return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 // only machine mode is supported
}
@ -434,10 +432,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
: state()
, cycle_offset(0)
, instr_if(*this) {
csr[misa] = hart_state<reg_t>::get_misa();
csr[misa] = traits<BASE>::MISA_VAL;
uart_buf.str("");
// read-only registers
csr_wr_cb[misa] = nullptr;
for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
// special handling
@ -462,6 +458,9 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
}
// read-only registers
csr_rd_cb[misa] = &riscv_hart_m_p<BASE>::read_reg;
csr_wr_cb[misa] = nullptr;
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {