diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index 6c9a099..8b0b594 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -309,8 +309,6 @@ public:
 
         T satp;
 
-        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
-
         static constexpr uint32_t get_mask() {
             return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
         }
@@ -434,10 +432,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
 : state()
 , cycle_offset(0)
 , instr_if(*this) {
-    csr[misa] = hart_state<reg_t>::get_misa();
+    csr[misa] = traits<BASE>::MISA_VAL;
     uart_buf.str("");
-    // read-only registers
-    csr_wr_cb[misa] = nullptr;
     for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
     for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
     // special handling
@@ -462,6 +458,9 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
         csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
         csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
     }
+    // read-only registers
+    csr_rd_cb[misa] = &riscv_hart_m_p<BASE>::read_reg;
+    csr_wr_cb[misa] = nullptr;
 }
 
 template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {