fix mu_p platform features and CSRs
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4b3f5a6b0c
commit
aaceecd5dc
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@ -147,8 +147,6 @@ protected:
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inline void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
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this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
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}
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inline void wait(unsigned type){
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@ -66,7 +66,9 @@
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namespace iss {
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namespace arch {
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template <typename BASE, bool PMP=false> class riscv_hart_mu_p : public BASE {
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enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N};
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template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
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protected:
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const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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const std::array<const char *, 16> trap_str = {{""
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@ -92,7 +94,7 @@ protected:
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
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public:
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using super = BASE;
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using this_class = riscv_hart_mu_p<BASE, PMP>;
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using this_class = riscv_hart_mu_p<BASE, FEAT>;
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using phys_addr_t = typename super::phys_addr_t;
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using reg_t = typename super::reg_t;
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using addr_t = typename super::addr_t;
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@ -218,7 +220,7 @@ public:
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if {
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riscv_instrumentation_if(riscv_hart_mu_p<BASE, PMP> &arch)
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riscv_instrumentation_if(riscv_hart_mu_p<BASE, FEAT> &arch)
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: arch(arch) {}
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/**
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* get the name of this architecture
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@ -233,7 +235,7 @@ protected:
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virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
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riscv_hart_mu_p<BASE, PMP> &arch;
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riscv_hart_mu_p<BASE, FEAT> &arch;
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};
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friend struct riscv_instrumentation_if;
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@ -286,8 +288,8 @@ protected:
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void check_interrupt();
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};
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template <typename BASE, bool PMP>
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riscv_hart_mu_p<BASE, PMP>::riscv_hart_mu_p()
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template <typename BASE, features_e FEAT>
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riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
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: state()
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, cycle_offset(0)
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, instr_if(*this) {
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@ -326,9 +328,26 @@ riscv_hart_mu_p<BASE, PMP>::riscv_hart_mu_p()
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// read-only registers
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csr_rd_cb[misa] = &this_class::read_reg;
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csr_wr_cb[misa] = nullptr;
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if(FEAT & FEAT_PMP){
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for(size_t i=pmpaddr0; i<=pmpaddr15; ++i){
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csr_rd_cb[i] = &this_class::read_reg;
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csr_wr_cb[i] = &this_class::write_reg;
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}
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for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
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csr_rd_cb[i] = &this_class::read_reg;
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csr_wr_cb[i] = &this_class::write_reg;
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}
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}
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if(FEAT & FEAT_EXT_N){
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csr_rd_cb[mideleg] = &this_class::read_reg;
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csr_wr_cb[mideleg] = &this_class::write_reg;
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csr_rd_cb[medeleg] = &this_class::read_reg;
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csr_wr_cb[medeleg] = &this_class::write_reg;
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}
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}
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template <typename BASE, bool PMP> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, PMP>::load_file(std::string name, int type) {
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template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
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FILE *fp = fopen(name.c_str(), "r");
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if (fp) {
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std::array<char, 5> buf;
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@ -372,8 +391,8 @@ template <typename BASE, bool PMP> std::pair<uint64_t, bool> riscv_hart_mu_p<BAS
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throw std::runtime_error("memory load file not found");
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}
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template <typename BASE, bool PMP>
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iss::status riscv_hart_mu_p<BASE, PMP>::read(const address_type type, const access_type access, const uint32_t space,
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, uint8_t *const data) {
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#ifndef NDEBUG
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if (access && iss::access_type::DEBUG) {
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@ -430,8 +449,8 @@ iss::status riscv_hart_mu_p<BASE, PMP>::read(const address_type type, const acce
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}
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}
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template <typename BASE, bool PMP>
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iss::status riscv_hart_mu_p<BASE, PMP>::write(const address_type type, const access_type access, const uint32_t space,
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, const uint8_t *const data) {
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#ifndef NDEBUG
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const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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@ -537,7 +556,7 @@ iss::status riscv_hart_mu_p<BASE, PMP>::write(const address_type type, const acc
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}
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_csr(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
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if (addr >= csr.size()) return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if (this->reg.PRIV < req_priv_lvl) // not having required privileges
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@ -548,7 +567,7 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_
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return (this->*(it->second))(addr, val);
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write_csr(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
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if (addr >= csr.size()) return iss::Err;
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auto req_priv_lvl = (addr >> 8) & 0x3;
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if (this->reg.PRIV < req_priv_lvl) // not having required privileges
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@ -561,17 +580,17 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write
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return (this->*(it->second))(addr, val);
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_reg(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_reg(unsigned addr, reg_t &val) {
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val = csr[addr];
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write_reg(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_reg(unsigned addr, reg_t val) {
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csr[addr] = val;
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_cycle(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
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auto cycle_val = this->reg.icount + cycle_offset;
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if (addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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@ -582,7 +601,7 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_time(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
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uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
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if (addr == time) {
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val = static_cast<reg_t>(time_val);
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@ -593,31 +612,31 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_status(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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val = state.mstatus & hart_state_type::get_mask(req_priv_lvl);
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write_status(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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state.write_mstatus(val, req_priv_lvl);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_ie(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
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val = csr[mie];
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val &= csr[mideleg];
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_hartid(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
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val = mhartid_reg;
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write_ie(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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csr[mie] = (csr[mie] & ~mask) | (val & mask);
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@ -625,13 +644,13 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::read_ip(unsigned addr, reg_t &val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
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val = csr[mip];
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val &= csr[mideleg];
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return iss::Ok;
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}
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template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write_ip(unsigned addr, reg_t val) {
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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mask &= ~(1 << 7); // MTIP is read only
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@ -640,8 +659,8 @@ template <typename BASE, bool PMP> iss::status riscv_hart_mu_p<BASE, PMP>::write
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return iss::Ok;
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}
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template <typename BASE, bool PMP>
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iss::status riscv_hart_mu_p<BASE, PMP>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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if ((paddr.val + length) > mem.size()) return iss::Err;
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if(mem_read_cb) return mem_read_cb(paddr, length, data);
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switch (paddr.val) {
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@ -666,8 +685,8 @@ iss::status riscv_hart_mu_p<BASE, PMP>::read_mem(phys_addr_t paddr, unsigned len
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return iss::Ok;
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}
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template <typename BASE, bool PMP>
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iss::status riscv_hart_mu_p<BASE, PMP>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
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if ((paddr.val + length) > mem.size()) return iss::Err;
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if(mem_write_cb) return mem_write_cb(paddr, length, data);
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switch (paddr.val) {
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@ -743,12 +762,12 @@ iss::status riscv_hart_mu_p<BASE, PMP>::write_mem(phys_addr_t paddr, unsigned le
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return iss::Ok;
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}
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template <typename BASE, bool PMP> inline void riscv_hart_mu_p<BASE, PMP>::reset(uint64_t address) {
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template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT>::reset(uint64_t address) {
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BASE::reset(address);
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state.mstatus = hart_state_type::mstatus_reset_val;
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}
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template <typename BASE, bool PMP> void riscv_hart_mu_p<BASE, PMP>::check_interrupt() {
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template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::check_interrupt() {
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auto ideleg = csr[mideleg];
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// Multiple simultaneous interrupts and traps at the same privilege level are
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// handled in the following decreasing priority order:
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@ -770,7 +789,7 @@ template <typename BASE, bool PMP> void riscv_hart_mu_p<BASE, PMP>::check_interr
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}
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}
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template <typename BASE, bool PMP> uint64_t riscv_hart_mu_p<BASE, PMP>::enter_trap(uint64_t flags, uint64_t addr) {
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr) {
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// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
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// calculate and write mcause val
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auto trap_id = bit_sub<0, 16>(flags);
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return this->reg.NEXT_PC;
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}
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template <typename BASE, bool PMP> uint64_t riscv_hart_mu_p<BASE, PMP>::leave_trap(uint64_t flags) {
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::leave_trap(uint64_t flags) {
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auto cur_priv = this->reg.PRIV;
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auto inst_priv = (flags & 0x3)? 3:0;
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auto status = state.mstatus;
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// pop the relevant lower-privilege interrupt enable and privilege mode stack
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// clear respective yIE
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switch (inst_priv) {
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}
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// sets the pc to the value stored in the x epc register.
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this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
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CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[this->reg.PRIV] << " to "
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CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
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<< lvl[this->reg.PRIV];
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return this->reg.NEXT_PC;
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}
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@ -47,7 +47,7 @@ using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
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#ifdef CORE_TGC_D
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#include "iss/arch/riscv_hart_mu_p.h"
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#include "iss/arch/tgc_d.h"
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using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d>;
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using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
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#endif
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#ifdef WITH_LLVM
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#include <iss/llvm/jit_helper.h>
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@ -44,7 +44,7 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
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#ifdef CORE_TGC_D
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#include "iss/arch/riscv_hart_mu_p.h"
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#include "iss/arch/tgc_d.h"
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using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d>;
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using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
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#endif
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#include "iss/debugger/encoderdecoder.h"
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#include "iss/debugger/gdb_session.h"
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