fix wait for interrupt. Adapt for new SCC structure

CMakeLists.txt

@@ -60,7 +60,7 @@ endif()
 
 target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
 target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
 target_link_libraries(${PROJECT_NAME} PUBLIC ${Boost_LIBRARIES} )
 set_target_properties(${PROJECT_NAME} PROPERTIES
@@ -78,7 +78,7 @@ if(SystemC_FOUND)
 	    target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SCV)
 	    target_include_directories(${PROJECT_NAME}_sc PUBLIC ${SCV_INCLUDE_DIRS})
 	endif()
-	target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${PROJECT_NAME} scc )
+	target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${PROJECT_NAME} scc)
 	if(WITH_LLVM)
 		target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${llvm_libs})
 	endif()

incl/iss/arch/riscv_hart_m_p.h

@@ -894,7 +894,10 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
 
     if (enabled_interrupts != 0) {
         int res = 0;
-        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
+        while ((enabled_interrupts & 1) == 0) {
+        	enabled_interrupts >>= 1;
+        	res++;
+        }
         this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
@@ -946,20 +949,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
 }
 
 template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    /* TODO: configurable support of User mode
-    auto cur_priv = this->reg.PRIV;
-    auto inst_priv = flags & 0x3;
-    auto status = state.mstatus;
-
-    // pop the relevant lower-privilege interrupt enable and privilege mode stack
-    // clear respective yIE
-    if (inst_priv == PRIV_M) {
-        this->reg.PRIV = state.mstatus.MPP;
-        state.mstatus.MPP = 0; // clear mpp to U mode
-        state.mstatus.MIE = state.mstatus.MPIE;
-    } else {
-    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
-    }*/
+    state.mstatus.MIE = state.mstatus.MPIE;
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = csr[mepc];
     CLOG(INFO, disass) << "Executing xRET";

incl/sysc/core_complex.h

@@ -33,10 +33,10 @@
 #ifndef _SYSC_SIFIVE_FE310_H_
 #define _SYSC_SIFIVE_FE310_H_
 
-#include "scc/initiator_mixin.h"
+#include "tlm/scc/initiator_mixin.h"
 #include "scc/traceable.h"
 #include "scc/utilities.h"
-#include "scv4tlm/tlm_rec_initiator_socket.h"
+#include "tlm/scc/scv4tlm/tlm_rec_initiator_socket.h"
 #include <cci_configuration>
 #include <tlm>
 #include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
@@ -75,7 +75,7 @@ class core_wrapper;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::scc::scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
 
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 

src/sysc/core_complex.cpp

@@ -191,6 +191,8 @@ public:
         } else
             this->csr[arch::mip] &= ~mask;
         this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
 
 private: