remove MSVC warning

add MSVC 16 compatibility
fix find_package use and debug access alignment check
2021-10-10 19:56:33 +02:00 · 2021-10-10 19:06:41 +02:00 · 2021-08-26 22:10:27 +02:00 · 2021-08-20 09:02:56 +02:00 · 2021-08-19 13:38:29 +02:00 · 2021-08-19 10:50:25 +02:00
38 changed files with 8734 additions and 7050 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -1,20 +1,21 @@
 cmake_minimum_required(VERSION 3.12)
-
-project("riscv" VERSION 1.0.0)
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc VERSION 1.0.0)

 include(GNUInstallDirs)

-conan_basic_setup()
+find_package(elfio)

-find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
 if(WITH_LLVM)
-	if(DEFINED ENV{LLVM_HOME})
-		find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-	endif(DEFINED ENV{LLVM_HOME})
-	find_package(LLVM REQUIRED CONFIG)
-	message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-	message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-	llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+    if(DEFINED ENV{LLVM_HOME})
+        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+    endif(DEFINED ENV{LLVM_HOME})
+    find_package(LLVM REQUIRED CONFIG)
+    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
 endif()

 #Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
@ -27,97 +28,142 @@ endif()
 add_subdirectory(softfloat)

 # library files
-FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
-set(LIB_HEADERS ${RiscVSCHeaders} )
+FILE(GLOB TGC_SOURCES
+    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
+    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
+)
 set(LIB_SOURCES 
-	src/iss/tgf_b.cpp
-	src/iss/tgf_c.cpp
-	src/vm/fp_functions.cpp
-	src/vm/tcc/vm_tgf_b.cpp
-	src/vm/tcc/vm_tgf_c.cpp
-	src/vm/interp/vm_tgf_b.cpp
-	src/vm/interp/vm_tgf_c.cpp
+    src/vm/fp_functions.cpp
    src/plugin/instruction_count.cpp
    src/plugin/cycle_estimate.cpp
+    ${TGC_SOURCES}
 )
+
 if(WITH_LLVM)
-set(LIB_SOURCES ${LIB_SOURCES}
-	src/vm/llvm/fp_impl.cpp
-	src/vm/llvm/vm_tgf_b.cpp
-	src/vm/llvm/vm_tgf_c.cpp
-)
+  set(LIB_SOURCES ${LIB_SOURCES}
+    src/vm/llvm/fp_impl.cpp
+    #src/vm/llvm/vm_tgf_b.cpp
+    #src/vm/llvm/vm_tgf_c.cpp
+  )
 endif()

 # Define the library
-add_library(riscv SHARED ${LIB_SOURCES})
-target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
-target_include_directories(riscv PUBLIC incl ../external/elfio)
-target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-set_target_properties(riscv PROPERTIES
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
+# list code gen dependencies
+if(TARGET ${CORE_NAME}_cpp)
+    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
+endif()
+
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
+    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
+endif()
+target_include_directories(${PROJECT_NAME} PUBLIC incl)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
+endif()
+if(TARGET CONAN_PKG::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
+elseif(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+
+set_target_properties(${PROJECT_NAME} PROPERTIES
  VERSION ${PROJECT_VERSION}
  FRAMEWORK FALSE
-  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )
-
-if(SystemC_FOUND)
-	add_library(riscv_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC) 
-	target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
-	
-	if(SCV_FOUND)   
-	    target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
-	    target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
-	endif()
-	target_link_libraries(riscv_sc PUBLIC riscv scc )
-	if(WITH_LLVM)
-		target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
-	endif()
-	target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
-	set_target_properties(riscv_sc PROPERTIES
-	  VERSION ${PROJECT_VERSION}
-	  FRAMEWORK FALSE
-	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
-	)
-endif()
-
-project("riscv-sim")
-add_executable(riscv-sim src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
-target_include_directories(riscv-sim PRIVATE ../external/libGIS)
-if(WITH_LLVM)
-	target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
-	target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
-endif()
-# Links the target exe against the libraries
-target_link_libraries(riscv-sim riscv)
-target_link_libraries(riscv-sim jsoncpp)
-target_link_libraries(riscv-sim external)
-target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
-if (Tcmalloc_FOUND)
-    target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
-endif(Tcmalloc_FOUND)
-
-install(TARGETS riscv riscv-sim
+install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel   # headers for mac (note the different component -> different package)
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
-
-
-
+install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
+        DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
+        FILES_MATCHING # install only matched files
+        PATTERN "*.h" # select header files
+        )
+###############################################################################
 #
-# SYSTEM PACKAGING (RPM, TGZ, ...)
-# _____________________________________________________________________________
+###############################################################################
+project(tgc-sim)
+find_package(Boost COMPONENTS program_options thread REQUIRED)

-#include(CPackConfig)
+add_executable(${PROJECT_NAME} src/main.cpp)
+# This sets the include directory for the reference project. This is the -I flag in gcc.
+target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+if(WITH_LLVM)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+endif()
+# Links the target exe against the libraries
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options Boost::thread)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY} ${BOOST_thread_LIBRARY})
+endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
+if (Tcmalloc_FOUND)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
+endif(Tcmalloc_FOUND)

+install(TARGETS tgc-sim
+  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
+  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+)
+###############################################################################
 #
-# CMAKE PACKAGING (for other CMake projects to use this one easily)
-# _____________________________________________________________________________
+###############################################################################
+project(dbt-rise-tgc_sc VERSION 1.0.0)
+
+include(SystemCPackage)
+if(SystemC_FOUND)
+    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
+    endif()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
+    endif()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
+    endif()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    if(WITH_LLVM)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    endif()
+    
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    set_target_properties(${PROJECT_NAME} PROPERTIES
+      VERSION ${PROJECT_VERSION}
+      FRAMEWORK FALSE
+      PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+    )
+    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+	  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+	  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
+	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+	)    
+endif()

-#include(PackageConfigurator)
--- a/contrib/build.tcl
+++ b/contrib/build.tcl
@ -0,0 +1,30 @@
+namespace eval Specification {
+    proc buildproc { args } {
+        global env
+        variable installDir
+        variable compiler
+        variable compiler [::scsh::get_backend_compiler]
+        #  set target $machine
+        set target [::scsh::machine]
+        set linkerOptions ""
+        set preprocessorOptions ""
+        set libversion $compiler
+        switch -exact -- $target {
+            "linux" {
+            	set install_dir $::env(TGFS_INSTALL_ROOT)
+                set incldir "${install_dir}/include"
+                set libdir "${install_dir}/lib64"
+                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
+                # Set the Linker paths.
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+            }
+            default {
+               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
+               return
+            }
+        }
+        ::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
+        ::scsh::cwr_append_ipsimbld_opts linker       "$linkerOptions"
+    }
+    ::scsh::add_build_callback [namespace current]::buildproc
+}
--- a/contrib/tgc_import.cc
+++ b/contrib/tgc_import.cc
@ -0,0 +1,4 @@
+
+#include "sysc/core_complex.h"
+
+void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }
--- a/contrib/tgc_import.tcl
+++ b/contrib/tgc_import.tcl
@ -0,0 +1,50 @@
+#############################################################################
+#
+#############################################################################
+proc getScriptDirectory {} {
+    set dispScriptFile [file normalize [info script]]
+    set scriptFolder [file dirname $dispScriptFile]
+    return $scriptFolder
+}
+if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
+    set hardware /HARDWARE/HW/HW
+} else {
+    set hardware /HARDWARE
+}
+
+set scriptDir [getScriptDirectory]
+set top_design_name core_complex
+set clocks clk_i
+set resets rst_i
+set model_prefix "i_"
+set model_postfix ""
+
+::pct::new_project
+::pct::open_library TLM2_PL
+::pct::clear_systemc_defines
+::pct::clear_systemc_include_path
+::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
+::pct::set_import_protocol_generation_flag false
+::pct::set_update_existing_encaps_flag true
+::pct::set_dynamic_port_arrays_flag true
+::pct::set_import_scml_properties_flag true
+::pct::load_modules --set-category modules tgc_import.cc
+
+# Set Port Protocols correctly
+set block ${top_design_name}
+foreach clock ${clocks} {
+	::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
+}
+foreach reset ${resets} {
+    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
+}
+::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+
+# Set compile settings and look
+set block SYSTEM_LIBRARY:${top_design_name}
+::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_background_color_rgb $block 255 255 255 255
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+
+# export the result as component
+::pct::export_system_library ${top_design_name}  ${top_design_name}.xml
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
--- a/gen_input/TGFS.core_desc
+++ b/gen_input/TGFS.core_desc
@ -2,27 +2,36 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

-Core TGF_B provides RV32I {
-	constants {
-        XLEN:=32;
-        PCLEN:=32;
+Core TGC_B provides RV32I {
+	architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
 	}
 }

-Core TGF_C provides RV32I, RV32M, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
+Core TGC_C provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000001000100000100;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
    }
-}
+}
+
+Core TGC_D provides RV32I, RV32M, RV32IC {
+    architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+    }
+}
--- a/gen_input/minres_rv.core_desc
+++ b/gen_input/minres_rv.core_desc
@ -1,74 +0,0 @@
-import "RV32I.core_desc"
-import "RV64I.core_desc"
-import "RVM.core_desc"
-import "RVA.core_desc"
-import "RVC.core_desc"
-import "RVF.core_desc"
-import "RVD.core_desc"
-
-
-Core MNRV32 provides RV32I, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
-    constants {
-        XLEN:=32;
-        FLEN:=64;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64I provides RV64I {
-    constants {
-        XLEN:=64;
-        PCLEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b10000000000001000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
-    constants {
-        XLEN:=64;
-        FLEN:=64;
-        PCLEN:=64;
-        MUL_LEN:=128;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
--- a/gen_input/templates/interp/src-CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/src-CORENAME.cpp.gtl
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -29,43 +29,12 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
+<% 
+def getRegisterSizes(){
+	def regs = registers.collect{it.size}
+	regs[-1]=64 // correct for NEXT_PC
+	regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+    return regs
 }
 %>
 #include "util/ities.h"
@ -77,10 +46,10 @@ def getRegisterAliasNames(){

 using namespace iss::arch;

-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;

 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
    reg.icount = 0;
@ -92,8 +61,8 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
    reg.trap_state=0;
-    reg.machine_state=0x3;
    reg.icount=0;
 }

--- a/gen_input/templates/interp/incl-CORENAME.h.gtl
+++ b/gen_input/templates/interp/incl-CORENAME.h.gtl
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -29,47 +29,38 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
+<%
+import com.minres.coredsl.util.BigIntegerWithRadix

-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
+def getRegisterSizes(){
+    def regs = registers.collect{nativeTypeSize(it.size)}
+    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+    return regs
+}
+def getRegisterOffsets(){
+    def offset = 0
+    def offsets = []
+    getRegisterSizes().each { size ->
+        offsets<<offset
+        offset+=size/8
    }
+    return offsets
 }
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
+def byteSize(int size){
+    if(size<=8) return 8;
+    if(size<=16) return 16;
+    if(size<=32) return 32;
+    if(size<=64) return 64;
+    return 128;
 }
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
+def getCString(def val){
+    if(val instanceof BigIntegerWithRadix)
+        return ((BigIntegerWithRadix)val).toCString()
+    else
+        return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
@ -87,43 +78,28 @@ struct ${coreDef.name.toLowerCase()};

 template <> struct traits<${coreDef.name.toLowerCase()}> {

-	constexpr static char const* const core_type = "${coreDef.name}";
+    constexpr static char const* const core_type = "${coreDef.name}";
    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
+    static constexpr std::array<const char*, ${registers.size}> reg_names{
+        {"${registers.collect{it.name}.join('", "')}"}};
 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
+    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
+        {"${registers.collect{it.alias}.join('", "')}"}};

-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};

-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};

-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
+    enum reg_e {
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
+        TRAP_STATE=NUM_REGS,
        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
+        ICOUNT,
+        CYCLE,
+        INSTRET
    };

-    using reg_t = uint${regDataWidth}_t;
+    using reg_t = uint${addrDataWidth}_t;

    using addr_t = uint${addrDataWidth}_t;

@ -133,17 +109,22 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {

    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+        {${getRegisterSizes().join(',')}}};

-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+        {${getRegisterOffsets().join(',')}}};

    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

    enum sreg_flag_e { FLAGS };

-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    
+    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+        ${instr.instruction.name} = ${index},<%}%>
+        MAX_OPCODE
+    };
 };

 struct ${coreDef.name.toLowerCase()}: public arch_if {
@ -189,32 +170,29 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
    inline uint32_t get_last_branch() { return reg.last_branch; }

 protected:
+#pragma pack(push, 1)
    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        registers.each { reg -> if(reg.size>0) {%> 
+        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
+        }}%>
+        uint32_t trap_state = 0, pending_trap = 0;
        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t last_branch;
    } reg;
-
+#pragma pack(pop)
    std::array<address_type, 4> addr_mode;
    
    uint64_t interrupt_sim=0;
 <%
-def fcsr = allRegs.find {it.name=='FCSR'}
+def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+    uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
+    void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}      
 <%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
 <%}%>
 };

--- a/gen_input/templates/interp/CORENAME_cyles.txt.gtl
+++ b/gen_input/templates/interp/CORENAME_cyles.txt.gtl
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@ -0,0 +1,342 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include "../fp_functions.h"
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/interp/vm_base.h>
+#include <util/logging.h>
+#include <sstream>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace interp {
+namespace ${coreDef.name.toLowerCase()} {
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super       = typename iss::interp::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t      = typename super::addr_t;
+    using reg_t       = typename traits::reg_t;
+    using mem_type_e  = typename traits::mem_type_e;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (super::tgt_adapter == nullptr)
+            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return super::tgt_adapter;
+    }
+
+protected:
+    using this_class = vm_impl<ARCH>;
+    using compile_ret_t = virt_addr_t;
+    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
+
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    compile_func decode_inst(code_word_t instr) ;
+    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
+
+    // some compile time constants
+    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
+    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
+    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+
+    std::array<compile_func, LUT_SIZE> lut;
+
+    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+    std::array<compile_func, LUT_SIZE> lut_11;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        compile_func opc;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    inline void raise(uint16_t trap_id, uint16_t cause){
+        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
+        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
+        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+    }
+
+    inline void leave(unsigned lvl){
+        this->core.leave_trap(lvl);
+    }
+
+    inline void wait(unsigned type){
+        this->core.wait_until(type);
+    }
+
+    template<typename T>
+    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
+    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint8_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint16_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint32_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint64_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct InstructionDesriptor {
+        size_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name} */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */
+            <%instr.disass.eachLine{%>${it}
+            <%}%>
+        }
+        // used registers<%instr.usedVariables.each{ k,v->
+            if(v.isArray) {%>
+        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+        <%}}%>// calculate next pc value
+        *NEXT_PC = *PC + ${instr.length/8};
+        // execute instruction
+        try {
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>} catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
+        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
+        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+        raise(0,  2);
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        }
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+
+    static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
+    iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
+        auto phys_pc = this->core.v2p(pc);
+        //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+        //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
+        //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
+        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
+        //} else {
+            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
+        //}
+        return iss::Ok;
+    }
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+    volatile CODE_WORD x = insn;
+    insn = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id) {
+    for (auto instr : instr_descr) {
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
+    }
+}
+
+inline bool is_count_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
+}
+
+inline bool is_jump_to_self_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
+}
+
+template <typename ARCH>
+typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.opc;
+    }
+    return &this_class::illegal_intruction;
+}
+
+template <typename ARCH>
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
+    // we fetch at max 4 byte, alignment is 2
+    code_word_t insn = 0;
+    auto *const data = (uint8_t *)&insn;
+    auto pc=start;
+    while(!this->core.should_stop() &&
+            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
+        auto res = fetch_ins(pc, data);
+        if(res!=iss::Ok){
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+        } else {
+            if (is_jump_to_self_enabled(cond) &&
+                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto f = decode_inst(insn);
+            pc = (this->*f)(pc, insn);
+        }
+    }
+    return pc;
+}
+
+} // namespace mnrv32
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace interp
+} // namespace iss
--- a/gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
@ -1,247 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2020 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include "../fp_functions.h"
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/interp/vm_base.h>
-#include <util/logging.h>
-#include <sstream>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace interp {
-namespace ${coreDef.name.toLowerCase()} {
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
-public:
-    using super = typename iss::interp::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-    using reg_t = typename traits<ARCH>::reg_t;
-    using iss::interp::vm_base<ARCH>::get_reg;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (super::tgt_adapter == nullptr)
-            super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return super::tgt_adapter;
-    }
-
-protected:
-    using this_class = vm_impl<ARCH>;
-    using compile_ret_t = virt_addr_t;
-    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
-
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
-
-    virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
-
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    std::array<compile_func *, 4> qlut;
-
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
-
-    void raise_trap(uint16_t trap_id, uint16_t cause){
-        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
-    }
-
-    void leave_trap(unsigned lvl){
-        this->core.leave_trap(lvl);
-        auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
-        this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
-    }
-
-    void wait(unsigned type){
-        this->core.wait_until(type);
-    }
-
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
-        ${it}<%}%>
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        return pc;
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
-    auto pc=start;
-    while(pred){
-        auto paddr = this->core.v2p(pc);
-        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-            if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-            if ((insn & 0x3) == 0x3) // this is a 32bit instruction
-                if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        } else {
-            if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        }
-        if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-        auto lut_val = extract_fields(insn);
-        auto f = qlut[insn & 0x3][lut_val];
-        if (!f)
-            f = &this_class::illegal_intruction;
-        pc = (this->*f)(pc, insn);
-    }
-    return pc;
-}
-
-} // namespace mnrv32
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace interp
-} // namespace iss
--- a/incl/iss/arch/.gitignore
+++ b/incl/iss/arch/.gitignore
@ -0,0 +1 @@
+/tgc_*.h
--- a/incl/iss/arch/riscv_hart_common.h
+++ b/incl/iss/arch/riscv_hart_common.h
@ -0,0 +1,242 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_COMMON
+#define _RISCV_HART_COMMON
+
+#include "iss/arch_if.h"
+#include <cstdint>
+
+namespace iss {
+namespace arch {
+
+enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
+
+enum riscv_csr {
+    /* user-level CSR */
+    // User Trap Setup
+    ustatus = 0x000,
+    uie = 0x004,
+    utvec = 0x005,
+    // User Trap Handling
+    uscratch = 0x040,
+    uepc = 0x041,
+    ucause = 0x042,
+    utval = 0x043,
+    uip = 0x044,
+    // User Floating-Point CSRs
+    fflags = 0x001,
+    frm = 0x002,
+    fcsr = 0x003,
+    // User Counter/Timers
+    cycle = 0xC00,
+    time = 0xC01,
+    instret = 0xC02,
+    hpmcounter3 = 0xC03,
+    hpmcounter4 = 0xC04,
+    /*...*/
+    hpmcounter31 = 0xC1F,
+    cycleh = 0xC80,
+    timeh = 0xC81,
+    instreth = 0xC82,
+    hpmcounter3h = 0xC83,
+    hpmcounter4h = 0xC84,
+    /*...*/
+    hpmcounter31h = 0xC9F,
+    /* supervisor-level CSR */
+    // Supervisor Trap Setup
+    sstatus = 0x100,
+    sedeleg = 0x102,
+    sideleg = 0x103,
+    sie = 0x104,
+    stvec = 0x105,
+    scounteren = 0x106,
+    // Supervisor Trap Handling
+    sscratch = 0x140,
+    sepc = 0x141,
+    scause = 0x142,
+    stval = 0x143,
+    sip = 0x144,
+    // Supervisor Protection and Translation
+    satp = 0x180,
+    /* machine-level CSR */
+    // Machine Information Registers
+    mvendorid = 0xF11,
+    marchid = 0xF12,
+    mimpid = 0xF13,
+    mhartid = 0xF14,
+    // Machine Trap Setup
+    mstatus = 0x300,
+    misa = 0x301,
+    medeleg = 0x302,
+    mideleg = 0x303,
+    mie = 0x304,
+    mtvec = 0x305,
+    mcounteren = 0x306,
+    mtvt = 0x307, //CLIC
+    // Machine Trap Handling
+    mscratch = 0x340,
+    mepc = 0x341,
+    mcause = 0x342,
+    mtval = 0x343,
+    mip = 0x344,
+    mxnti = 0x345, //CLIC
+    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
+    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
+    // Physical Memory Protection
+    pmpcfg0 = 0x3A0,
+    pmpcfg1 = 0x3A1,
+    pmpcfg2 = 0x3A2,
+    pmpcfg3 = 0x3A3,
+    pmpaddr0 = 0x3B0,
+    pmpaddr1 = 0x3B1,
+    pmpaddr2 = 0x3B2,
+    pmpaddr3 = 0x3B3,
+    pmpaddr4 = 0x3B4,
+    pmpaddr5 = 0x3B5,
+    pmpaddr6 = 0x3B6,
+    pmpaddr7 = 0x3B7,
+    pmpaddr8 = 0x3B8,
+    pmpaddr9 = 0x3B9,
+    pmpaddr10 = 0x3BA,
+    pmpaddr11 = 0x3BB,
+    pmpaddr12 = 0x3BC,
+    pmpaddr13 = 0x3BD,
+    pmpaddr14 = 0x3BE,
+    pmpaddr15 = 0x3BF,
+    // Machine Counter/Timers
+    mcycle = 0xB00,
+    minstret = 0xB02,
+    mhpmcounter3 = 0xB03,
+    mhpmcounter4 = 0xB04,
+    /*...*/
+    mhpmcounter31 = 0xB1F,
+    mcycleh = 0xB80,
+    minstreth = 0xB82,
+    mhpmcounter3h = 0xB83,
+    mhpmcounter4h = 0xB84,
+    /*...*/
+    mhpmcounter31h = 0xB9F,
+    // Machine Counter Setup
+    mhpmevent3 = 0x323,
+    mhpmevent4 = 0x324,
+    /*...*/
+    mhpmevent31 = 0x33F,
+    // Debug/Trace Registers (shared with Debug Mode)
+    tselect = 0x7A0,
+    tdata1 = 0x7A1,
+    tdata2 = 0x7A2,
+    tdata3 = 0x7A3,
+    // Debug Mode Registers
+    dcsr = 0x7B0,
+    dpc = 0x7B1,
+    dscratch = 0x7B2
+};
+
+
+enum {
+    PGSHIFT = 12,
+    PTE_PPN_SHIFT = 10,
+    // page table entry (PTE) fields
+    PTE_V = 0x001,   // Valid
+    PTE_R = 0x002,   // Read
+    PTE_W = 0x004,   // Write
+    PTE_X = 0x008,   // Execute
+    PTE_U = 0x010,   // User
+    PTE_G = 0x020,   // Global
+    PTE_A = 0x040,   // Accessed
+    PTE_D = 0x080,   // Dirty
+    PTE_SOFT = 0x300 // Reserved for Software
+};
+
+template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
+
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
+
+enum {
+    ISA_A = 1,
+    ISA_B = 1 << 1,
+    ISA_C = 1 << 2,
+    ISA_D = 1 << 3,
+    ISA_E = 1 << 4,
+    ISA_F = 1 << 5,
+    ISA_G = 1 << 6,
+    ISA_I = 1 << 8,
+    ISA_M = 1 << 12,
+    ISA_N = 1 << 13,
+    ISA_Q = 1 << 16,
+    ISA_S = 1 << 18,
+    ISA_U = 1 << 20
+};
+
+struct vm_info {
+    int levels;
+    int idxbits;
+    int ptesize;
+    uint64_t ptbase;
+    bool is_active() { return levels; }
+};
+
+class trap_load_access_fault : public trap_access {
+public:
+    trap_load_access_fault(uint64_t badaddr)
+    : trap_access(5 << 16, badaddr) {}
+};
+class illegal_instruction_fault : public trap_access {
+public:
+    illegal_instruction_fault(uint64_t badaddr)
+    : trap_access(2 << 16, badaddr) {}
+};
+class trap_instruction_page_fault : public trap_access {
+public:
+    trap_instruction_page_fault(uint64_t badaddr)
+    : trap_access(12 << 16, badaddr) {}
+};
+class trap_load_page_fault : public trap_access {
+public:
+    trap_load_page_fault(uint64_t badaddr)
+    : trap_access(13 << 16, badaddr) {}
+};
+class trap_store_page_fault : public trap_access {
+public:
+    trap_store_page_fault(uint64_t badaddr)
+    : trap_access(15 << 16, badaddr) {}
+};
+}
+}
+
+#endif
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2021 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -32,11 +32,11 @@
 *       eyck@minres.com - initial implementation
 ******************************************************************************/

-#ifndef _RISCV_CORE_H_
-#define _RISCV_CORE_H_
+#ifndef _RISCV_HART_M_P_H
+#define _RISCV_HART_M_P_H

+#include "riscv_hart_common.h"
 #include "iss/arch/traits.h"
-#include "iss/arch_if.h"
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
@ -50,6 +50,7 @@
 #include <sstream>
 #include <type_traits>
 #include <unordered_map>
+#include <functional>
 #include <util/bit_field.h>
 #include <util/ities.h>
 #include <util/sparse_array.h>
@ -65,191 +66,36 @@
 namespace iss {
 namespace arch {

-enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
-
-enum riscv_csr {
-    /* user-level CSR */
-    // User Trap Setup
-    ustatus = 0x000,
-    uie = 0x004,
-    utvec = 0x005,
-    // User Trap Handling
-    uscratch = 0x040,
-    uepc = 0x041,
-    ucause = 0x042,
-    utval = 0x043,
-    uip = 0x044,
-    // User Floating-Point CSRs
-    fflags = 0x001,
-    frm = 0x002,
-    fcsr = 0x003,
-    // User Counter/Timers
-    cycle = 0xC00,
-    time = 0xC01,
-    instret = 0xC02,
-    hpmcounter3 = 0xC03,
-    hpmcounter4 = 0xC04,
-    /*...*/
-    hpmcounter31 = 0xC1F,
-    cycleh = 0xC80,
-    timeh = 0xC81,
-    instreth = 0xC82,
-    hpmcounter3h = 0xC83,
-    hpmcounter4h = 0xC84,
-    /*...*/
-    hpmcounter31h = 0xC9F,
-    /* supervisor-level CSR */
-    // Supervisor Trap Setup
-    sstatus = 0x100,
-    sedeleg = 0x102,
-    sideleg = 0x103,
-    sie = 0x104,
-    stvec = 0x105,
-    scounteren = 0x106,
-    // Supervisor Trap Handling
-    sscratch = 0x140,
-    sepc = 0x141,
-    scause = 0x142,
-    stval = 0x143,
-    sip = 0x144,
-    // Supervisor Protection and Translation
-    satp = 0x180,
-    /* machine-level CSR */
-    // Machine Information Registers
-    mvendorid = 0xF11,
-    marchid = 0xF12,
-    mimpid = 0xF13,
-    mhartid = 0xF14,
-    // Machine Trap Setup
-    mstatus = 0x300,
-    misa = 0x301,
-    medeleg = 0x302,
-    mideleg = 0x303,
-    mie = 0x304,
-    mtvec = 0x305,
-    mcounteren = 0x306,
-    // Machine Trap Handling
-    mscratch = 0x340,
-    mepc = 0x341,
-    mcause = 0x342,
-    mtval = 0x343,
-    mip = 0x344,
-    // Machine Protection and Translation
-    pmpcfg0 = 0x3A0,
-    pmpcfg1 = 0x3A1,
-    pmpcfg2 = 0x3A2,
-    pmpcfg3 = 0x3A3,
-    pmpaddr0 = 0x3B0,
-    pmpaddr1 = 0x3B1,
-    /*...*/
-    pmpaddr15 = 0x3BF,
-    // Machine Counter/Timers
-    mcycle = 0xB00,
-    minstret = 0xB02,
-    mhpmcounter3 = 0xB03,
-    mhpmcounter4 = 0xB04,
-    /*...*/
-    mhpmcounter31 = 0xB1F,
-    mcycleh = 0xB80,
-    minstreth = 0xB82,
-    mhpmcounter3h = 0xB83,
-    mhpmcounter4h = 0xB84,
-    /*...*/
-    mhpmcounter31h = 0xB9F,
-    // Machine Counter Setup
-    mhpmevent3 = 0x323,
-    mhpmevent4 = 0x324,
-    /*...*/
-    mhpmevent31 = 0x33F,
-    // Debug/Trace Registers (shared with Debug Mode)
-    tselect = 0x7A0,
-    tdata1 = 0x7A1,
-    tdata2 = 0x7A2,
-    tdata3 = 0x7A3,
-    // Debug Mode Registers
-    dcsr = 0x7B0,
-    dpc = 0x7B1,
-    dscratch = 0x7B2
-};
-
-namespace {
-
-std::array<const char *, 16> trap_str = {{""
-                                          "Instruction address misaligned", // 0
-                                          "Instruction access fault",       // 1
-                                          "Illegal instruction",            // 2
-                                          "Breakpoint",                     // 3
-                                          "Load address misaligned",        // 4
-                                          "Load access fault",              // 5
-                                          "Store/AMO address misaligned",   // 6
-                                          "Store/AMO access fault",         // 7
-                                          "Environment call from U-mode",   // 8
-                                          "Environment call from S-mode",   // 9
-                                          "Reserved",                       // a
-                                          "Environment call from M-mode",   // b
-                                          "Instruction page fault",         // c
-                                          "Load page fault",                // d
-                                          "Reserved",                       // e
-                                          "Store/AMO page fault"}};
-std::array<const char *, 12> irq_str = {
-    {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-     "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
-     "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-
-enum {
-    PGSHIFT = 12,
-    PTE_PPN_SHIFT = 10,
-    // page table entry (PTE) fields
-    PTE_V = 0x001,   // Valid
-    PTE_R = 0x002,   // Read
-    PTE_W = 0x004,   // Write
-    PTE_X = 0x008,   // Execute
-    PTE_U = 0x010,   // User
-    PTE_G = 0x020,   // Global
-    PTE_A = 0x040,   // Accessed
-    PTE_D = 0x080,   // Dirty
-    PTE_SOFT = 0x300 // Reserved for Software
-};
-
-template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
-
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
-
-enum {
-    ISA_A = 1,
-    ISA_B = 1 << 1,
-    ISA_C = 1 << 2,
-    ISA_D = 1 << 3,
-    ISA_E = 1 << 4,
-    ISA_F = 1 << 5,
-    ISA_G = 1 << 6,
-    ISA_I = 1 << 8,
-    ISA_M = 1 << 12,
-    ISA_N = 1 << 13,
-    ISA_Q = 1 << 16,
-    ISA_S = 1 << 18,
-    ISA_U = 1 << 20
-};
-
-class trap_load_access_fault : public trap_access {
-public:
-    trap_load_access_fault(uint64_t badaddr)
-    : trap_access(5 << 16, badaddr) {}
-};
-class illegal_instruction_fault : public trap_access {
-public:
-    illegal_instruction_fault(uint64_t badaddr)
-    : trap_access(2 << 16, badaddr) {}
-};
-} // namespace
-
 template <typename BASE> class riscv_hart_m_p : public BASE {
+protected:
+    const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
+    const std::array<const char *, 16> trap_str = {{""
+                                              "Instruction address misaligned", // 0
+                                              "Instruction access fault",       // 1
+                                              "Illegal instruction",            // 2
+                                              "Breakpoint",                     // 3
+                                              "Load address misaligned",        // 4
+                                              "Load access fault",              // 5
+                                              "Store/AMO address misaligned",   // 6
+                                              "Store/AMO access fault",         // 7
+                                              "Environment call from U-mode",   // 8
+                                              "Environment call from S-mode",   // 9
+                                              "Reserved",                       // a
+                                              "Environment call from M-mode",   // b
+                                              "Instruction page fault",         // c
+                                              "Load page fault",                // d
+                                              "Reserved",                       // e
+                                              "Store/AMO page fault"}};
+    const std::array<const char *, 12> irq_str = {
+        {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
+         "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
+         "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
 public:
-    using super = BASE;
+    using core = BASE;
    using this_class = riscv_hart_m_p<BASE>;
-    using phys_addr_t = typename super::phys_addr_t;
-    using reg_t = typename super::reg_t;
-    using addr_t = typename super::addr_t;
+    using phys_addr_t = typename core::phys_addr_t;
+    using reg_t = typename core::reg_t;
+    using addr_t = typename core::addr_t;

    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
@ -298,25 +144,40 @@ public:

        mstatus_t mstatus;

-        static const reg_t mstatus_reset_val = 0;
+        static const reg_t mstatus_reset_val = 0x1800;

        void write_mstatus(T val) {
-            auto mask = get_mask();
+            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
            mstatus = new_val;
        }

-        T satp;
-
-        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
-
        static constexpr uint32_t get_mask() {
-            return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
+            //return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
+            //       +-SD
+            //       |        +-TSR
+            //       |        |+-TW
+            //       |        ||+-TVM
+            //       |        |||+-MXR
+            //       |        ||||+-SUM
+            //       |        |||||+-MPRV
+            //       |        |||||| +-XS
+            //       |        |||||| | +-FS
+            //       |        |||||| | | +-MPP
+            //       |        |||||| | | |  +-SPP
+            //       |        |||||| | | |  |+-MPIE
+            //       |        ||||||/|/|/|  ||   +-MIE
+            return 0b00000000000000000001100010001000;
        }
    };
+    using hart_state_type = hart_state<reg_t>;

    constexpr reg_t get_irq_mask() {
-        return 0b101110111011; // only machine mode is supported
+        return 0b100010001000; // only machine mode is supported
+    }
+
+    constexpr reg_t get_pc_mask() {
+        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
    }

    riscv_hart_m_p();
@ -331,8 +192,8 @@ public:
    iss::status write(const address_type type, const access_type access, const uint32_t space,
            const uint64_t addr, const unsigned length, const uint8_t *const data) override;

-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
+    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
+    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
    virtual uint64_t leave_trap(uint64_t flags) override;

    const reg_t& get_mhartid() const { return mhartid_reg;	}
@ -344,7 +205,19 @@ public:
    };

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
- 
+
+    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
+        mem_read_cb = memReadCb;
+    }
+
+    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
+        mem_write_cb = memWriteCb;
+    }
+
+    void set_csr(unsigned addr, reg_t val){
+        csr[addr & csr.page_addr_mask] = val;
+    }
+
 protected:
    struct riscv_instrumentation_if : public iss::instrumentation_if {

@ -376,8 +249,11 @@ protected:
    virtual iss::status read_csr(unsigned addr, reg_t &val);
    virtual iss::status write_csr(unsigned addr, reg_t val);

-    hart_state<reg_t> state;
-    uint64_t cycle_offset;
+    hart_state_type state;
+    int64_t cycle_offset{0};
+    uint64_t mcycle_csr{0};
+    int64_t instret_offset{0};
+    uint64_t minstret_csr{0};
    reg_t fault_data;
    uint64_t tohost = tohost_dflt;
    uint64_t fromhost = fromhost_dflt;
@ -396,17 +272,29 @@ protected:
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;

 private:
+    iss::status read_reg(unsigned addr, reg_t &val);
+    iss::status write_reg(unsigned addr, reg_t val);
+    iss::status read_null(unsigned addr, reg_t &val);
+    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
    iss::status read_cycle(unsigned addr, reg_t &val);
+    iss::status write_cycle(unsigned addr, reg_t val);
+    iss::status read_instret(unsigned addr, reg_t &val);
+    iss::status write_instret(unsigned addr, reg_t val);
+    iss::status read_tvec(unsigned addr, reg_t &val);
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
    iss::status write_ip(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
+    iss::status write_epc(unsigned addr, reg_t val);

-    reg_t mhartid_reg{0xF};
+    reg_t mhartid_reg{0x0};
+    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
+    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;

 protected:
    void check_interrupt();
@ -415,30 +303,71 @@ protected:
 template <typename BASE>
 riscv_hart_m_p<BASE>::riscv_hart_m_p()
 : state()
-, cycle_offset(0)
 , instr_if(*this) {
-    csr[misa] = hart_state<reg_t>::get_misa();
+    // reset values
+    csr[misa] = traits<BASE>::MISA_VAL;
+    csr[mvendorid] = 0x669;
+    csr[marchid] = 0x80000003;
+    csr[mimpid] = 1;
+
    uart_buf.str("");
-    // read-only registers
-    csr_wr_cb[misa] = nullptr;
-    for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
-    for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
-    // special handling
-    csr_rd_cb[time] = &riscv_hart_m_p<BASE>::read_time;
-    csr_wr_cb[time] = nullptr;
-    csr_rd_cb[timeh] = &riscv_hart_m_p<BASE>::read_time;
-    csr_wr_cb[timeh] = nullptr;
-    csr_rd_cb[mcycle] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[mcycleh] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[minstret] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[minstreth] = &riscv_hart_m_p<BASE>::read_cycle;
-    csr_rd_cb[mstatus] = &riscv_hart_m_p<BASE>::read_status;
-    csr_wr_cb[mstatus] = &riscv_hart_m_p<BASE>::write_status;
-    csr_rd_cb[mip] = &riscv_hart_m_p<BASE>::read_ip;
-    csr_wr_cb[mip] = &riscv_hart_m_p<BASE>::write_ip;
-    csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
-    csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
-    csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
+    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
+        csr_rd_cb[addr] = &this_class::read_null;
+        csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+        csr_rd_cb[addr] = &this_class::read_null;
+        csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
+        csr_rd_cb[addr] = &this_class::read_null;
+        csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
+        csr_rd_cb[addr] = &this_class::read_null;
+    }
+    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+        csr_rd_cb[addr] = &this_class::read_null;
+        //csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    // common regs
+    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
+    for(auto addr: addrs) {
+        csr_rd_cb[addr] = &this_class::read_reg;
+        csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    // special handling & overrides
+    csr_rd_cb[time] = &this_class::read_time;
+    csr_rd_cb[timeh] = &this_class::read_time;
+    csr_rd_cb[cycle] = &this_class::read_cycle;
+    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    csr_rd_cb[instret] = &this_class::read_instret;
+    csr_rd_cb[instreth] = &this_class::read_instret;
+
+    csr_rd_cb[mcycle] = &this_class::read_cycle;
+    csr_wr_cb[mcycle] = &this_class::write_cycle;
+    csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    csr_rd_cb[minstret] = &this_class::read_instret;
+    csr_wr_cb[minstret] = &this_class::write_instret;
+    csr_rd_cb[minstreth] = &this_class::read_instret;
+    csr_wr_cb[minstreth] = &this_class::write_instret;
+    csr_rd_cb[mstatus] = &this_class::read_status;
+    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
+    csr_rd_cb[mip] = &this_class::read_ip;
+    csr_wr_cb[mip] = &this_class::write_ip;
+    csr_rd_cb[mie] = &this_class::read_ie;
+    csr_wr_cb[mie] = &this_class::write_ie;
+    csr_rd_cb[mhartid] = &this_class::read_hartid;
+    csr_rd_cb[mcounteren] = &this_class::read_null;
+    csr_wr_cb[mcounteren] = &this_class::write_null;
+    csr_wr_cb[misa] = &this_class::write_null;
+    csr_wr_cb[mvendorid] = &this_class::write_null;
+    csr_wr_cb[marchid] = &this_class::write_null;
+    csr_wr_cb[mimpid] = &this_class::write_null;
 }

 template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
@ -459,6 +388,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
            if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
            if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
            for (const auto pseg : reader.segments) {
                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                const auto seg_data = pseg->get_data();
@ -467,18 +397,39 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                            traits<BASE>::MEM, pseg->get_physical_address(),
                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                    if (res != iss::Ok)
-                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
                                   << pseg->get_physical_address();
                }
            }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                    tohost = sec->get_address();
                    fromhost = tohost + 0x40;
                }
-            }

-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
        }
        throw std::runtime_error("memory load file is not a valid elf file");
    }
@ -507,13 +458,23 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
                return iss::Err;
            }
            try {
+                auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+                if(alignment>1 && (addr&(alignment-1))){
+                    this->reg.trap_state = 1<<31 | 4<<16;
+                    fault_data=addr;
+                    return iss::Err;
+                }
                auto res = type==iss::address_type::PHYSICAL?
                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                if (unlikely(res != iss::Ok)){
+                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    fault_data=addr;
+                }
                return res;
            } catch (trap_access &ta) {
                this->reg.trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                return iss::Err;
            }
        } break;
@ -539,6 +500,7 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
        return iss::Ok;
    } catch (trap_access &ta) {
        this->reg.trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
        return iss::Err;
    }
 }
@ -579,14 +541,22 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
                return iss::Err;
            }
            try {
+                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
+                    this->reg.trap_state = 1<<31 | 6<<16;
+                    fault_data=addr;
+                    return iss::Err;
+                }
                auto res = type==iss::address_type::PHYSICAL?
                        write_mem(phys_addr_t{access, space, addr}, length, data):
                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok))
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
+                if (unlikely(res != iss::Ok)) {
+                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    fault_data=addr;
+                }
                return res;
            } catch (trap_access &ta) {
                this->reg.trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                return iss::Err;
            }

@ -646,6 +616,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
        return iss::Ok;
    } catch (trap_access &ta) {
        this->reg.trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
        return iss::Err;
    }
 }
@ -653,32 +624,40 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
    if (addr >= csr.size()) return iss::Err;
    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
+    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
+        throw illegal_instruction_fault(this->fault_data);
    auto it = csr_rd_cb.find(addr);
-    if (it == csr_rd_cb.end()) {
-        val = csr[addr & csr.page_addr_mask];
-        return iss::Ok;
-    }
-    rd_csr_f f = it->second;
-    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
-    return (this->*f)(addr, val);
+    if (it == csr_rd_cb.end() || !it->second) // non existent register
+        throw illegal_instruction_fault(this->fault_data);
+    return (this->*(it->second))(addr, val);
 }

 template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
    if (addr >= csr.size()) return iss::Err;
    auto req_priv_lvl = (addr >> 8) & 0x3;
-    if (this->reg.machine_state < req_priv_lvl)
+    if (this->reg.PRIV < req_priv_lvl) // not having required privileges
        throw illegal_instruction_fault(this->fault_data);
-    if((addr&0xc00)==0xc00)
+    if((addr&0xc00)==0xc00) // writing to read-only region
        throw illegal_instruction_fault(this->fault_data);
    auto it = csr_wr_cb.find(addr);
-    if (it == csr_wr_cb.end()) {
-        csr[addr & csr.page_addr_mask] = val;
-        return iss::Ok;
-    }
-    wr_csr_f f = it->second;
-    if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
-    return (this->*f)(addr, val);
+    if (it == csr_wr_cb.end() || !it->second) // non existent register
+        throw illegal_instruction_fault(this->fault_data);
+    return (this->*(it->second))(addr, val);
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
+    val = csr[addr];
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
+    val = 0;
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
+    csr[addr] = val;
+    return iss::Ok;
 }

 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
@ -692,8 +671,50 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
+    if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if (addr == mcycleh)
+            return iss::Err;
+        mcycle_csr = static_cast<uint64_t>(val);
+    } else {
+        if (addr == mcycle) {
+            mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
+        } else  {
+            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
+        }
+    }
+    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
+    if ((addr&0xff) == (minstret&0xff)) {
+        val = static_cast<reg_t>(this->reg.instret);
+    } else if ((addr&0xff) == (minstreth&0xff)) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
+        val = static_cast<reg_t>(this->reg.instret >> 32);
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
+    if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if ((addr&0xff) == (minstreth&0xff))
+            return iss::Err;
+        this->reg.instret = static_cast<uint64_t>(val);
+    } else {
+        if ((addr&0xff) == (minstret&0xff)) {
+            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
+        } else  {
+            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
+        }
+    }
+    this->reg.instret--;
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
    if (addr == time) {
        val = static_cast<reg_t>(time_val);
    } else if (addr == timeh) {
@ -703,8 +724,13 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
+    val = csr[mtvec] & ~2;
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
-    val = state.mstatus & hart_state<reg_t>::get_mask();
+    val = state.mstatus & hart_state_type::get_mask();
    return iss::Ok;
 }

@ -714,9 +740,13 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
+    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
    val = csr[mie];
-    val &= csr[mideleg];
    return iss::Ok;
 }

@ -734,7 +764,6 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned add

 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
    val = csr[mip];
-    val &= csr[mideleg];
    return iss::Ok;
 }

@ -746,9 +775,14 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned add
    return iss::Ok;
 }

+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
+    csr[addr] = val & get_pc_mask();
+    return iss::Ok;
+}
+
 template <typename BASE>
 iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
+    if(mem_read_cb) return mem_read_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x0200BFF8: { // CLINT base, mtime reg
        if (sizeof(reg_t) < length) return iss::Err;
@ -763,9 +797,9 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
        if (this->reg.icount > 30000) data[3] |= 0x80;
    } break;
    default: {
-        const auto &p = mem(paddr.val / mem.page_size);
-        auto offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
+        for(auto offs=0U; offs<length; ++offs) {
+            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
+        }
    }
    }
    return iss::Ok;
@ -773,7 +807,7 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u

 template <typename BASE>
 iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
+    if(mem_write_cb) return mem_write_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x10013000: // UART0 base, TXFIFO reg
    case 0x10023000: // UART1 base, TXFIFO reg
@ -804,9 +838,10 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
        // tohost handling in case of riscv-test
        if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4));
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
            auto tohost_lower =
-                (traits<BASE>::XLEN == 32 && paddr.val == tohost);
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
            if (tohost_lower || tohost_upper) {
                uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
                if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
@ -837,7 +872,8 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
                    }
                } else if (tohost_lower)
                    to_host_wr_cnt++;
-            } else if (traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
            }
@ -849,11 +885,11 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,

 template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
    BASE::reset(address);
-    state.mstatus = hart_state<reg_t>::mstatus_reset_val;
+    state.mstatus = hart_state_type::mstatus_reset_val;
 }

 template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
-    auto ideleg = csr[mideleg];
+    //auto ideleg = csr[mideleg];
    // Multiple simultaneous interrupts and traps at the same privilege level are
    // handled in the following decreasing priority order:
    // external interrupts, software interrupts, timer interrupts, then finally
@ -861,17 +897,20 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
    auto ena_irq = csr[mip] & csr[mie];

    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
-    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
+    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
+    auto enabled_interrupts = m_enabled ? ena_irq : 0;

    if (enabled_interrupts != 0) {
        int res = 0;
-        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
+        while ((enabled_interrupts & 1) == 0) {
+        	enabled_interrupts >>= 1;
+        	res++;
+        }
        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
    }
 }

-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
+template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
    auto trap_id = bit_sub<0, 16>(flags);
@ -880,11 +919,11 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
    // calculate effective privilege level
    if (trap_id == 0) { // exception
        // store ret addr in xepc register
-        csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
-        csr[mtval] = fault_data;
+        csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
+        csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
        fault_data = 0;
    } else {
-        csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
+        csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
        this->reg.pending_trap = 0;
    }
    csr[mcause] = (trap_id << 31) + cause;
@ -903,13 +942,17 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
    auto ivec = csr[mtvec];
    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x1UL;
+    this->reg.NEXT_PC = ivec & ~0x3UL;
    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
    // reset trap state
-    this->reg.machine_state = PRIV_M;
+    this->reg.PRIV = PRIV_M;
    this->reg.trap_state = 0;
    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+    sprintf(buffer.data(), "0x%016llx", addr);
+#else
    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
    if((flags&0xffffffff) != 0xffffffff)
    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
@ -918,27 +961,16 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
 }

 template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    auto cur_priv = this->reg.machine_state;
-    auto inst_priv = flags & 0x3;
-    auto status = state.mstatus;
-
-    // pop the relevant lower-privilege interrupt enable and privilege mode stack
-    // clear respective yIE
-    if (inst_priv == PRIV_M) {
-        this->reg.machine_state = state.mstatus.MPP;
-        state.mstatus.MPP = 0; // clear mpp to U mode
-        state.mstatus.MIE = state.mstatus.MPIE;
-    } else {
-    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
-    }
-
+    state.mstatus.MIE = state.mstatus.MPIE;
+    state.mstatus.MPIE = 1;
    // sets the pc to the value stored in the x epc register.
-    this->reg.NEXT_PC = csr[mepc];
+    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
    CLOG(INFO, disass) << "Executing xRET";
+    check_interrupt();
    return this->reg.NEXT_PC;
 }

 } // namespace arch
 } // namespace iss

-#endif /* _RISCV_CORE_H_ */
+#endif /* _RISCV_HART_M_P_H */
--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
--- a/incl/iss/arch/tgc_c.h
+++ b/incl/iss/arch/tgc_c.h
@ -0,0 +1,282 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _TGC_C_H_
+#define _TGC_C_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct tgc_c;
+
+template <> struct traits<tgc_c> {
+
+    constexpr static char const* const core_type = "TGC_C";
+    
+    static constexpr std::array<const char*, 35> reg_names{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+ 
+    static constexpr std::array<const char*, 35> reg_aliases{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
+
+    constexpr static unsigned FP_REGS_SIZE = 0;
+
+    enum reg_e {
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
+        TRAP_STATE=NUM_REGS,
+        PENDING_TRAP,
+        ICOUNT,
+        CYCLE,
+        INSTRET
+    };
+
+    using reg_t = uint32_t;
+
+    using addr_t = uint32_t;
+
+    using code_word_t = uint32_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}};
+
+    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { MEM, CSR, FENCE, RES };
+    
+    enum class opcode_e : unsigned short {
+        LUI = 0,
+        AUIPC = 1,
+        JAL = 2,
+        JALR = 3,
+        BEQ = 4,
+        BNE = 5,
+        BLT = 6,
+        BGE = 7,
+        BLTU = 8,
+        BGEU = 9,
+        LB = 10,
+        LH = 11,
+        LW = 12,
+        LBU = 13,
+        LHU = 14,
+        SB = 15,
+        SH = 16,
+        SW = 17,
+        ADDI = 18,
+        SLTI = 19,
+        SLTIU = 20,
+        XORI = 21,
+        ORI = 22,
+        ANDI = 23,
+        SLLI = 24,
+        SRLI = 25,
+        SRAI = 26,
+        ADD = 27,
+        SUB = 28,
+        SLL = 29,
+        SLT = 30,
+        SLTU = 31,
+        XOR = 32,
+        SRL = 33,
+        SRA = 34,
+        OR = 35,
+        AND = 36,
+        FENCE = 37,
+        ECALL = 38,
+        EBREAK = 39,
+        URET = 40,
+        SRET = 41,
+        MRET = 42,
+        WFI = 43,
+        CSRRW = 44,
+        CSRRS = 45,
+        CSRRC = 46,
+        CSRRWI = 47,
+        CSRRSI = 48,
+        CSRRCI = 49,
+        MUL = 50,
+        MULH = 51,
+        MULHSU = 52,
+        MULHU = 53,
+        DIV = 54,
+        DIVU = 55,
+        REM = 56,
+        REMU = 57,
+        CADDI4SPN = 58,
+        CLW = 59,
+        CSW = 60,
+        CADDI = 61,
+        CNOP = 62,
+        CJAL = 63,
+        CLI = 64,
+        CLUI = 65,
+        CADDI16SP = 66,
+        __reserved_clui = 67,
+        CSRLI = 68,
+        CSRAI = 69,
+        CANDI = 70,
+        CSUB = 71,
+        CXOR = 72,
+        COR = 73,
+        CAND = 74,
+        CJ = 75,
+        CBEQZ = 76,
+        CBNEZ = 77,
+        CSLLI = 78,
+        CLWSP = 79,
+        CMV = 80,
+        CJR = 81,
+        __reserved_cmv = 82,
+        CADD = 83,
+        CJALR = 84,
+        CEBREAK = 85,
+        CSWSP = 86,
+        DII = 87,
+        MAX_OPCODE
+    };
+};
+
+struct tgc_c: public arch_if {
+
+    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
+    using reg_t =  typename traits<tgc_c>::reg_t;
+    using addr_t = typename traits<tgc_c>::addr_t;
+
+    tgc_c();
+    ~tgc_c();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+#pragma pack(push, 1)
+    struct TGC_C_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t X16 = 0; 
+        uint32_t X17 = 0; 
+        uint32_t X18 = 0; 
+        uint32_t X19 = 0; 
+        uint32_t X20 = 0; 
+        uint32_t X21 = 0; 
+        uint32_t X22 = 0; 
+        uint32_t X23 = 0; 
+        uint32_t X24 = 0; 
+        uint32_t X25 = 0; 
+        uint32_t X26 = 0; 
+        uint32_t X27 = 0; 
+        uint32_t X28 = 0; 
+        uint32_t X29 = 0; 
+        uint32_t X30 = 0; 
+        uint32_t X31 = 0; 
+        uint32_t PC = 0; 
+        uint32_t NEXT_PC = 0; 
+        uint8_t PRIV = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t last_branch;
+    } reg;
+#pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+
+    uint32_t get_fcsr(){return 0;}
+    void set_fcsr(uint32_t val){}
+
+};
+
+}
+}            
+#endif /* _TGC_C_H_ */
--- a/incl/iss/arch/tgf_b.h
+++ b/incl/iss/arch/tgf_b.h
@ -1,252 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-
-#ifndef _TGF_B_H_
-#define _TGF_B_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgf_b;
-
-template <> struct traits<tgf_b> {
-
-	constexpr static char const* const core_type = "TGF_B";
-    
-  	static constexpr std::array<const char*, 33> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
- 
-  	static constexpr std::array<const char*, 33> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
-
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-        X29,
-        X30,
-        X31,
-        PC,
-        NUM_REGS,
-        NEXT_PC=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT,
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-};
-
-struct tgf_b: public arch_if {
-
-    using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
-    using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
-    using reg_t =  typename traits<tgf_b>::reg_t;
-    using addr_t = typename traits<tgf_b>::addr_t;
-
-    tgf_b();
-    ~tgf_b();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct TGF_B_regs {
-        uint32_t X0 = 0;
-        uint32_t X1 = 0;
-        uint32_t X2 = 0;
-        uint32_t X3 = 0;
-        uint32_t X4 = 0;
-        uint32_t X5 = 0;
-        uint32_t X6 = 0;
-        uint32_t X7 = 0;
-        uint32_t X8 = 0;
-        uint32_t X9 = 0;
-        uint32_t X10 = 0;
-        uint32_t X11 = 0;
-        uint32_t X12 = 0;
-        uint32_t X13 = 0;
-        uint32_t X14 = 0;
-        uint32_t X15 = 0;
-        uint32_t X16 = 0;
-        uint32_t X17 = 0;
-        uint32_t X18 = 0;
-        uint32_t X19 = 0;
-        uint32_t X20 = 0;
-        uint32_t X21 = 0;
-        uint32_t X22 = 0;
-        uint32_t X23 = 0;
-        uint32_t X24 = 0;
-        uint32_t X25 = 0;
-        uint32_t X26 = 0;
-        uint32_t X27 = 0;
-        uint32_t X28 = 0;
-        uint32_t X29 = 0;
-        uint32_t X30 = 0;
-        uint32_t X31 = 0;
-        uint32_t PC = 0;
-        uint32_t NEXT_PC = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGF_B_H_ */
--- a/incl/iss/arch/tgf_c.h
+++ b/incl/iss/arch/tgf_c.h
@ -1,252 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-
-#ifndef _TGF_C_H_
-#define _TGF_C_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgf_c;
-
-template <> struct traits<tgf_c> {
-
-	constexpr static char const* const core_type = "TGF_C";
-    
-  	static constexpr std::array<const char*, 33> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
- 
-  	static constexpr std::array<const char*, 33> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
-
-    enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-        X29,
-        X30,
-        X31,
-        PC,
-        NUM_REGS,
-        NEXT_PC=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT,
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
-
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-};
-
-struct tgf_c: public arch_if {
-
-    using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
-    using reg_t =  typename traits<tgf_c>::reg_t;
-    using addr_t = typename traits<tgf_c>::addr_t;
-
-    tgf_c();
-    ~tgf_c();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct TGF_C_regs {
-        uint32_t X0 = 0;
-        uint32_t X1 = 0;
-        uint32_t X2 = 0;
-        uint32_t X3 = 0;
-        uint32_t X4 = 0;
-        uint32_t X5 = 0;
-        uint32_t X6 = 0;
-        uint32_t X7 = 0;
-        uint32_t X8 = 0;
-        uint32_t X9 = 0;
-        uint32_t X10 = 0;
-        uint32_t X11 = 0;
-        uint32_t X12 = 0;
-        uint32_t X13 = 0;
-        uint32_t X14 = 0;
-        uint32_t X15 = 0;
-        uint32_t X16 = 0;
-        uint32_t X17 = 0;
-        uint32_t X18 = 0;
-        uint32_t X19 = 0;
-        uint32_t X20 = 0;
-        uint32_t X21 = 0;
-        uint32_t X22 = 0;
-        uint32_t X23 = 0;
-        uint32_t X24 = 0;
-        uint32_t X25 = 0;
-        uint32_t X26 = 0;
-        uint32_t X27 = 0;
-        uint32_t X28 = 0;
-        uint32_t X29 = 0;
-        uint32_t X30 = 0;
-        uint32_t X31 = 0;
-        uint32_t PC = 0;
-        uint32_t NEXT_PC = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGF_C_H_ */
--- a/incl/iss/debugger/riscv_target_adapter.h
+++ b/incl/iss/debugger/riscv_target_adapter.h
@ -183,7 +183,8 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
    data.clear();
    avail.clear();
    const uint8_t *reg_base = core->get_regs_base_ptr();
-    for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
+    auto start_reg=arch::traits<ARCH>::X0;
+    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
        unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
        for (size_t j = 0; j < reg_width; ++j) {
@ -210,11 +211,11 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
 }

 template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
-    auto reg_count = arch::traits<ARCH>::NUM_REGS;
+    auto start_reg=arch::traits<ARCH>::X0;
    auto *reg_base = core->get_regs_base_ptr();
    auto iter = data.data();
-    for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
+    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
        std::copy(iter, iter + reg_width, reg_base);
        iter += 4;
--- a/incl/iss/factory.h
+++ b/incl/iss/factory.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2021 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -29,41 +29,34 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
- 
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/tgf_c.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>

-using namespace iss::arch;
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_

-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_names;
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
+#include <iss/iss.h>

-tgf_c::tgf_c() {
-    reg.icount = 0;
+namespace iss {
+
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+
+template<typename PLAT>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
+    using core_type = typename PLAT::core;
+    core_type* lcpu = new PLAT();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_LLVM
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+    return {nullptr, nullptr};
 }

-tgf_c::~tgf_c() = default;
-
-void tgf_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *tgf_c::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
 }

+#endif /* _ISS_FACTORY_H_ */
--- a/incl/iss/plugin/cycle_estimate.h
+++ b/incl/iss/plugin/cycle_estimate.h
@ -76,7 +76,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t instr_info) override;
+    void callback(instr_info_t instr_info, exec_info const&) override;

 private:
    iss::instrumentation_if *arch_instr;
--- a/incl/iss/plugin/instruction_count.h
+++ b/incl/iss/plugin/instruction_count.h
@ -69,7 +69,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t instr_info) override;
+    void callback(instr_info_t, exec_info const&) override;

 private:
    Json::Value root;
--- a/incl/sysc/core_complex.h
+++ b/incl/sysc/core_complex.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017-2021 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -30,33 +30,23 @@
 *
 *******************************************************************************/

-#ifndef _SYSC_SIFIVE_FE310_H_
-#define _SYSC_SIFIVE_FE310_H_
+#ifndef _SYSC_CORE_COMPLEX_H_
+#define _SYSC_CORE_COMPLEX_H_

-#include "tlm/scc/initiator_mixin.h"
-#include "scc/traceable.h"
-#include "scc/utilities.h"
-#include "tlm/scc/scv4tlm/tlm_rec_initiator_socket.h"
+#include <tlm/scc/initiator_mixin.h>
+#include <scc/traceable.h>
+#include <scc/tick2time.h>
+#include <scc/utilities.h>
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#ifdef CWR_SYSTEMC
+#include <scmlinc/scml_property.h>
+#else
 #include <cci_configuration>
+#endif
 #include <tlm>
-#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
-
-class scv_tr_db;
-class scv_tr_stream;
-struct _scv_tr_generator_default_data;
-template <class T_begin, class T_end> class scv_tr_generator;
-
-namespace iss {
-class vm_if;
-namespace arch {
-template <typename BASE> class riscv_hart_m_p;
-}
-namespace debugger {
-class target_adapter_if;
-}
-} // namespace iss
+#include <memory>

 namespace sysc {

@ -70,14 +60,13 @@ public:
    bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
 };

-namespace SiFive {
+namespace tgfs {
 class core_wrapper;
+struct core_trace;

 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
-
-    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};

    sc_core::sc_in<bool> rst_i{"rst_i"};

@ -89,6 +78,9 @@ public:

    sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};

+#ifndef CWR_SYSTEMC
+	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+
    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;

    cci::cci_param<std::string> elf_file{"elf_file", ""};
@ -97,7 +89,9 @@ public:

    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};

-    cci::cci_param<std::string> backend{"backend", "tcc"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
+
+    cci::cci_param<std::string> backend{"backend", "interp"};

    cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};

@ -105,7 +99,47 @@ public:

    cci::cci_param<uint32_t> mhartid{"mhartid", 0};

-    core_complex(sc_core::sc_module_name name);
+    core_complex(sc_core::sc_module_name const& name);
+
+#else
+	sc_core::sc_in<bool> clk_i{"clk_i"};
+
+	sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
+
+	scml_property<std::string> elf_file{"elf_file", ""};
+
+    scml_property<bool> enable_disass{"enable_disass", false};
+
+    scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
+
+    scml_property<std::string> core_type{"core_type", "tgc_c"};
+
+    scml_property<std::string> backend{"backend", "interp"};
+
+    scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
+
+    scml_property<bool> dump_ir{"dump_ir", false};
+
+    scml_property<uint32_t> mhartid{"mhartid", 0};
+
+    core_complex(sc_core::sc_module_name const& name)
+    : sc_module(name)
+    , local_irq_i{"local_irq_i", 16}
+    , elf_file{"elf_file", ""}
+    , enable_disass{"enable_disass", false}
+    , reset_address{"reset_address", 0ULL}
+    , core_type{"core_type", "tgc_c"}
+    , backend{"backend", "interp"}
+    , gdb_server_port{"gdb_server_port", 0}
+    , dump_ir{"dump_ir", false}
+    , mhartid{"mhartid", 0}
+    , read_lut(tlm_dmi_ext())
+    , write_lut(tlm_dmi_ext())
+    {
+    	init();
+    }
+
+#endif

    ~core_complex();

@ -129,13 +163,14 @@ public:

    void trace(sc_core::sc_trace_file *trf) const override;

-    void disass_output(uint64_t pc, const std::string instr);
+    bool disass_output(uint64_t pc, const std::string instr);

+    void set_clock_period(sc_core::sc_time period);
 protected:
    void before_end_of_elaboration() override;
    void start_of_simulation() override;
+	void forward();
    void run();
-    void clk_cb();
    void rst_cb();
    void sw_irq_cb();
    void timer_irq_cb();
@ -144,23 +179,14 @@ protected:
    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
    tlm_utils::tlm_quantumkeeper quantum_keeper;
    std::vector<uint8_t> write_buf;
-    std::unique_ptr<core_wrapper> cpu;
-    std::unique_ptr<iss::vm_if> vm;
-    sc_core::sc_time curr_clk;
-    iss::debugger::target_adapter_if *tgt_adapter;
-#ifdef WITH_SCV
-    //! transaction recording database
-    scv_tr_db *m_db;
-    //! blocking transaction recording stream handle
-    scv_tr_stream *stream_handle;
-    //! transaction generator handle for blocking transactions
-    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
-    scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
-    scv_tr_handle tr_handle;
-#endif
+    core_wrapper* cpu{nullptr};
+    sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    core_trace* trc{nullptr};
+    std::unique_ptr<scc::tick2time> t2t;
+private:
+    void init();
 };
-
 } /* namespace SiFive */
 } /* namespace sysc */

-#endif /* _SYSC_SIFIVE_FE310_H_ */
+#endif /* _SYSC_CORE_COMPLEX_H_ */
--- a/softfloat/build/Linux-x86_64-GCC/platform.h
+++ b/softfloat/build/Linux-x86_64-GCC/platform.h
@ -49,7 +49,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
+#ifdef __GNUC__
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
+#endif
 #include "opts-GCC.h"

--- a/src/iss/.gitignore
+++ b/src/iss/.gitignore
@ -0,0 +1 @@
+/tgc_*.cpp
--- a/src/iss/tgc_c.cpp
+++ b/src/iss/tgc_c.cpp
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -29,41 +29,41 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
- 
+
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgf_b.h>
+#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>

 using namespace iss::arch;

-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_names;
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
+constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;

-tgf_b::tgf_b() {
+tgc_c::tgc_c() {
    reg.icount = 0;
 }

-tgf_b::~tgf_b() = default;
+tgc_c::~tgc_c() = default;

-void tgf_b::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgf_b>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_b>::reg_t),0));
+void tgc_c::reset(uint64_t address) {
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
+    reg.PRIV=0x3;
    reg.trap_state=0;
-    reg.machine_state=0x3;
    reg.icount=0;
 }

-uint8_t *tgf_b::get_regs_base_ptr() {
+uint8_t *tgc_c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }

-tgf_b::phys_addr_t tgf_b::virt2phys(const iss::addr_t &pc) {
+tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
    return phys_addr_t(pc); // change logical address to physical address
 }

--- a/src/main.cpp
+++ b/src/main.cpp
@ -31,13 +31,24 @@
 *******************************************************************************/

 #include <iostream>
-#include <iss/iss.h>
+#include <iss/factory.h>

 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/tgf_b.h>
-#include <iss/arch/tgf_c.h>
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_c.h"
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_B
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_b.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#endif
+#ifdef CORE_TGC_D
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d.h"
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
 #endif
@ -47,23 +58,6 @@

 namespace po = boost::program_options;

-using cpu_ptr = std::unique_ptr<iss::arch_if>;
-using vm_ptr= std::unique_ptr<iss::vm_if>;
-
-template<typename CORE>
-std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
-    CORE* lcpu = new iss::arch::riscv_hart_m_p<CORE>();
-    if(backend == "interp")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-#ifdef WITH_LLVM
-    if(backend == "llvm")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-    if(backend == "tcc")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-    return {nullptr, nullptr};
-}
-
 int main(int argc, char *argv[]) {
    /*
     *  Define and parse the program options
@ -83,8 +77,8 @@ int main(int argc, char *argv[]) {
        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
        ("mem,m", po::value<std::string>(), "the memory input file")
        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
-        ("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
+        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
    // clang-format on
    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
    try {
@ -126,17 +120,27 @@ int main(int argc, char *argv[]) {
 #endif
        bool dump = clim.count("dump-ir");
        // instantiate the simulator
-        vm_ptr vm{nullptr};
-        cpu_ptr cpu{nullptr};
+        iss::vm_ptr vm{nullptr};
+        iss::cpu_ptr cpu{nullptr};
        std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgf_b") {
+        if (isa_opt == "tgc_c") {
            std::tie(cpu, vm) =
-                create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else if (isa_opt == "tgf_c") {
+                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#ifdef CORE_TGC_B
+        if (isa_opt == "tgc_b") {
            std::tie(cpu, vm) =
-                create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else {
-            LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D
+        if (isa_opt == "tgc_d") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+        {
+            LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
            return 127;
        }
        if (clim.count("plugin")) {
@ -157,7 +161,7 @@ int main(int argc, char *argv[]) {
                    vm->register_plugin(*ce_plugin);
                    plugin_list.push_back(ce_plugin);
                } else {
-                    LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+                    LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                    return 127;
                }
            }
@ -174,7 +178,7 @@ int main(int argc, char *argv[]) {
        }
        uint64_t start_address = 0;
        if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_b>::MEM);
+            vm->get_arch()->load_file(clim["mem"].as<std::string>());
        if (clim.count("elf"))
            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
                auto start_addr = vm->get_arch()->load_file(input);
@ -192,7 +196,7 @@ int main(int argc, char *argv[]) {
        auto cycles = clim["instructions"].as<uint64_t>();
        res = vm->start(cycles, dump);
    } catch (std::exception &e) {
-        LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
                   << std::endl;
        res = 2;
    }
--- a/src/plugin/cycle_estimate.cpp
+++ b/src/plugin/cycle_estimate.cpp
@ -47,10 +47,10 @@ iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
            try {
                is >> root;
            } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
            }
        } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
        }
    }
 }
@ -77,16 +77,18 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
    		}
    	}
    } else {
-        LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
    }
 	return true;

 }

-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
    assert(arch_instr && "No instrumentation interface available but callback executed");
 	auto entry = delays[instr_info.instr_id];
 	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
-    uint32_t delay = taken ? entry.taken : entry.not_taken;
-    if(delay>1) arch_instr->set_curr_instr_cycles(delay);
+    if (taken && entry.taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.taken);
+    else if (entry.not_taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.not_taken);
 }
--- a/src/plugin/instruction_count.cpp
+++ b/src/plugin/instruction_count.cpp
@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
            try {
                is >> root;
            } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
            }
        } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
        }
    }
 }
@ -85,11 +85,11 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
    	}
    	rep_counts.resize(delays.size());
    } else {
-        LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
    }
 	return true;
 }

-void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
 	rep_counts[instr_info.instr_id]++;
 }
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@ -30,26 +30,58 @@
 *
 *******************************************************************************/

+// clang-format off
+#include "iss/debugger/gdb_session.h"
+#include "iss/debugger/encoderdecoder.h"
+#include "iss/debugger/server.h"
+#include "iss/debugger/target_adapter_if.h"
+#include "iss/iss.h"
+#include "iss/vm_types.h"
 #include "sysc/core_complex.h"
+#ifdef CORE_TGC_B
 #include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgf_c.h"
-#include "iss/debugger/encoderdecoder.h"
-#include "iss/debugger/gdb_session.h"
-#include "iss/debugger/server.h"
-#include "iss/debugger/target_adapter_if.h"
-#include "iss/iss.h"
-#include "iss/vm_types.h"
+#include "iss/arch/tgc_b.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#endif
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_c.h"
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_D
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d.h"
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
+#endif
 #include "scc/report.h"
 #include <iostream>
 #include <sstream>
+#include <array>
+// clang-format on
+
+#define STR(X) #X
+#define CREATE_CORE(CN) \
+if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else

 #ifdef WITH_SCV
-#include <array>
 #include <scv.h>
+#else
+#include <scv-tr.h>
+using namespace scv_tr;
 #endif

+#ifndef CWR_SYSTEMC
+#define GET_PROP_VALUE(P) P.get_value()
+#else
+#define GET_PROP_VALUE(P) P.getValue()
+#endif
+
+#ifdef _MSC_VER
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+#define strncasecmp _strnicmp
+#define strcasecmp _stricmp
+#endif
+
 namespace sysc {
-namespace SiFive {
+namespace tgfs {
 using namespace std;
 using namespace iss;
 using namespace logging;
@ -57,69 +89,42 @@ using namespace sc_core;

 namespace {
 iss::debugger::encoder_decoder encdec;
-}
-
-using core_type = iss::arch::tgf_c;
-
-namespace {

 std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-
-std::array<const char*, 16> trap_str = { {
-		"Instruction address misaligned",
-		"Instruction access fault",
-		"Illegal instruction",
-		"Breakpoint",
-		"Load address misaligned",
-		"Load access fault",
-		"Store/AMO address misaligned",
-		"Store/AMO access fault",
-		"Environment call from U-mode",
-		"Environment call from S-mode",
-		"Reserved",
-		"Environment call from M-mode",
-		"Instruction page fault",
-		"Load page fault",
-		"Reserved",
-		"Store/AMO page fault"
-} };
-std::array<const char*, 12> irq_str = { {
-		"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
-		"User timer interrupt",    "Supervisor timer interrupt",    "Reserved", "Machine timer interrupt",
-		"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
 }

-class core_wrapper : public iss::arch::riscv_hart_m_p<core_type> {
+template<typename PLAT>
+class core_wrapper_t : public PLAT {
 public:
-    using base_type = arch::riscv_hart_m_p<core_type>;
-    using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
-    core_wrapper(core_complex *owner)
+    using reg_t       = typename arch::traits<typename PLAT::core>::reg_t;
+    using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
+    using heart_state_t = typename PLAT::hart_state_type;
+    core_wrapper_t(core_complex *owner)
    : owner(owner) { }

-    uint32_t get_mode() { return this->reg.machine_state; }
+    uint32_t get_mode() { return this->reg.PRIV; }

    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }

    inline bool get_interrupt_execution() { return this->interrupt_sim; }

-    base_type::hart_state<base_type::reg_t> &get_state() { return this->state; }
+    heart_state_t &get_state() { return this->state; }

-    void notify_phase(exec_phase p) override {
-        if (p == ISTART) owner->sync(this->reg.icount + cycle_offset);
+    void notify_phase(iss::arch_if::exec_phase p) override {
+        if (p == iss::arch_if::ISTART) owner->sync(this->reg.icount);
    }

    sync_type needed_sync() const override { return PRE_SYNC; }

    void disass_output(uint64_t pc, const std::string instr) override {
-        if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
+        if (!owner->disass_output(pc, instr)) {
            std::stringstream s;
-            s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            Log<Output2FILE<disass>>().get(INFO, "disass")
+            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
+              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
+            SCCDEBUG(owner->name())<<"disass: "
                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                << std::setfill(' ') << std::left << instr << s.str();
        }
-        owner->disass_output(pc, instr);
    };

    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
@ -146,6 +151,7 @@ public:
    }

    status read_csr(unsigned addr, reg_t &val) override {
+#ifndef CWR_SYSTEMC
        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
            uint64_t time_val;
            bool ret = owner->mtime_o->nb_peek(time_val);
@ -156,21 +162,32 @@ public:
                val = static_cast<reg_t>(time_val >> 32);
            }
            return ret?Ok:Err;
+#else
+		if((addr==arch::time || addr==arch::timeh)){
+			uint64_t time_val = owner->mtime_i.read();
+			if (addr == iss::arch::time) {
+				val = static_cast<reg_t>(time_val);
+			} else if (addr == iss::arch::timeh) {
+				if (sizeof(reg_t) != 4) return iss::Err;
+				val = static_cast<reg_t>(time_val >> 32);
+			}
+			return Ok;
+#endif
        } else {
-            return base_type::read_csr(addr, val);
+            return PLAT::read_csr(addr, val);
        }
    }

    void wait_until(uint64_t flags) override {
        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
        do {
-            wait(wfi_evt);
+            sc_core::wait(wfi_evt);
        } while (this->reg.pending_trap == 0);
-        base_type::wait_until(flags);
+        PLAT::wait_until(flags);
    }

    void local_irq(short id, bool value) {
-        base_type::reg_t mask = 0;
+        reg_t mask = 0;
        switch (id) {
        case 16: // SW
            mask = 1 << 3;
@ -191,6 +208,8 @@ public:
        } else
            this->csr[arch::mip] &= ~mask;
        this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
    }

 private:
@ -228,19 +247,95 @@ int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func
    return Err;
 }

-core_complex::core_complex(sc_module_name name)
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+
+class core_wrapper {
+public:
+    core_wrapper(core_complex *owner) : owner(owner) { }
+
+    void reset(uint64_t addr){vm->reset(addr);}
+    inline void start(){vm->start();}
+    inline std::pair<uint64_t, bool> load_file(std::string const& name){ return cpu->load_file(name);};
+
+    std::function<unsigned(void)> get_mode;
+    std::function<uint64_t(void)> get_state;
+    std::function<bool(void)> get_interrupt_execution;
+    std::function<void(bool)> set_interrupt_execution;
+    std::function<void(short, bool)> local_irq;
+
+    template<typename PLAT>
+    std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
+        auto* lcpu = new core_wrapper_t<PLAT>(owner);
+        lcpu->set_mhartid(hart_id);
+        get_mode = [lcpu]() { return lcpu->get_mode(); };
+        get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
+        get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
+        set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
+        local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
+        if(backend == "interp")
+            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
+#ifdef WITH_LLVM
+        if(backend == "llvm")
+            return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_TCC
+        if(backend == "tcc")
+    s        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+        return {nullptr, nullptr};
+    }
+
+    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
+        CREATE_CORE(tgc_c)
+#ifdef CORE_TGC_B
+        CREATE_CORE(tgc_b)
+#endif
+#ifdef CORE_TGC_D
+        CREATE_CORE(tgc_d)
+#endif
+        {
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+        }
+        auto *srv = debugger::server<debugger::gdb_session>::get();
+        if (srv) tgt_adapter = srv->get_target();
+        if (tgt_adapter)
+            tgt_adapter->add_custom_command(
+                {"sysc", [this](int argc, char *argv[], debugger::out_func of,
+                                debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
+                 "SystemC sub-commands: break <time>, print_time"});
+
+    }
+
+    core_complex * const owner;
+    vm_ptr vm{nullptr};
+    cpu_ptr cpu{nullptr};
+    iss::debugger::target_adapter_if *tgt_adapter{nullptr};
+};
+
+struct core_trace {
+    //! transaction recording database
+    scv_tr_db *m_db{nullptr};
+    //! blocking transaction recording stream handle
+    scv_tr_stream *stream_handle{nullptr};
+    //! transaction generator handle for blocking transactions
+    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle{nullptr};
+    scv_tr_handle tr_handle;
+};
+
+SC_HAS_PROCESS(core_complex);// NOLINT
+#ifndef CWR_SYSTEMC
+core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
-, tgt_adapter(nullptr)
-#ifdef WITH_SCV
-, m_db(scv_tr_db::get_default_db())
-, stream_handle(nullptr)
-, instr_tr_handle(nullptr)
-, fetch_tr_handle(nullptr)
-#endif
 {
-    SC_HAS_PROCESS(core_complex);// NOLINT
+	init();
+}
+#endif
+
+void core_complex::init(){
+	trc=new core_trace();
    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
        auto lut_entry = read_lut.getEntry(start);
        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@ -253,8 +348,6 @@ core_complex::core_complex(sc_module_name name)
    });

    SC_THREAD(run);
-    SC_METHOD(clk_cb);
-    sensitive << clk_i;
    SC_METHOD(rst_cb);
    sensitive << rst_i;
    SC_METHOD(sw_irq_cb);
@ -263,82 +356,82 @@ core_complex::core_complex(sc_module_name name)
    sensitive << timer_irq_i;
    SC_METHOD(global_irq_cb);
    sensitive << global_irq_i;
+    trc->m_db=scv_tr_db::get_default_db();
+
+	SC_METHOD(forward);
+#ifndef CWR_SYSTEMC
+	sensitive<<clk_i;
+#else
+	sensitive<<curr_clk;
+	t2t.reset(new scc::tick2time{"t2t"});
+	t2t->clk_i(clk_i);
+	t2t->clk_o(curr_clk);
+#endif
 }

-core_complex::~core_complex() = default;
+core_complex::~core_complex(){
+    delete cpu;
+    delete trc;
+}

 void core_complex::trace(sc_trace_file *trf) const {}

-using vm_ptr= std::unique_ptr<iss::vm_if>;
-vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_port){
-    if(backend == "interp")
-        return vm_ptr{iss::interp::create<core_type>(cpu, gdb_port)};
-#ifdef WITH_LLVM
-    if(backend == "llvm")
-        return vm_ptr{iss::llvm::create(lcpu, gdb_port)};
-#endif
-    if(backend == "tcc")
-        return vm_ptr{iss::tcc::create<core_type>(cpu, gdb_port)};
-    return {nullptr};
-}
-
 void core_complex::before_end_of_elaboration() {
-    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
-    cpu = scc::make_unique<core_wrapper>(this);
-    cpu->set_mhartid(mhartid.get_value());
-
-    vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
-#ifdef WITH_SCV
-    vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
-#else
-    vm->setDisassEnabled(enable_disass.get_value());
-#endif
-    auto *srv = debugger::server<debugger::gdb_session>::get();
-    if (srv) tgt_adapter = srv->get_target();
-    if (tgt_adapter)
-        tgt_adapter->add_custom_command(
-            {"sysc", [this](int argc, char *argv[], debugger::out_func of,
-                            debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
-             "SystemC sub-commands: break <time>, print_time"});
+    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
+    // cpu = scc::make_unique<core_wrapper>(this);
+    cpu = new core_wrapper(this);
+    cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
+    sc_assert(cpu->vm!=nullptr);
+    cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
 }

 void core_complex::start_of_simulation() {
    quantum_keeper.reset();
-    if (elf_file.get_value().size() > 0) {
-        istringstream is(elf_file.get_value());
+    if (GET_PROP_VALUE(elf_file).size() > 0) {
+        istringstream is(GET_PROP_VALUE(elf_file));
        string s;
        while (getline(is, s, ',')) {
            std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
+#ifndef CWR_SYSTEMC
            if (reset_address.is_default_value() && start_addr.second == true)
                reset_address.set_value(start_addr.first);
+#else
+            if (start_addr.second == true)
+                reset_address=start_addr.first;
+#endif
        }
    }
-#ifdef WITH_SCV
-    if (m_db != nullptr && stream_handle == nullptr) {
+    if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
        string basename(this->name());
-        stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
-        instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
-        fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
+        trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);
+        trc->instr_tr_handle = new scv_tr_generator<>("execute", *trc->stream_handle);
    }
+}
+
+bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
+    if (trc->m_db == nullptr) return false;
+    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
+    trc->tr_handle = trc->instr_tr_handle->begin_transaction();
+    trc->tr_handle.record_attribute("PC", pc);
+    trc->tr_handle.record_attribute("INSTR", instr_str);
+    trc->tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
+    trc->tr_handle.record_attribute("MSTATUS", cpu->get_state());
+    trc->tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
+    return true;
+}
+
+void core_complex::forward() {
+#ifndef CWR_SYSTEMC
+	set_clock_period(clk_i.read());
+#else
+	set_clock_period(curr_clk.read());
+
 #endif
 }

-void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-#ifdef WITH_SCV
-    if (m_db == nullptr) return;
-    if (tr_handle.is_active()) tr_handle.end_transaction();
-    tr_handle = instr_tr_handle->begin_transaction();
-    tr_handle.record_attribute("PC", pc);
-    tr_handle.record_attribute("INSTR", instr_str);
-    tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
-    tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.backing.val);
-    tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
-#endif
-}
-
-void core_complex::clk_cb() {
-    curr_clk = clk_i.read();
-    if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
+void core_complex::set_clock_period(sc_core::sc_time period) {
+	curr_clk = period;
+    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
 }

 void core_complex::rst_cb() {
@ -355,14 +448,14 @@ void core_complex::run() {
    wait(SC_ZERO_TIME); // separate from elaboration phase
    do {
        if (rst_i.read()) {
-            cpu->reset(reset_address.get_value());
+            cpu->reset(GET_PROP_VALUE(reset_address));
            wait(rst_i.negedge_event());
        }
-        while (clk_i.read() == SC_ZERO_TIME) {
-            wait(clk_i.value_changed_event());
+        while (curr_clk.read() == SC_ZERO_TIME) {
+            wait(curr_clk.value_changed_event());
        }
        cpu->set_interrupt_execution(false);
-        vm->start();
+        cpu->start();
    } while (cpu->get_interrupt_execution());
    sc_stop();
 }
@ -382,16 +475,14 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
        gp.set_data_ptr(data);
        gp.set_data_length(length);
        gp.set_streaming_width(length);
-        sc_time delay{quantum_keeper.get_local_time()};
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            if (is_fetch && tr_handle.is_active()) {
-                tr_handle.end_transaction();
+        sc_time delay=quantum_keeper.get_local_time();
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            if (is_fetch && trc->tr_handle.is_active()) {
+                trc->tr_handle.end_transaction();
            }
-            auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-#endif
        initiator->b_transport(gp, delay);
        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
@ -431,13 +522,11 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
        gp.set_data_ptr(write_buf.data());
        gp.set_data_length(length);
        gp.set_streaming_width(length);
-        sc_time delay{quantum_keeper.get_local_time()};
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
+        sc_time delay=quantum_keeper.get_local_time();
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-#endif
        initiator->b_transport(gp, delay);
        quantum_keeper.set(delay);
        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
@ -500,6 +589,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
        return initiator->transport_dbg(gp) == length;
    }
 }
-
 } /* namespace SiFive */
 } /* namespace sysc */
--- a/src/vm/interp/.gitignore
+++ b/src/vm/interp/.gitignore
@ -0,0 +1 @@
+/vm_tgc_*.cpp
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
--- a/src/vm/interp/vm_tgf_b.cpp
+++ b/src/vm/interp/vm_tgf_b.cpp
--- a/src/vm/interp/vm_tgf_c.cpp
+++ b/src/vm/interp/vm_tgf_c.cpp
--- a/src/vm/tcc/vm_tgf_b.cpp
+++ b/src/vm/tcc/vm_tgf_b.cpp
@ -377,7 +377,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
        gen_trap_check(tu);
@ -424,7 +423,6 @@ private:
            new_pc_val,
            tu.l_not(tu.constant(0x1, 32U))), 32);
        tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
@ -466,7 +464,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
        gen_trap_check(tu);
@ -507,7 +504,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
        gen_trap_check(tu);
@ -552,7 +548,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
        gen_trap_check(tu);
@ -597,7 +592,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
        gen_trap_check(tu);
@ -638,7 +632,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
        gen_trap_check(tu);
@ -679,7 +672,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
        gen_trap_check(tu);
@ -1621,7 +1613,6 @@ private:
            tu.constant(1, 64U),
            tu.trunc(tu.constant(imm, 32U), 32));
        tu.close_scope();
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
        gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
        gen_trap_check(tu);
@ -2055,13 +2046,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,

 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
    tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
    tu("leave_trap(core_ptr, {});", lvl);
    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@ -2070,7 +2059,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
    tu("trap_entry:");
    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
    tu("return *next_pc;");
 }

--- a/src/vm/tcc/vm_tgf_c.cpp
+++ b/src/vm/tcc/vm_tgf_c.cpp
@ -449,7 +449,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
        gen_trap_check(tu);
@ -487,7 +486,6 @@ private:
            new_pc_val,
            tu.l_not(tu.constant(0x1, 32U))), 32);
        tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
        gen_trap_check(tu);
@ -528,7 +526,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
        gen_trap_check(tu);
@ -569,7 +566,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
        gen_trap_check(tu);
@ -614,7 +610,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
        gen_trap_check(tu);
@ -659,7 +654,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
        gen_trap_check(tu);
@ -700,7 +694,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
        gen_trap_check(tu);
@ -741,7 +734,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
        gen_trap_check(tu);
@ -1683,7 +1675,6 @@ private:
            tu.constant(1, 64U),
            tu.trunc(tu.constant(imm, 32U), 32));
        tu.close_scope();
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
        gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
        gen_trap_check(tu);
@ -2562,7 +2553,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
        gen_trap_check(tu);
@ -2868,7 +2858,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 76);
        gen_trap_check(tu);
@ -2908,7 +2897,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 77);
        gen_trap_check(tu);
@ -2948,7 +2936,6 @@ private:
        auto is_cont_v = tu.choose(
            tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)),
            tu.constant(0U, 32), tu.constant(1U, 32));
-        tu.store(is_cont_v, traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);
        gen_trap_check(tu);
@ -3055,7 +3042,6 @@ private:
        tu.open_scope();
        auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
        tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 82);
        gen_trap_check(tu);
@ -3108,7 +3094,6 @@ private:
            tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
        auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
        tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
-        tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
        tu.close_scope();
        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 84);
        gen_trap_check(tu);
@ -3247,13 +3232,11 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,

 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
    tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
    tu("leave_trap(core_ptr, {});", lvl);
    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@ -3262,7 +3245,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
    tu("trap_entry:");
    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
    tu("return *next_pc;");
 }
Author	SHA1	Message	Date
Eyck Jentzsch	c8679fca85	remove MSVC warning	2021-10-10 19:56:33 +02:00
Eyck Jentzsch	f0ada1ba8c	add MSVC 16 compatibility	2021-10-10 19:06:41 +02:00
Eyck Jentzsch	09b01af3fa	fix find_package use and debug access alignment check	2021-08-26 22:10:27 +02:00
Eyck Jentzsch	9c8b72693e	correct trap ids of access faults	2021-08-20 09:02:56 +02:00
Eyck Jentzsch	c409e7b7ca	adapt to fixed handling of SystemCPackage	2021-08-19 13:38:29 +02:00
Eyck Jentzsch	2f05083cf0	fix elf loader and pmp check for debug accesses	2021-08-19 10:50:25 +02:00
Eyck Jentzsch	e934049dd4	fix inconsistency due to PA adaptation	2021-08-16 17:55:14 +02:00
Eyck Jentzsch	94f796ebdb	add install target and PA compatibility	2021-08-16 17:02:31 +02:00
Eyck Jentzsch	836ba269e3	fix clic reset values	2021-08-16 15:05:05 +02:00
Eyck Jentzsch	c8681096be	update vm_tgfs_c to match CoreDSL	2021-08-14 10:57:36 +02:00
Eyck Jentzsch	adeffe47ad	fix behavior of riscv_hart_mu_p to match TGC_D	2021-08-12 20:34:10 +02:00
Eyck Jentzsch	d95846a849	fix trap handling if illegal fetch (PMP) and U-mode CSRs	2021-08-01 17:23:22 +02:00
Eyck Jentzsch	af887c286f	fix for #2	2021-07-28 09:09:08 +02:00
Eyck Jentzsch	4ddf50162c	make library naming consistent	2021-07-27 15:55:08 +02:00
Eyck Jentzsch	da819d8890	fix SystemC lib handling in build system	2021-07-27 12:25:31 +02:00
Eyck Jentzsch	5ef5d57d30	Merge branch 'tmp' into develop	2021-07-27 10:49:35 +02:00
Eyck Jentzsch	d7bddd825c	add clic CSRs	2021-07-27 10:47:48 +02:00
Eyck Jentzsch	15f46a87db	adapt core_complex to use scv-tr (scc commit id a3cde47)	2021-07-27 09:38:05 +02:00
Eyck Jentzsch	fc1ae4d57d	update build system	2021-07-26 12:03:52 +02:00
Eyck Jentzsch	d0f3a120fd	fix naming in MU wrapper	2021-07-19 16:26:23 +02:00
Eyck Jentzsch	c592a26346	fix mepc mask	2021-07-09 13:01:22 +02:00
Eyck Jentzsch	e68918c2e8	fix instruction decode	2021-07-09 07:37:12 +02:00
Eyck Jentzsch	473f8a5a17	fix privilege behavior	2021-07-07 11:30:00 +02:00
Eyck Jentzsch	2f4b5bd9b2	fix detailed behavior of TGC_C	2021-07-06 21:19:36 +02:00
Eyck Jentzsch	23b9741adf	refine and fix TGC_C iss to becoem compliant	2021-06-29 11:51:30 +02:00
Eyck Jentzsch	5d8da08ce5	fix linker issue the root cuase of the issue is the template paramter deduction which led to the wrong template parameter.	2021-06-26 14:30:36 +02:00
Stas	a249aea703	getting rid of the error: reference to 'wait' is ambiguous	2021-06-25 13:35:42 +02:00
Eyck Jentzsch	e432dd8208	fix handling of exceptions while accessing address spaces	2021-06-07 22:22:36 +02:00
Eyck Jentzsch	8c385647dd	remove redundant code from checked in generated sources	2021-05-26 23:06:31 +02:00
Eyck Jentzsch	aaceecd5dc	fix mu_p platform features and CSRs	2021-05-17 09:20:09 +02:00
Eyck Jentzsch	4b3f5a6b0c	add missing change	2021-05-16 16:44:30 +02:00
Eyck Jentzsch	d41e1d816a	add factory for ISS and use it in main.cpp	2021-05-16 16:44:14 +02:00
Eyck Jentzsch	a35974c9f5	make cpu type in core_complex configurable	2021-05-16 15:06:42 +02:00
Eyck Jentzsch	9c456ba8f2	initial version of MU hart	2021-05-14 13:29:39 +02:00
Eyck Jentzsch	c57884caee	small fix	2021-05-13 16:01:04 +02:00
Eyck Jentzsch	cf7b62a3f9	update names	2021-05-13 15:54:48 +02:00
Eyck Jentzsch	f2bf6d682a	fix build setup	2021-05-13 14:03:10 +02:00
Eyck Jentzsch	a1fa8877f7	make core name a cmake option	2021-05-13 09:32:38 +02:00
Eyck Jentzsch	391f9bb808	remove unneeded constants	2021-05-08 15:14:19 +02:00
Stanislaw Kaushanski	ef02dba8c5	add read misa callback	2021-04-09 11:20:51 +02:00
Stanislaw Kaushanski	2f4cfb68dc	update to latest SCC	2021-04-07 18:56:46 +02:00
Stanislaw Kaushanski	7009943106	fix wait for interrupt. Adapt for new SCC structure	2021-04-07 17:42:08 +02:00
Eyck Jentzsch	0a76ccbdac	make RSP register response independend of register definition	2021-03-31 07:48:46 +00:00
Eyck Jentzsch	32e4aa83b8	use extracted variables	2021-03-27 09:36:52 +00:00
Eyck Jentzsch	78c7064295	update groovy template to extract used registers	2021-03-26 08:24:45 +00:00
Eyck Jentzsch	412a4bd9bb	update name	2021-03-23 17:13:32 +00:00
Eyck Jentzsch	b0bcb7febb	small fixes for robustness and readability	2021-03-22 22:47:30 +00:00
Eyck Jentzsch	51fbc34fb3	change namespace of core complex	2021-03-22 11:57:40 +00:00
Eyck Jentzsch	4e0f20eba0	rework abort conditions	2021-03-17 19:32:57 +00:00
Eyck Jentzsch	ff3fa19208	fix RVM description bugs	2021-03-13 10:46:41 +00:00
Eyck Jentzsch	80057eef32	fix RVC description bugs, remove paged fetch	2021-03-13 10:46:41 +00:00
Stas	a5186ff88d	optional dependency to TGF_B_src target	2021-03-12 11:16:24 +01:00
Eyck Jentzsch	f4ec21007b	fix signedness issues	2021-03-11 16:12:28 +00:00
Eyck Jentzsch	ac8eab6e25	update RISC-V desciptions	2021-03-10 17:31:10 +00:00
Eyck Jentzsch	768716b064	fix another missing XLEN	2021-03-09 11:07:56 +00:00
Eyck Jentzsch	bea0dcc387	update missing XLEN	2021-03-09 11:03:37 +00:00
Eyck Jentzsch	a6691bcd3c	update generated code with correct sign extension	2021-03-09 10:21:36 +00:00
Eyck Jentzsch	40db74ce02	remove tgf_b code generation	2021-03-07 16:26:14 +00:00
Eyck Jentzsch	c171e3c1ba	update CoreDSL descriptions	2021-03-07 10:51:15 +00:00
Eyck Jentzsch	c251fe15d5	fix desscriptions to conform to ISA spec version 20191213 and TGF-C	2021-03-07 10:51:00 +00:00
Eyck Jentzsch	dae8acb8a3	checkpoint before refactor	2021-03-06 07:17:42 +00:00
Eyck Jentzsch	f7cec99fa6	adapt to changes in SCC	2021-03-01 21:08:18 +00:00
Eyck Jentzsch	be0e7db185	fix templates to comply with CoreDSL2	2021-03-01 21:07:20 +00:00
Eyck Jentzsch	4aa26b85a0	adapt to change in SCC	2021-03-01 06:36:27 +00:00
Eyck Jentzsch	9534d58d01	regenerated sources and and add opcode enum to headers Conflicts: gen_input/CoreDSL-Instruction-Set-Description	2021-03-01 06:26:33 +00:00
Eyck Jentzsch	1668df0531	regenerated sources and and add opcode enum to headers	2021-02-23 08:29:31 +00:00
Eyck Jentzsch	d8e009c72b	update CoreDSL decriptions	2021-02-15 18:15:13 +00:00
Eyck Jentzsch	d07c8679ed	update core definition	2021-02-15 18:14:52 +00:00
Eyck Jentzsch	3d5b61f301	move boost libraries from tgfs_sc to tgfs library	2021-02-15 18:03:39 +00:00
Eyck Jentzsch	337f1634c0	add mssing change	2021-02-15 18:01:46 +00:00
Eyck Jentzsch	72b09472d5	update RISC-V descriptions	2021-02-15 18:01:33 +00:00
Eyck Jentzsch	3261055871	update description to latest CoreDSL2	2021-02-15 11:35:56 +00:00
Eyck Jentzsch	34bb8e62ae	generate working ISS from CoreDSL 2.0	2021-02-06 14:47:06 +00:00
eyck	da7e29fbb7	update definitions of derived constants	2021-01-01 09:19:48 +00:00
eyck	c4da47cedd	integrate code generation into build process (first attempt)	2020-12-30 07:29:52 +00:00
eyck	ab554539e3	first version of tgf_c based on CoreDSL 2.0	2020-12-29 08:48:22 +00:00
eyck	d43b35949e	fix CMakeList.txt so that it builds without platform and external libs	2020-12-23 16:24:10 +00:00