DBT-RISE
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DBT-RISE-TGC
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update names

This commit is contained in:
Eyck Jentzsch 2021-05-13 15:38:33 +02:00
parent f2bf6d682a
commit cf7b62a3f9
10 changed files with 67 additions and 46 deletions
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5
CMakeLists.txt
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@ -66,7 +66,8 @@ set_target_properties(${PROJECT_NAME} PROPERTIES
if(SystemC_FOUND)
add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_${CORE_NAME})
target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
if(SCV_FOUND)
@ -87,7 +88,7 @@ endif()
project(tgc-sim)
add_executable(${PROJECT_NAME} src/main.cpp)
# This sets the include directory for the reference project. This is the -I flag in gcc.
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
if(WITH_LLVM)
target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})

14
gen_input/TGFS.core_desc
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@ -2,7 +2,7 @@ import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGF_B provides RV32I {
Core TGC_B provides RV32I {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
@ -14,7 +14,7 @@ Core TGF_B provides RV32I {
}
}
Core TGF_C provides RV32I, RV32M, RV32IC {
Core TGC_C provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
@ -25,3 +25,13 @@ Core TGF_C provides RV32I, RV32M, RV32IC {
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}
Core TGC_D provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
}
}

2
incl/iss/arch/.gitignore vendored
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@ -1 +1 @@
/tgf_b.h
/tgc_*.h

34
incl/iss/arch/tgf_c.h → incl/iss/arch/tgc_c.h
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@ -30,8 +30,8 @@
*
*******************************************************************************/
#ifndef _TGF_C_H_
#define _TGF_C_H_
#ifndef _TGC_C_H_
#define _TGC_C_H_
#include <array>
#include <iss/arch/traits.h>
@ -41,11 +41,11 @@
namespace iss {
namespace arch {
struct tgf_c;
struct tgc_c;
template <> struct traits<tgf_c> {
template <> struct traits<tgc_c> {
constexpr static char const* const core_type = "TGF_C";
constexpr static char const* const core_type = "TGC_C";
static constexpr std::array<const char*, 35> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
@ -53,7 +53,7 @@ template <> struct traits<tgf_c> {
static constexpr std::array<const char*, 35> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;
@ -179,15 +179,15 @@ template <> struct traits<tgf_c> {
};
};
struct tgf_c: public arch_if {
struct tgc_c: public arch_if {
using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
using reg_t = typename traits<tgf_c>::reg_t;
using addr_t = typename traits<tgf_c>::addr_t;
using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
using reg_t = typename traits<tgc_c>::reg_t;
using addr_t = typename traits<tgc_c>::addr_t;
tgf_c();
~tgf_c();
tgc_c();
~tgc_c();
void reset(uint64_t address=0) override;
@ -208,9 +208,9 @@ struct tgf_c: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
} else
return virt2phys(addr);
}
@ -223,7 +223,7 @@ struct tgf_c: public arch_if {
protected:
#pragma pack(push, 1)
struct TGF_C_regs {
struct TGC_C_regs {
uint32_t X0 = 0;
uint32_t X1 = 0;
uint32_t X2 = 0;
@ -275,4 +275,4 @@ protected:
}
}
#endif /* _TGF_C_H_ */
#endif /* _TGC_C_H_ */

2
src/iss/.gitignore vendored
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@ -1 +1 @@
/tgf_b.cpp
/tgc_*.cpp

22
src/iss/tgf_c.cpp → src/iss/tgc_c.cpp
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@ -32,26 +32,26 @@
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/tgf_c.h>
#include <iss/arch/tgc_c.h>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
tgf_c::tgf_c() {
tgc_c::tgc_c() {
reg.icount = 0;
}
tgf_c::~tgf_c() = default;
tgc_c::~tgc_c() = default;
void tgf_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
void tgc_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
@ -59,11 +59,11 @@ void tgf_c::reset(uint64_t address) {
reg.icount=0;
}
uint8_t *tgf_c::get_regs_base_ptr() {
uint8_t *tgc_c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

14
src/main.cpp
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@ -36,10 +36,14 @@
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_m_p.h>
#ifdef WITH_TGF_B
#include <iss/arch/tgf_b.h>
#ifdef CORE_TGC_C
#include "iss/arch/tgc_c.h"
using core_type = iss::arch::tgc_c;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/tgc_d.h"
using core_type = iss::arch::tgc_d;
#endif
#include <iss/arch/tgf_c.h>
#ifdef WITH_LLVM
#include <iss/llvm/jit_helper.h>
#endif
@ -139,7 +143,7 @@ int main(int argc, char *argv[]) {
#endif
if (isa_opt == "tgf_c") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
create_cpu<core_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else {
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
return 127;
@ -179,7 +183,7 @@ int main(int argc, char *argv[]) {
}
uint64_t start_address = 0;
if (clim.count("mem"))
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_c>::MEM);
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<core_type>::MEM);
if (clim.count("elf"))
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
auto start_addr = vm->get_arch()->load_file(input);

10
src/sysc/core_complex.cpp
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@ -32,7 +32,14 @@
#include "sysc/core_complex.h"
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgf_c.h"
#ifdef CORE_TGC_C
#include "iss/arch/tgc_c.h"
using core_type = iss::arch::tgc_c;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/tgc_d.h"
using core_type = iss::arch::tgc_d;
#endif
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/server.h"
@ -59,7 +66,6 @@ namespace {
iss::debugger::encoder_decoder encdec;
}
using core_type = iss::arch::tgf_c;
namespace {

2
src/vm/interp/.gitignore vendored
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@ -1 +1 @@
/vm_tgf_b.cpp
/vm_tgc_*.cpp

8
src/vm/interp/vm_tgf_c.cpp → src/vm/interp/vm_tgc_c.cpp
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@ -31,7 +31,7 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/tgf_c.h>
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace tgf_c {
namespace tgc_c {
using namespace iss::arch;
using namespace iss::debugger;
@ -3542,8 +3542,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}