update generated code with correct sign extension
This commit is contained in:
parent
40db74ce02
commit
a6691bcd3c
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@ -165,6 +165,12 @@ protected:
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
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template<unsigned W, typename T>
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inline T sext(T from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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private:
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/****************************************************************************
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@ -36,7 +36,9 @@
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#include <boost/lexical_cast.hpp>
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#include <boost/program_options.hpp>
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#include <iss/arch/riscv_hart_m_p.h>
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#ifdef WITH_TGF_B
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#include <iss/arch/tgf_b.h>
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#endif
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#include <iss/arch/tgf_c.h>
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#ifdef WITH_LLVM
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#include <iss/llvm/jit_helper.h>
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@ -129,10 +131,13 @@ int main(int argc, char *argv[]) {
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vm_ptr vm{nullptr};
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cpu_ptr cpu{nullptr};
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std::string isa_opt(clim["isa"].as<std::string>());
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#ifdef WITH_TGF_B
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if (isa_opt == "tgf_b") {
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std::tie(cpu, vm) =
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create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else if (isa_opt == "tgf_c") {
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} else
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#endif
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if (isa_opt == "tgf_c") {
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std::tie(cpu, vm) =
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create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else {
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@ -174,7 +179,7 @@ int main(int argc, char *argv[]) {
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}
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uint64_t start_address = 0;
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if (clim.count("mem"))
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_b>::MEM);
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_c>::MEM);
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if (clim.count("elf"))
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for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
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auto start_addr = vm->get_arch()->load_file(input);
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@ -165,6 +165,12 @@ protected:
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
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template<unsigned W, typename T>
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inline T sext(T from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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private:
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/****************************************************************************
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@ -444,7 +450,7 @@ private:
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// execute instruction
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{
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if(rd != 0) *(X+rd) = *PC + 4;
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pc_assign(*NEXT_PC) = *PC + (int32_t)imm;
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pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
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}
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2);
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@ -479,7 +485,7 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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int32_t new_pc = *(X+rs1) + (int16_t)imm;
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int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
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if(rd != 0) *(X+rd) = *PC + 4;
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pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
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}
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@ -515,7 +521,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -548,7 +554,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -581,7 +587,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -614,7 +620,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -647,7 +653,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -680,7 +686,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -714,7 +720,7 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm);
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int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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}
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// post execution stuff
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@ -750,10 +756,10 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint32_t load_address = *(X+rs1) + (int16_t)imm;
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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if(traits::eei_aligned_addresses && (load_address & 0x1)) raise(0, 4);
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else {
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int16_t res = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm);
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int16_t res = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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}
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}
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@ -790,10 +796,10 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint32_t load_address = *(X+rs1) + (int16_t)imm;
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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if(traits::eei_aligned_addresses && (load_address & 0x3)) raise(0, 4);
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else {
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int32_t res = (int32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)imm);
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int32_t res = (int32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = (uint32_t)res;
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}
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}
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@ -830,7 +836,7 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm);
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uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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}
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// post execution stuff
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@ -866,10 +872,10 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint32_t load_address = *(X+rs1) + (int16_t)imm;
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uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
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if(traits::eei_aligned_addresses && (load_address & 0x1)) raise(0, 4);
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else {
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uint16_t res = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm);
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uint16_t res = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
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if(rd != 0) *(X+rd) = res;
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}
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}
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@ -905,7 +911,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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writeSpace1(traits::MEM, *(X+rs1) + (int16_t)imm, (int8_t)*(X+rs2));
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writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -939,7 +945,7 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint32_t store_address = *(X+rs1) + (int16_t)imm;
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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if(traits::eei_aligned_addresses && (store_address & 0x1)) raise(0, 6);
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else writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
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}
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@ -976,7 +982,7 @@ private:
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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uint32_t store_address = *(X+rs1) + (int16_t)imm;
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uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
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if(traits::eei_aligned_addresses && (store_address & 0x3)) raise(0, 6);
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else writeSpace4(traits::MEM, store_address, *(X+rs2));
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}
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@ -1012,7 +1018,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)imm;
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if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -1045,7 +1051,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)imm? 1 : 0;
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if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -1111,7 +1117,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)imm;
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if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -1144,7 +1150,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)imm;
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if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -1177,7 +1183,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 4;
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// execute instruction
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if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)imm;
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if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -2567,7 +2573,7 @@ private:
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + 2;
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// execute instruction
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*(X+rs1) = *(X+rs1) + (int8_t)imm;
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*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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@ -2629,7 +2635,7 @@ private:
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// execute instruction
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{
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*(X+1) = *PC + 2;
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pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
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pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
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}
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
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@ -2663,7 +2669,7 @@ private:
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*NEXT_PC = *PC + 2;
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// execute instruction
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{
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if(rd == 0) *(X+rd) = (int8_t)imm;
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if(rd == 0) *(X+rd) = (int8_t)sext<6>(imm);
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}
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
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@ -2699,7 +2705,7 @@ private:
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{
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if(rd == 0) raise(0, 2);
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if(imm == 0) raise(0, 2);
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*(X+rd) = (int32_t)imm;
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*(X+rd) = (int32_t)sext<18>(imm);
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}
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
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||||
|
@ -2732,7 +2738,7 @@ private:
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|||
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
if(nzimm) *(X+2) = *(X+2) + (int16_t)nzimm;
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||||
if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
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||||
else raise(0, 2);
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68);
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||||
|
@ -2841,7 +2847,7 @@ private:
|
|||
// execute instruction
|
||||
{
|
||||
uint8_t rs1_idx = rs1 + 8;
|
||||
*(X+rs1_idx) = *(X+rs1_idx) & (int8_t)imm;
|
||||
*(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
|
||||
}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
|
||||
|
@ -3013,7 +3019,7 @@ private:
|
|||
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
|
||||
pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
|
||||
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
||||
|
@ -3045,7 +3051,7 @@ private:
|
|||
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
|
||||
if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
|
||||
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
||||
|
@ -3077,7 +3083,7 @@ private:
|
|||
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
*NEXT_PC = *PC + 2;
|
||||
// execute instruction
|
||||
if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)imm;
|
||||
if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
|
||||
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
||||
|
|
Loading…
Reference in New Issue