DBT-RISE/DBT-RISE-TGC
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fix RVM description bugs

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This commit is contained in:
Eyck Jentzsch 2021-03-13 10:46:30 +00:00
parent 80057eef32
commit ff3fa19208
2 changed files with 8 additions and 8 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit eab89af46bd1d6485e150111db1612ce8dca984b
Subproject commit a5f12b0659ba668c2a8651bd23be19bab2bb6f12

14
src/vm/interp/vm_tgf_c.cpp
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@ -486,7 +486,7 @@ private:
// execute instruction
{
int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
if(rd != 0) *(X+rd) = *PC + 2;
if(rd != 0) *(X+rd) = *PC + 4;
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
}
// post execution stuff
@ -2155,7 +2155,7 @@ private:
// execute instruction
{
if(rd != 0) {
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
}
}
@ -2193,7 +2193,7 @@ private:
// execute instruction
{
if(rd != 0) {
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
}
@ -2231,8 +2231,8 @@ private:
// execute instruction
{
if(rd != 0) {
int64_t res = (int32_t)*(X+rs1) * (uint32_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
}
// post execution stuff
@ -2269,8 +2269,8 @@ private:
// execute instruction
{
if(rd != 0) {
uint64_t res = (uint32_t)*(X+rs1) * (uint32_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
}
// post execution stuff