updates templates for decoder in seperate class, adds again generated templates

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop

.clang-format

@@ -1,4 +1,3 @@
----
 Language:        Cpp
 # BasedOnStyle:  LLVM
 # should be in line with IndentWidth
@@ -13,8 +12,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
 AllowShortBlocksOnASingleLine: false
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: All
-AllowShortIfStatementsOnASingleLine: true
+AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: true
+AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
@@ -39,8 +38,8 @@ BreakBeforeTernaryOperators: true
 BreakConstructorInitializersBeforeComma: true
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit:     120
+ColumnLimit:     140
-CommentPragmas:  '^ IWYU pragma:'
+CommentPragmas:  '^( IWYU pragma:| @suppress)'
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
 ConstructorInitializerIndentWidth: 0
 ContinuationIndentWidth: 4
@@ -76,13 +75,13 @@ PenaltyBreakFirstLessLess: 120
 PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Right
+PointerAlignment: Left
 ReflowComments:  true
 SortIncludes:    true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
 SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: ControlStatements
+SpaceBeforeParens: Never
 SpaceInEmptyParentheses: false
 SpacesBeforeTrailingComments: 1
 SpacesInAngles:  false

.gitignore

@@ -1,5 +1,6 @@
 .DS_Store
 /*.il
+/.settings
 /avr-instr.html
 /blink.S
 /flash.*
@@ -14,7 +15,6 @@
 /*.ods
 /build*/
 /*.logs
-language.settings.xml
 /*.gtkw
 /Debug wo LLVM/
 /*.txdb
@@ -30,6 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
 /*.yaml
 /*.json

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

.settings/org.eclipse.cdt.codan.core.prefs

@@ -1,73 +0,0 @@
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-org.eclipse.cdt.codan.checkers.errreturnvalue=Error
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-org.eclipse.cdt.codan.checkers.nolinecomment=-Error
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-org.eclipse.cdt.codan.checkers.noreturn=Error
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.settings/org.eclipse.cdt.core.prefs

@@ -1,13 +0,0 @@
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.settings/org.eclipse.cdt.managedbuilder.core.prefs

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CMakeLists.txt

@@ -1,96 +1,123 @@
-cmake_minimum_required(VERSION 3.12)
+cmake_minimum_required(VERSION 3.18)
-###############################################################################
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
+
+# ##############################################################################
 #
-###############################################################################
+# ##############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
+include(flink)
 
 find_package(elfio QUIET)
-find_package(Boost COMPONENTS coroutine)
+find_package(jsoncpp)
-
+find_package(Boost COMPONENTS coroutine REQUIRED)
-if(WITH_LLVM)
-    if(DEFINED ENV{LLVM_HOME})
-        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-    endif(DEFINED ENV{LLVM_HOME})
-    find_package(LLVM REQUIRED CONFIG)
-    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
-endif()
-
-#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
-#set(CMAKE_MACOSX_RPATH ON)
-#set(CMAKE_SKIP_BUILD_RPATH FALSE)
-#set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
-#set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
-#set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
 
 add_subdirectory(softfloat)
 
-# library files
-FILE(GLOB TGC_SOURCES    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp) 
-FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
-
 set(LIB_SOURCES
+    src/iss/plugin/instruction_count.cpp
+    src/iss/arch/tgc5c.cpp
+    src/vm/interp/vm_tgc5c.cpp
     src/vm/fp_functions.cpp
-    src/plugin/instruction_count.cpp
+    src/vm/instruction_decoder.cpp
-    
+    src/iss/semihosting/semihosting.cpp
-    ${TGC_SOURCES}
-    ${TGC_VM_SOURCES}
 )
-if(TARGET RapidJSON)
+
-    list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
+if(WITH_TCC)
+    list(APPEND LIB_SOURCES
+        src/vm/tcc/vm_tgc5c.cpp
+    )
 endif()
 
 if(WITH_LLVM)
-	FILE(GLOB TGC_LLVM_SOURCES
+    list(APPEND LIB_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
+        src/vm/llvm/vm_tgc5c.cpp
+        src/vm/llvm/fp_impl.cpp
     )
-	list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
+endif()
+
+if(WITH_ASMJIT)
+    list(APPEND LIB_SOURCES
+        src/vm/asmjit/vm_tgc5c.cpp
+    )
+endif()
+
+# library files
+FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
+list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+
+foreach(FILEPATH ${GEN_ISS_SOURCES})
+    get_filename_component(CORE ${FILEPATH} NAME_WE)
+    string(TOUPPER ${CORE} CORE)
+    list(APPEND LIB_DEFINES CORE_${CORE})
+endforeach()
+
+message(STATUS "Core defines are ${LIB_DEFINES}")
+
+if(WITH_LLVM)
+    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()
 
 if(WITH_TCC)
-	FILE(GLOB TGC_TCC_SOURCES
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(WITH_ASMJIT)
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+endif()
+
+if(TARGET yaml-cpp::yaml-cpp)
+    list(APPEND LIB_SOURCES
+        src/iss/plugin/cycle_estimate.cpp
+        src/iss/plugin/instruction_count.cpp
     )
-	list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} ${LIB_SOURCES})
+add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
-# list code gen dependencies
-if(TARGET ${CORE_NAME}_cpp)
-    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
-endif()
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
+
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp Boost::coroutine)
+target_include_directories(${PROJECT_NAME} PUBLIC src)
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
-    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
+
-else()
+target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
+
-endif()
+# only re-export the include paths
-if(TARGET CONAN_PKG::elfio)
+get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
-    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
+target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
-elseif(TARGET elfio::elfio)
+get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
-    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+
-else()
+if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
-    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
-endif()
-if(TARGET lz4::lz4)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
-    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
-endif()
-if(TARGET RapidJSON)
-    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
 endif()
 
+target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
+
+if(TARGET yaml-cpp::yaml-cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
+    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
+endif()
+
+if(WITH_LLVM)
+    find_package(LLVM)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+
+    if(BUILD_SHARED_LIBS)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
+    endif()
+endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
     VERSION ${PROJECT_VERSION}
@@ -109,33 +136,54 @@ install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
     DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
     FILES_MATCHING # install only matched files
     PATTERN "*.h" # select header files
-        )
+)
-###############################################################################
+install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
+
+# ##############################################################################
 #
-###############################################################################
+# ##############################################################################
+set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
+
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
+endif()
+
 foreach(F IN LISTS TGC_SOURCES)
+    if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
         string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
         string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
         target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endif()
 endforeach()
 
-if(WITH_LLVM)
+# if(WITH_LLVM)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-endif()
+# endif()
-# Links the target exe against the libraries
+# if(WITH_TCC)
-target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+# endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
+
 if(TARGET Boost::program_options)
     target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
 else()
     target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
 endif()
+
 target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
-if (Tcmalloc_FOUND)
+
+if(Tcmalloc_FOUND)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
 
@@ -148,27 +196,57 @@ install(TARGETS tgc-sim
     PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
     INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
 )
-###############################################################################
-#
-###############################################################################
-project(dbt-rise-tgc_sc VERSION 1.0.0)
 
-include(SystemCPackage)
+if(BUILD_TESTING)
-if(SystemC_FOUND)
+    # ... CMake code to create tests ...
-    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    add_test(NAME tgc-sim-interp
+        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
+
+    if(WITH_TCC)
+        add_test(NAME tgc-sim-tcc
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
+    endif()
+
+    if(WITH_LLVM)
+        add_test(NAME tgc-sim-llvm
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
+    endif()
+
+    if(WITH_ASMJIT)
+        add_test(NAME tgc-sim-asmjit
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
+    endif()
+endif()
+
+# ##############################################################################
+#
+# ##############################################################################
+if(TARGET scc-sysc)
+    project(dbt-rise-tgc_sc VERSION 1.0.0)
+    set(LIB_SOURCES
+        src/sysc/core_complex.cpp
+        src/sysc/register_tgc_c.cpp
+    )
+    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
+    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
+    add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+
     foreach(F IN LISTS TGC_SOURCES)
+        if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
             string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
             string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
             target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    endforeach()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
-    if(WITH_LLVM)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
         endif()
+    endforeach()
 
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+
+    # if(WITH_LLVM)
+    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    # endif()
+    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
         VERSION ${PROJECT_VERSION}
         FRAMEWORK FALSE
@@ -184,4 +262,3 @@ if(SystemC_FOUND)
         INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
     )
 endif()
-

cmake/flink.cmake

@@ -0,0 +1,35 @@
+# according to https://github.com/horance-liu/flink.cmake/tree/master
+# SPDX-License-Identifier: Apache-2.0
+
+include(CMakeParseArguments)
+
+function(target_do_force_link_libraries target visibility lib)
+  if(MSVC)
+    target_link_libraries(${target} ${visibility} "/WHOLEARCHIVE:${lib}")
+  elseif(APPLE)
+    target_link_libraries(${target} ${visibility} -Wl,-force_load ${lib})
+  else()
+    target_link_libraries(${target} ${visibility} -Wl,--whole-archive ${lib} -Wl,--no-whole-archive)
+  endif()
+endfunction()
+
+function(target_force_link_libraries target)
+  cmake_parse_arguments(FLINK
+    ""
+    ""
+    "PUBLIC;INTERFACE;PRIVATE"
+    ${ARGN}
+  )
+  
+  foreach(lib IN LISTS FLINK_PUBLIC)
+    target_do_force_link_libraries(${target} PUBLIC ${lib})
+  endforeach()
+
+  foreach(lib IN LISTS FLINK_INTERFACE)
+    target_do_force_link_libraries(${target} INTERFACE ${lib})
+  endforeach()
+  
+  foreach(lib IN LISTS FLINK_PRIVATE)
+    target_do_force_link_libraries(${target} PRIVATE ${lib})
+  endforeach()
+endfunction()

contrib/instr/.gitignore

@@ -0,0 +1 @@
+/*.yaml

contrib/instr/TGC5C_instr.yaml

@@ -0,0 +1,624 @@
+
+RVI: 
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+    mask: 0b00000000000000000000000001111111
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contrib/pa/.gitignore

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+/results
+/cwr
+/*.xml

contrib/pa/README.md

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+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib/pa
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```

contrib/pa/build.tcl

@@ -16,7 +16,7 @@ namespace eval Specification {
                 set libdir "${install_dir}/lib64"
                 set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                 # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
             }
             default {
                puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"

contrib/pa/tgc_import.tcl

@@ -6,14 +6,11 @@ proc getScriptDirectory {} {
     set scriptFolder [file dirname $dispScriptFile]
     return $scriptFolder
 }
-if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
     set hardware /HARDWARE/HW/HW
-} else {
-    set hardware /HARDWARE
-}
 
 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -28,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
 
 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -38,13 +36,15 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
     ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
 
 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/pa/tgc_import_tb.tcl

@@ -0,0 +1,71 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
+::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
+::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
+::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
+::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
+::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml

gen_input/TGC5C.core_desc

@@ -0,0 +1,13 @@
+import "ISA/RVI.core_desc"
+import "ISA/RVM.core_desc"
+import "ISA/RVC.core_desc"
+
+Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned int MARCHID_VAL = 0x80000003;
+    }
+}

gen_input/TGC_C.core_desc

@@ -1,13 +0,0 @@
-import "RV32I.core_desc"
-import "RVM.core_desc"
-import "RVC.core_desc"
-
-Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
-    architectural_state {
-        XLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned MARCHID_VAL = 0x80000003;
-    }
-}

gen_input/templates/CORENAME.cpp.gtl

@@ -33,23 +33,24 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
+	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 %>
+// clang-format off
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const char*, ${registers.size()}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
@@ -62,15 +63,15 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    trap_state=0;
+    reg.trap_state=0;
-    icount=0;
+    reg.icount=0;
 }
 
 uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
-    return phys_addr_t(pc); // change logical address to physical address
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
 }
-
+// clang-format on

gen_input/templates/CORENAME.h.gtl

@@ -30,14 +30,12 @@
  *
  *******************************************************************************/
 <%
-import com.minres.coredsl.util.BigIntegerWithRadix
-
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    // regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
+    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     return regs
 }
 def getRegisterOffsets(){
@@ -57,15 +55,12 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    if(val instanceof BigIntegerWithRadix)
+    return val.toString()+'ULL'
-        return ((BigIntegerWithRadix)val).toCString()
-    else
-        return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-
+// clang-format off
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -80,18 +75,18 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     constexpr static char const* const core_type = "${coreDef.name}";
     
-    static constexpr std::array<const char*, ${registers.size}> reg_names{
+    static constexpr std::array<const char*, ${registers.size()}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
  
-    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
+    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
 
     enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
 
     constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
     enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -104,19 +99,19 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
+    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
         {${getRegisterSizes().join(',')}}};
 
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
         {${getRegisterOffsets().join(',')}}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
     
-    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };
@@ -136,25 +131,17 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     uint8_t* get_regs_base_ptr() override;
 
-    inline uint64_t get_icount() { return icount; }
+    inline uint64_t get_icount() { return reg.icount; }
 
     inline bool should_stop() { return interrupt_sim; }
 
     inline uint64_t stop_code() { return interrupt_sim; }
 
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
     virtual phys_addr_t virt2phys(const iss::addr_t& addr);
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
-    inline uint32_t get_last_branch() { return last_branch; }
+    inline uint32_t get_last_branch() { return reg.last_branch; }
 
 
 #pragma pack(push, 1)
@@ -162,14 +149,14 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
         registers.each { reg -> if(reg.size>0) {%> 
         uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
         }}%>
-    } reg;
-#pragma pack(pop)
         uint32_t trap_state = 0, pending_trap = 0;
         uint64_t icount = 0;
         uint64_t cycle = 0;
         uint64_t instret = 0;
         uint32_t instruction = 0;
         uint32_t last_branch = 0;
+    } reg;
+#pragma pack(pop)
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;
@@ -187,3 +174,4 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
+// clang-format on

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -8,9 +8,14 @@
         instrGroups[groupName]+=it;
     }
     instrGroups
-}%><%getInstructionGroups().each{name, instrList -> %>
+}%><%int index = 0; getInstructionGroups().each{name, instrList -> %>
-${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
+${name}: <% instrList.each { %>
-  - ${it.instruction.name}:
+  ${it.instruction.name}:
+    index: ${index++}
     encoding: ${it.encoding}
-    mask: ${it.mask}<%}}%>
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}%>
+    size:   ${it.length}
+    branch:   ${it.modifiesPC}
+    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
 

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <sysc/iss_factory.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <sysc/sc_core_adapter.h>
+#include <sysc/core_complex.h>
+#include <array>
+<%
+def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
+%>
+namespace iss {
+namespace interp {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#if defined(WITH_LLVM)
+namespace llvm {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_TCC)
+namespace tcc {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+#if defined(WITH_ASMJIT)
+namespace asmjit {
+using namespace sysc;
+volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        }),
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
+        iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
+        })<%}%>
+};
+}
+#endif
+}
+// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -0,0 +1,344 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/asmjit/vm_base.h>
+#include <asmjit/asmjit.h>
+#include <util/logging.h>
+#include <vm/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace asmjit {
+
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::asmjit;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::asmjit::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using mem_type_e = typename super::mem_type_e;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using super::get_ptr_for;
+    using super::get_reg_for;
+    using super::get_reg_for_Gp;
+    using super::load_reg_from_mem;
+    using super::load_reg_from_mem_Gp;
+    using super::write_reg_to_mem;
+    using super::gen_read_mem;
+    using super::gen_write_mem;
+    using super::gen_wait;
+    using super::gen_leave;
+    using super::gen_sync;
+    using super::gen_set_tval;
+   
+    using this_class = vm_impl<ARCH>;
+    using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
+
+    continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    void gen_block_prologue(jit_holder& jh) override;
+    void gen_block_epilogue(jit_holder& jh) override;
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    void gen_instr_prologue(jit_holder& jh);
+    void gen_instr_epilogue(jit_holder& jh);
+    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
+
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    } 
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate disass */
+            <%instr.disass.eachLine{%>
+            ${it}<%}%>
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
+        }
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, ${idx});
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc+${instr.length/8};
+        mov(cc, jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        gen_sync(jh, POST_SYNC, ${idx});
+        gen_instr_epilogue(jh);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
+        x86::Compiler& cc = jh.cc;
+        if(this->disass_enabled){          
+            auto mnemonic = std::string("illegal_instruction");
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+        }
+        cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
+        gen_sync(jh, PRE_SYNC, instr_descr.size());
+        mov(cc, jh.pc, pc.val);
+        gen_set_tval(jh, instr);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        mov(cc, jh.next_pc, pc.val);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_raise(jh, 0, 2);
+        gen_sync(jh, POST_SYNC, instr_descr.size());
+        gen_instr_epilogue(jh);
+        return BRANCH;
+    }
+};
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok)
+        throw trap_access(TRAP_ID, pc.val);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001)
+        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) 
+        f = &this_class::illegal_instruction;
+    return (this->*f)(pc, instr, jh);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_prologue");
+
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
+
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_epilogue");
+    x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cmp(cc, current_trap_state, 0);
+    cc.jne(jh.trap_entry);
+    cc.inc(get_ptr_for(jh, traits::ICOUNT));
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
+    jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
+    jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
+    jh.tval = get_reg_Gp(jh.cc, 64, false);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
+    x86::Compiler& cc = jh.cc;
+    cc.comment("//gen_block_epilogue");
+    cc.ret(jh.next_pc);
+
+    cc.bind(jh.trap_entry);
+    this->write_back(jh);
+
+    x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
+    mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+
+    x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
+    mov(cc, current_pc, get_ptr_for(jh, traits::PC));
+
+    cc.comment("//enter trap call;");
+    InvokeNode* call_enter_trap;
+    cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
+    call_enter_trap->setArg(0, jh.arch_if_ptr);
+    call_enter_trap->setArg(1, current_trap_state);
+    call_enter_trap->setArg(2, current_pc);
+    call_enter_trap->setArg(3, jh.tval);
+
+    x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
+    mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
+    mov(cc, jh.next_pc, current_next_pc);
+
+    mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
+    cc.ret(jh.next_pc);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
+    auto& cc = jh.cc;
+    cc.comment("//gen_raise");
+    auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
+    mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
+    mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+}
+
+} // namespace tgc5c
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace asmjit
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,23 +30,23 @@
  *
  *******************************************************************************/
 <%
-import com.minres.coredsl.util.BigIntegerWithRadix
-
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-#include "../fp_functions.h"
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
+#include <vm/fp_functions.h>
 #include <util/logging.h>
-#include <sstream>
 #include <boost/coroutine2/all.hpp>
 #include <functional>
+#include <exception>
+#include <vector>
+#include <sstream>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -63,6 +63,10 @@ using namespace iss::arch;
 using namespace iss::debugger;
 using namespace std::placeholders;
 
+struct memory_access_exception : public std::exception{
+    memory_access_exception(){}
+};
+
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
     using traits = arch::traits<ARCH>;
@@ -73,6 +77,7 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
     
     vm_impl();
 
@@ -92,37 +97,15 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
 
-    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum {
-        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
-        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
-    };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        typename arch::traits<ARCH>::opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.trap_state = trap_val;
+        this->core.reg.trap_state = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
     }
 
     inline void leave(unsigned lvl){
@@ -133,48 +116,17 @@ protected:
         this->core.wait_until(type);
     }
 
+    inline void set_tval(uint64_t new_tval){
+        tval = new_tval;
+    }
+
+    uint64_t fetch_count{0};
+    uint64_t tval{0};
+
     using yield_t = boost::coroutines2::coroutine<void>::push_type;
     using coro_t = boost::coroutines2::coroutine<void>::pull_type;
     std::vector<coro_t> spawn_blocks;
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -183,6 +135,7 @@ protected:
     }
     
     inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
         for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
              if(*it){
                  (*it)();
@@ -193,34 +146,102 @@ protected:
 <%functions.each{ it.eachLine { %>
     ${it}<%}%>
 <%}%>
+
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
+    struct instruction_descriptor {
         size_t length;
         uint32_t value;
         uint32_t mask;
         typename arch::traits<ARCH>::opcode_e op;
     };
+    struct decoding_tree_node{
+        std::vector<instruction_descriptor> instrs;
+        std::vector<decoding_tree_node*> children;
+        uint32_t submask = std::numeric_limits<uint32_t>::max();
+        uint32_t value;
+        decoding_tree_node(uint32_t value) : value(value){}
+    };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    decoding_tree_node* root {nullptr};
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
 
-    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        auto phys_pc = this->core.v2p(pc);
+        if(this->core.has_mmu()) {
-        //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+            auto phys_pc = this->core.virt2phys(pc);
-        //    if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
+//            if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        //    if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
+//                if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
-        //        if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
+//                if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
-        //} else {
+//                    if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
-            if (this->core.read(phys_pc, 4, data) != iss::Ok)  return iss::Err;
+//                        return iss::Err;
-        //}
+//            } else {
+                if (this->core.read(phys_pc, 4, data) != iss::Ok)
+                    return iss::Err;
+//            }
+        } else {
+            if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
+                return iss::Err;
+
+        }
         return iss::Ok;
     }
+    
+    void populate_decoding_tree(decoding_tree_node* root){
+        //create submask
+        for(auto instr: root->instrs){
+            root->submask &= instr.mask;
+        }
+        //put each instr according to submask&encoding into children
+        for(auto instr: root->instrs){
+            bool foundMatch = false;
+            for(auto child: root->children){
+                //use value as identifying trait
+                if(child->value == (instr.value&root->submask)){
+                    child->instrs.push_back(instr);
+                    foundMatch = true;
+                }
+            }
+            if(!foundMatch){
+                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
+                child->instrs.push_back(instr);
+                root->children.push_back(child);
+            }
+        }
+        root->instrs.clear();
+        //call populate_decoding_tree for all children
+        if(root->children.size() >1)
+            for(auto child: root->children){
+                populate_decoding_tree(child);      
+            }
+        else{
+            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
+            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
+            return instr1.mask > instr2.mask;
+            }); 
+        }
+    }
+
+    typename arch::traits<ARCH>::opcode_e  decode_instr(decoding_tree_node* node, code_word_t word){
+        if(!node->children.size()){
+            if(node->instrs.size() == 1) return node->instrs[0].op;
+            for(auto instr : node->instrs){
+                if((instr.mask&word) == instr.value) return instr.op;
+            }
+        }
+        else{
+            for(auto child : node->children){
+                if (child->value == (node->submask&word)){
+                    return decode_instr(child, word);
+                }  
+            }  
+        }
+        return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+    }
 };
 
 template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
@@ -247,20 +268,19 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    unsigned id=0;
+    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
-    for (auto instr : instr_descr) {
+    for(auto instr:instr_descr){
-        auto quadrant = instr.value & 0x3;
+        root->instrs.push_back(instr);
-        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-    }
-    for(auto& lut: qlut){
-        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-            return bit_count(a.mask) > bit_count(b.mask);
-        });
     }
+    populate_decoding_tree(root);
 }
 
-inline bool is_count_limit_enabled(finish_cond_e cond){
+inline bool is_icount_limit_enabled(finish_cond_e cond){
-    return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
+    return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
+}
+
+inline bool is_fcount_limit_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
 }
 
 inline bool is_jump_to_self_enabled(finish_cond_e cond){
@@ -268,44 +288,39 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
-    for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.id;
-    }
-    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
-}
-
-template <typename ARCH>
-typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     auto pc=start;
-    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-    auto& trap_state = this->core.trap_state;
+    auto& trap_state = this->core.reg.trap_state;
-    auto& icount = this->core.icount;
+    auto& icount =  this->core.reg.icount;
-    auto& cycle = this->core.cycle;
+    auto& cycle =  this->core.reg.cycle;
-    auto& instret = this->core.instret;
+    auto& instret =  this->core.reg.instret;
-    auto& instr = this->core.instruction;
+    auto& instr =  this->core.reg.instruction;
     // we fetch at max 4 byte, alignment is 2
     auto *const data = reinterpret_cast<uint8_t*>(&instr);
 
     while(!this->core.should_stop() &&
-            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
+            !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
+            !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
+        fetch_count++;
         if(fetch_ins(pc, data)!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = decode_inst_id(instr);
+            auto inst_id = decode_instr(root, instr);
             // pre execution stuff
+             this->core.reg.last_branch = 0;
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            try{
                 switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
                 case arch::traits<ARCH>::opcode_e::${instr.name}: {
                     <%instr.fields.eachLine{%>${it}
                     <%}%>if(this->disass_enabled){
-		            /* generate console output when executing the command */
+                        /* generate console output when executing the command */<%instr.disass.eachLine{%>
-		            <%instr.disass.eachLine{%>${it}
+                        ${it}<%}%>
-		            <%}%>
                     }
                     // used registers<%instr.usedVariables.each{ k,v->
                     if(v.isArray) {%>
@@ -313,21 +328,26 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
                     <%}}%>// calculate next pc value
                     *NEXT_PC = *PC + ${instr.length/8};
-		        // execute instruction
+                    // execute instruction<%instr.behavior.eachLine{%>
-		        <%instr.behavior.eachLine{%>${it}
+                    ${it}<%}%>
-		        <%}%>TRAP_${instr.name}:break;
+                    break;
                 }// @suppress("No break at end of case")<%}%>
                 default: {
                     *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
                     raise(0,  2);
                 }
                 }
+            }catch(memory_access_exception& e){}
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
             // trap check
             if(trap_state!=0){
-                super::core.enter_trap(trap_state, pc.val, instr);
+                //In case of Instruction address misaligned (cause = 0 and trapid = 0) need the targeted addr (in tval)
+                auto mcause = (trap_state>>16) & 0xff; 
+                super::core.enter_trap(trap_state, pc.val, mcause ? instr:tval);
             } else {
                 icount++;
                 instret++;
@@ -335,13 +355,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             cycle++;
             pc.val=*NEXT_PC;
             this->core.reg.PC = this->core.reg.NEXT_PC;
-            this->core.trap_state = this->core.pending_trap;
+            this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
     }
     return pc;
 }
 
-}
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -351,3 +371,34 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace interp
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+// clang-format off
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
+#include <iss/iss.h>
+#include <iss/llvm/vm_base.h>
+#include <util/logging.h>
+#include <vm/instruction_decoder.h>
+
+#ifndef FMT_HEADER_ONLY
+#define FMT_HEADER_ONLY
+#endif
+#include <fmt/format.h>
+
+#include <array>
+#include <iss/debugger/riscv_target_adapter.h>
+
+namespace iss {
+namespace llvm {
+namespace fp_impl {
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
+}
+
+namespace ${coreDef.name.toLowerCase()} {
+using namespace ::llvm;
+using namespace iss::arch;
+using namespace iss::debugger;
+
+template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
+public:
+    using traits = arch::traits<ARCH>;
+    using super = typename iss::llvm::vm_base<ARCH>;
+    using virt_addr_t = typename super::virt_addr_t;
+    using phys_addr_t = typename super::phys_addr_t;
+    using code_word_t = typename super::code_word_t;
+    using addr_t = typename super::addr_t;
+
+    vm_impl();
+
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
+
+    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
+
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
+        debugger_if::dbg_enabled = true;
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
+        return vm_base<ARCH>::tgt_adapter;
+    }
+
+protected:
+    using vm_base<ARCH>::get_reg_ptr;
+
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+
+    template <typename T> inline ConstantInt *size(T type) {
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
+    }
+
+    void setup_module(Module* m) override {
+        super::setup_module(m);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
+    }
+
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
+        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
+    }
+
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
+
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
+    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
+    void gen_leave_trap(unsigned lvl);
+    void gen_wait(unsigned type);
+    void set_tval(uint64_t new_tval);
+    void set_tval(Value* new_tval);
+    void gen_trap_behavior(BasicBlock *) override;
+    void gen_instr_prologue();
+    void gen_instr_epilogue(BasicBlock *bb);
+
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
+        return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
+    }
+
+    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+                                                           this->get_type(traits::XLEN));
+        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
+    }
+
+    // some compile time constants
+
+    using this_class = vm_impl<ARCH>;
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }   
+
+private:
+    /****************************************************************************
+     * start opcode definitions
+     ****************************************************************************/
+    struct instruction_descriptor {
+        uint32_t length;
+        uint32_t value;
+        uint32_t mask;
+        compile_func op;
+    };
+
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
+         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+    }};
+
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
+            ${it}<%}%>
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,${idx});
+        
+        this->gen_set_pc(pc, traits::PC);
+        this->set_tval(instr);
+        pc=pc+ ${instr.length/8};
+        this->gen_set_pc(pc, traits::NEXT_PC);
+        
+        this->gen_instr_prologue();
+        /*generate behavior*/
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        this->gen_sync(POST_SYNC, ${idx});
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    std::tuple<continuation_e, BasicBlock *> illegal_instruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+        if(this->disass_enabled){
+            auto mnemonic = std::string("illegal_instruction");
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
+                                   get_reg_ptr(traits::PC), true);
+        this->builder.CreateStore(
+            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
+                                     this->gen_const(64U, 1)),
+            get_reg_ptr(traits::ICOUNT), true);
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        this->set_tval(instr);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        bb = this->leave_blk;
+        this->gen_instr_epilogue(bb);
+        this->builder.CreateBr(bb);
+        return std::make_tuple(BRANCH, nullptr);
+    }    
+};
+
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
+}
+
+template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
+
+template <typename ARCH>
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
+: vm_base<ARCH>(core, core_id, cluster_id)
+, instr_decoder([this]() {
+        std::vector<generic_instruction_descriptor> g_instr_descr;
+        g_instr_descr.reserve(instr_descr.size());
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
+            g_instr_descr.push_back(new_instr_descr);
+        }
+        return std::move(g_instr_descr);
+    }()) {}
+
+template <typename ARCH>
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
+    // we fetch at max 4 byte, alignment is 2
+    enum {TRAP_ID=1<<16};
+    code_word_t instr = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
+    phys_addr_t paddr(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, data);
+    if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    // curr pc on stack
+    ++inst_cnt;
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
+    if (f == nullptr) {
+        f = &this_class::illegal_instruction;
+    }
+    return (this->*f)(pc, instr, this_block);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+    this->builder.SetInsertPoint(leave_blk);
+    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
+    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+}
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
+    this->builder.CreateCall(this->mod->getFunction("wait"), args);
+}
+
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(uint64_t tval) {
+    auto tmp_tval = this->gen_const(64, tval);
+    this->set_tval(tmp_tval);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::set_tval(Value* new_tval) {
+    this->builder.CreateStore(this->gen_ext(new_tval, 64, false), this->tval);
+}
+template <typename ARCH> 
+void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+    this->builder.SetInsertPoint(trap_blk);
+    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    auto *cur_pc_val = this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), true);
+    std::vector<Value *> args{this->core_ptr,
+                                this->adj_to64(trap_state_val),
+                                this->adj_to64(cur_pc_val),
+                              this->adj_to64(this->builder.CreateLoad(this->get_type(64),this->tval))};
+    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
+    this->builder.CreateStore(this->gen_const(32U, static_cast<int>(UNKNOWN_JUMP)), get_reg_ptr(traits::LAST_BRANCH), false);
+
+    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
+    this->builder.CreateRet(trap_addr_val);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue() {
+    auto* trap_val =
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PENDING_TRAP), get_reg_ptr(arch::traits<ARCH>::PENDING_TRAP));
+    this->builder.CreateStore(trap_val, get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), false);
+}
+            
+
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
+    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
+    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          target_bb, this->trap_blk, 1);
+    this->builder.SetInsertPoint(target_bb);
+    // update icount
+    auto* icount_val = this->builder.CreateAdd(
+        this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::ICOUNT), get_reg_ptr(arch::traits<ARCH>::ICOUNT)), this->gen_const(64U, 1));
+    this->builder.CreateStore(icount_val, get_reg_ptr(arch::traits<ARCH>::ICOUNT), false);
+}
+
+} // namespace ${coreDef.name.toLowerCase()}
+
+template <>
+std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
+    return std::unique_ptr<vm_if>(ret);
+}
+} // namespace llvm
+} // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/llvm/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/llvm/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/llvm/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -1,325 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
-#include <iss/iss.h>
-#include <iss/llvm/vm_base.h>
-#include <util/logging.h>
-
-#ifndef FMT_HEADER_ONLY
-#define FMT_HEADER_ONLY
-#endif
-#include <fmt/format.h>
-
-#include <array>
-#include <iss/debugger/riscv_target_adapter.h>
-
-namespace iss {
-namespace llvm {
-namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
-}
-
-namespace ${coreDef.name.toLowerCase()} {
-using namespace ::llvm;
-using namespace iss::arch;
-using namespace iss::debugger;
-
-template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
-public:
-    using super = typename iss::llvm::vm_base<ARCH>;
-    using virt_addr_t = typename super::virt_addr_t;
-    using phys_addr_t = typename super::phys_addr_t;
-    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-
-    vm_impl();
-
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
-
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
-
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
-        debugger_if::dbg_enabled = true;
-        if (vm_base<ARCH>::tgt_adapter == nullptr)
-            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
-        return vm_base<ARCH>::tgt_adapter;
-    }
-
-protected:
-    using vm_base<ARCH>::get_reg_ptr;
-
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
-
-    template <typename T> inline ConstantInt *size(T type) {
-        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
-    }
-
-    void setup_module(Module* m) override {
-        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
-    }
-
-    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
-    }
-
-    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
-
-    void gen_leave_behavior(BasicBlock *leave_blk) override;
-
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-
-    void gen_leave_trap(unsigned lvl);
-
-    void gen_wait(unsigned type);
-
-    void gen_trap_behavior(BasicBlock *) override;
-
-    void gen_trap_check(BasicBlock *bb);
-
-    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
-        return this->builder.CreateLoad(get_reg_ptr(i), false);
-    }
-
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
-                                                           this->get_type(traits<ARCH>::XLEN));
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
-    }
-
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
-
-    using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
-                                                                                  code_word_t instr,
-                                                                                  BasicBlock *bb);
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-	std::array<compile_func *, 4> qlut;
-
-	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
-
-private:
-    /****************************************************************************
-     * start opcode definitions
-     ****************************************************************************/
-    struct InstructionDesriptor {
-        size_t length;
-        uint32_t value;
-        uint32_t mask;
-        compile_func op;
-    };
-
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
-         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
-    }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
-    	${it}<%}%>
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
-		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
-                                   get_reg_ptr(traits<ARCH>::PC), true);
-        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
-                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->gen_raise_trap(0, 2);     // illegal instruction trap
-		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        this->gen_trap_check(this->leave_blk);
-        return std::make_tuple(BRANCH, nullptr);
-    }
-};
-
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
-}
-
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
-
-template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
-    }
-}
-
-template <typename ARCH>
-std::tuple<continuation_e, BasicBlock *>
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
-    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-    // curr pc on stack
-    ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
-    if (f == nullptr) {
-        f = &this_class::illegal_intruction;
-    }
-    return (this->*f)(pc, insn, this_block);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
-    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
-}
-
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
-    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
-    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateRet(trap_addr_val);
-}
-
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
-    this->gen_cond_branch(this->builder.CreateICmp(
-                              ICmpInst::ICMP_EQ, v,
-                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          bb, this->trap_blk, 1);
-}
-
-} // namespace ${coreDef.name.toLowerCase()}
-
-template <>
-std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
-    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
-    return std::unique_ptr<vm_if>(ret);
-}
-} // namespace llvm
-} // namespace iss

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2020 MINRES Technologies GmbH
+ * Copyright (C) 2020-2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,15 +29,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/tcc/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
+#include <vm/instruction_decoder.h>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -55,10 +55,12 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
     using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
+    using mem_type_e  = typename traits::mem_type_e;    
     using addr_t      = typename super::addr_t;
     using tu_builder  = typename super::tu_builder;
 
@@ -82,7 +84,7 @@ protected:
     using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
     void setup_module(std::string m) override {
         super::setup_module(m);
@@ -98,16 +100,20 @@ protected:
 
     void gen_wait(tu_builder& tu, unsigned type);
 
+    inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
+
+    inline void gen_set_tval(tu_builder& tu, value new_tval);
+
     inline void gen_trap_check(tu_builder& tu) {
         tu("if(*trap_state!=0) goto trap_entry;");
     }
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
         switch(reg_num){
-        case traits<ARCH>::NEXT_PC:
+        case traits::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
-        case traits<ARCH>::PC:
+        case traits::PC:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
@@ -119,167 +125,158 @@ protected:
         }
     }
 
-    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
     
-    std::array<compile_func, LUT_SIZE> lut;
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-
+    inline S sext(U from) {
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
+        auto mask = (1ULL<<W) - 1;
-    std::array<compile_func, LUT_SIZE> lut_11;
+        auto sign_mask = 1ULL<<(W-1);
-
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    std::array<compile_func *, 4> qlut;
-
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
     }
 
 private:
     /****************************************************************************
      * start opcode definitions
      ****************************************************************************/
-    struct InstructionDesriptor {
+    struct instruction_descriptor {
-        size_t length;
+        uint32_t length;
         uint32_t value;
         uint32_t mask;
         compile_func op;
     };
 
-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
 
+    //needs to be declared after instr_descr
+    decoder instr_decoder;
+
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+        tu("${instr.name}_{:#010x}:", pc.val);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
         }
+        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
+        pc=pc+ ${instr.length/8};
+        gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu.open_scope();
+        this->gen_set_tval(tu, instr);
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        tu.close_scope();
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);        
+        return returnValue;
+    }
     <%}%>
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
         vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
+        }
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         gen_raise_trap(tu, 0, 2);     // illegal instruction trap
+        this->gen_set_tval(tu, instr);
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = insn;
+    volatile CODE_WORD x = instr;
-    insn = 2 * x;
+    instr = 2 * x;
 }
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
-: vm_base<ARCH>(core, core_id, cluster_id) {
+: vm_base<ARCH>(core, core_id, cluster_id)
-    qlut[0] = lut_00.data();
+, instr_decoder([this]() {
-    qlut[1] = lut_01.data();
+        std::vector<generic_instruction_descriptor> g_instr_descr;
-    qlut[2] = lut_10.data();
+        g_instr_descr.reserve(instr_descr.size());
-    qlut[3] = lut_11.data();
+        for (uint32_t i = 0; i < instr_descr.size(); ++i) {
-    for (auto instr : instr_descr) {
+            generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
-        auto quantrant = instr.value & 0x3;
+            g_instr_descr.push_back(new_instr_descr);
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
         }
-}
+        return std::move(g_instr_descr);
+    }()) {}
 
 template <typename ARCH>
 std::tuple<continuation_e>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
+    code_word_t instr = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
     phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
+    if(this->core.has_mmu())
-    paddr = this->core.v2p(pc);
+        paddr = this->core.virt2phys(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+    //TODO: re-add page handling
-        auto res = this->core.read(paddr, 2, data);
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
     if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//    }
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-        }
-    } else {
-        auto res = this->core.read(paddr, 4, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
-    auto lut_val = extract_fields(insn);
+    uint32_t inst_index = instr_decoder.decode_instr(instr);
-    auto f = qlut[insn & 0x3][lut_val];
+    compile_func f = nullptr;
+    if(inst_index < instr_descr.size())
+        f = instr_descr[inst_index].op;
     if (f == nullptr) {
-        f = &this_class::illegal_intruction;
+        f = &this_class::illegal_instruction;
     }
-    return (this->*f)(pc, insn, tu);
+    return (this->*f)(pc, instr, tu);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
+    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
 }
 
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
+    tu(fmt::format("tval = {};", new_tval));
+}
+template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
+    tu(fmt::format("tval = {};", new_tval.str));
+}
+
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc);");
+    this->gen_sync(tu, POST_SYNC, -1);    
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
+    tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
     tu("return *next_pc;");
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -287,5 +284,36 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-}
+} // namesapce tcc
 } // namespace iss
+
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
+namespace iss {
+namespace {
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
+}
+}
+// clang-format on

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-

incl/iss/arch/.gitignore

@@ -1 +0,0 @@
-/tgc_*.h

incl/iss/arch/tgc_c.h

@@ -1,273 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#ifndef _TGC_C_H_
-#define _TGC_C_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct tgc_c;
-
-template <> struct traits<tgc_c> {
-
-    constexpr static char const* const core_type = "TGC_C";
-    
-    static constexpr std::array<const char*, 36> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
- 
-    static constexpr std::array<const char*, 36> reg_aliases{
-        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
-
-    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, 36> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32}};
-
-    static constexpr std::array<const uint32_t, 36> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, CSR, FENCE, RES };
-    
-    enum class opcode_e : unsigned short {
-        LUI = 0,
-        AUIPC = 1,
-        JAL = 2,
-        JALR = 3,
-        BEQ = 4,
-        BNE = 5,
-        BLT = 6,
-        BGE = 7,
-        BLTU = 8,
-        BGEU = 9,
-        LB = 10,
-        LH = 11,
-        LW = 12,
-        LBU = 13,
-        LHU = 14,
-        SB = 15,
-        SH = 16,
-        SW = 17,
-        ADDI = 18,
-        SLTI = 19,
-        SLTIU = 20,
-        XORI = 21,
-        ORI = 22,
-        ANDI = 23,
-        SLLI = 24,
-        SRLI = 25,
-        SRAI = 26,
-        ADD = 27,
-        SUB = 28,
-        SLL = 29,
-        SLT = 30,
-        SLTU = 31,
-        XOR = 32,
-        SRL = 33,
-        SRA = 34,
-        OR = 35,
-        AND = 36,
-        FENCE = 37,
-        ECALL = 38,
-        EBREAK = 39,
-        URET = 40,
-        SRET = 41,
-        MRET = 42,
-        WFI = 43,
-        DRET = 44,
-        CSRRW = 45,
-        CSRRS = 46,
-        CSRRC = 47,
-        CSRRWI = 48,
-        CSRRSI = 49,
-        CSRRCI = 50,
-        FENCE_I = 51,
-        MUL = 52,
-        MULH = 53,
-        MULHSU = 54,
-        MULHU = 55,
-        DIV = 56,
-        DIVU = 57,
-        REM = 58,
-        REMU = 59,
-        CADDI4SPN = 60,
-        CLW = 61,
-        CSW = 62,
-        CADDI = 63,
-        CNOP = 64,
-        CJAL = 65,
-        CLI = 66,
-        CLUI = 67,
-        CADDI16SP = 68,
-        __reserved_clui = 69,
-        CSRLI = 70,
-        CSRAI = 71,
-        CANDI = 72,
-        CSUB = 73,
-        CXOR = 74,
-        COR = 75,
-        CAND = 76,
-        CJ = 77,
-        CBEQZ = 78,
-        CBNEZ = 79,
-        CSLLI = 80,
-        CLWSP = 81,
-        CMV = 82,
-        CJR = 83,
-        __reserved_cmv = 84,
-        CADD = 85,
-        CJALR = 86,
-        CEBREAK = 87,
-        CSWSP = 88,
-        DII = 89,
-        MAX_OPCODE
-    };
-};
-
-struct tgc_c: public arch_if {
-
-    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
-    using reg_t =  typename traits<tgc_c>::reg_t;
-    using addr_t = typename traits<tgc_c>::addr_t;
-
-    tgc_c();
-    ~tgc_c();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-
-    inline uint64_t get_icount() { return icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return last_branch; }
-
-
-#pragma pack(push, 1)
-    struct TGC_C_regs { 
-        uint32_t X0 = 0; 
-        uint32_t X1 = 0; 
-        uint32_t X2 = 0; 
-        uint32_t X3 = 0; 
-        uint32_t X4 = 0; 
-        uint32_t X5 = 0; 
-        uint32_t X6 = 0; 
-        uint32_t X7 = 0; 
-        uint32_t X8 = 0; 
-        uint32_t X9 = 0; 
-        uint32_t X10 = 0; 
-        uint32_t X11 = 0; 
-        uint32_t X12 = 0; 
-        uint32_t X13 = 0; 
-        uint32_t X14 = 0; 
-        uint32_t X15 = 0; 
-        uint32_t X16 = 0; 
-        uint32_t X17 = 0; 
-        uint32_t X18 = 0; 
-        uint32_t X19 = 0; 
-        uint32_t X20 = 0; 
-        uint32_t X21 = 0; 
-        uint32_t X22 = 0; 
-        uint32_t X23 = 0; 
-        uint32_t X24 = 0; 
-        uint32_t X25 = 0; 
-        uint32_t X26 = 0; 
-        uint32_t X27 = 0; 
-        uint32_t X28 = 0; 
-        uint32_t X29 = 0; 
-        uint32_t X30 = 0; 
-        uint32_t X31 = 0; 
-        uint32_t PC = 0; 
-        uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0; 
-        uint32_t DPC = 0;
-    } reg;
-#pragma pack(pop)
-    uint32_t trap_state = 0, pending_trap = 0;
-    uint64_t icount = 0;
-    uint64_t cycle = 0;
-    uint64_t instret = 0;
-    uint32_t instruction = 0;
-    uint32_t last_branch = 0;
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-    uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _TGC_C_H_ */

incl/iss/arch/tgc_mapper.h

@@ -1,43 +0,0 @@
-#ifndef _ISS_ARCH_TGC_MAPPER_H
-#define _ISS_ARCH_TGC_MAPPER_H
-
-#include "riscv_hart_m_p.h"
-#include "tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_B
-#include "riscv_hart_m_p.h"
-#include "tgc_b.h"
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#endif
-#ifdef CORE_TGC_C_XRB_NN
-#include "riscv_hart_m_p.h"
-#include "tgc_c_xrb_nn.h"
-using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
-#endif
-#ifdef CORE_TGC_D
-#include "riscv_hart_mu_p.h"
-#include "tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_D_XRB_MAC
-#include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_mac.h"
-using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-#include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_nn.h"
-using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_E
-#include "riscv_hart_mu_p.h"
-#include "tgc_e.h"
-using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_X
-#include "riscv_hart_mu_p.h"
-#include "tgc_x.h"
-using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
-#endif
-
-#endif

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-include(Common)
+#include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)
@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat ${LIB_SOURCES})
+add_library(softfloat STATIC ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)

softfloat/build/Linux-386-GCC/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-386-SSE2-GCC/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-ARM-VFPv2-GCC/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 //#define INLINE inline
 #define INLINE static
@@ -48,10 +48,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC__
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #endif
 #include "opts-GCC.h"
-

softfloat/build/Win32-MinGW/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Win32-SSE2-MinGW/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #include "opts-GCC.h"
-

softfloat/build/Win64-MinGW-w64/platform.h

@@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 =============================================================================*/
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define LITTLEENDIAN 1
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #ifdef __GNUC_STDC_INLINE__
 #define INLINE inline
 #else
@@ -47,8 +47,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
 #include "opts-GCC.h"
-

softfloat/build/template-FAST_INT64/platform.h

@@ -37,14 +37,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // Edit lines marked with `==>'.  See "SoftFloat-source.html".
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-==> #define LITTLEENDIAN 1
+== > #define LITTLEENDIAN 1
 
-/*----------------------------------------------------------------------------
+    /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+     *----------------------------------------------------------------------------*/
-==> #define INLINE inline
+    == > #define INLINE inline
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-==> #define THREAD_LOCAL _Thread_local
 
+    /*----------------------------------------------------------------------------
+     *----------------------------------------------------------------------------*/
+    == > #define THREAD_LOCAL _Thread_local

softfloat/build/template-not-FAST_INT64/platform.h

@@ -37,14 +37,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // Edit lines marked with `==>'.  See "SoftFloat-source.html".
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-==> #define LITTLEENDIAN 1
+== > #define LITTLEENDIAN 1
 
-/*----------------------------------------------------------------------------
+    /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+     *----------------------------------------------------------------------------*/
-==> #define INLINE inline
+    == > #define INLINE inline
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-==> #define THREAD_LOCAL _Thread_local
 
+    /*----------------------------------------------------------------------------
+     *----------------------------------------------------------------------------*/
+    == > #define THREAD_LOCAL _Thread_local

softfloat/source/8086-SSE/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -62,12 +62,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define i64_fromPosOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromPosOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
-#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
-#define i64_fromNaN          (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
 
 /*----------------------------------------------------------------------------
 | "Common NaN" structure, used to transfer NaN representations from one format
@@ -92,7 +92,7 @@ struct commonNaN {
 | 16-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
@@ -100,13 +100,13 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -127,7 +126,7 @@ uint_fast16_t
 | 32-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
@@ -135,13 +134,13 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 )
+#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -170,13 +169,13 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
 #define defaultNaNExtF80UI64 0xFFFF
-#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 80-bit unsigned integer formed from concatenating
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,16 +214,14 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000)
-#define defaultNaNF128UI0  UINT64_C( 0 )
+#define defaultNaNF128UI0 UINT64_C(0)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 128-bit unsigned integer formed from concatenating
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,15 +256,13 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
-

softfloat/source/8086/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -62,12 +62,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define i64_fromPosOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromPosOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
-#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
-#define i64_fromNaN          (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
 
 /*----------------------------------------------------------------------------
 | "Common NaN" structure, used to transfer NaN representations from one format
@@ -92,7 +92,7 @@ struct commonNaN {
 | 16-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
@@ -100,13 +100,13 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -127,7 +126,7 @@ uint_fast16_t
 | 32-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
@@ -135,13 +134,13 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 )
+#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -170,13 +169,13 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
 #define defaultNaNExtF80UI64 0xFFFF
-#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 80-bit unsigned integer formed from concatenating
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,16 +214,14 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000)
-#define defaultNaNF128UI0  UINT64_C( 0 )
+#define defaultNaNF128UI0 UINT64_C(0)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 128-bit unsigned integer formed from concatenating
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,15 +256,13 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
-

softfloat/source/ARM-VFPv2-defaultNaN/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -62,18 +62,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
 #define ui64_fromNegOverflow 0
 #define ui64_fromNaN 0
-#define i64_fromPosOverflow  INT64_C( 0x7FFFFFFFFFFFFFFF )
+#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF)
-#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
 #define i64_fromNaN 0
 
 /*----------------------------------------------------------------------------
 | "Common NaN" structure, used to transfer NaN representations from one format
 | to another.
 *----------------------------------------------------------------------------*/
-struct commonNaN { char _unused; };
+struct commonNaN {
+    char _unused;
+};
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 16-bit floating-point NaN.
@@ -85,7 +87,7 @@ struct commonNaN { char _unused; };
 | 16-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
@@ -93,13 +95,15 @@ struct commonNaN { char _unused; };
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f16UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&0x0200))                                                                                                                    \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF16UI( aPtr ) ((uint_fast16_t) defaultNaNF16UI)
+#define softfloat_commonNaNToF16UI(aPtr) ((uint_fast16_t)defaultNaNF16UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -107,8 +111,7 @@ struct commonNaN { char _unused; };
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -120,7 +123,7 @@ uint_fast16_t
 | 32-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
@@ -128,13 +131,15 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f32UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&0x00400000))                                                                                                                \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF32UI( aPtr ) ((uint_fast32_t) defaultNaNF32UI)
+#define softfloat_commonNaNToF32UI(aPtr) ((uint_fast32_t)defaultNaNF32UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -142,20 +147,20 @@ uint_fast16_t
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 )
+#define defaultNaNF64UI UINT64_C(0x7FF8000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -163,13 +168,15 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f64UIToCommonNaN(uiA, zPtr)                                                                                              \
+    if(!((uiA)&UINT64_C(0x0008000000000000)))                                                                                              \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#define softfloat_commonNaNToF64UI( aPtr ) ((uint_fast64_t) defaultNaNF64UI)
+#define softfloat_commonNaNToF64UI(aPtr) ((uint_fast64_t)defaultNaNF64UI)
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -177,14 +184,13 @@ uint_fast32_t
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
 #define defaultNaNExtF80UI64 0x7FFF
-#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 80-bit unsigned integer formed from concatenating
@@ -192,7 +198,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -208,24 +215,25 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                   \
+    if(!((uiA0)&UINT64_C(0x4000000000000000)))                                                                                             \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && ! defined softfloat_commonNaNToExtF80UI
+#if defined INLINE && !defined softfloat_commonNaNToExtF80UI
 INLINE
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) {
-{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNExtF80UI64;
     uiZ.v0 = defaultNaNExtF80UI0;
     return uiZ;
 }
 #else
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 #endif
 
 /*----------------------------------------------------------------------------
@@ -237,19 +245,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000)
-#define defaultNaNF128UI0  UINT64_C( 0 )
+#define defaultNaNF128UI0 UINT64_C(0)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 128-bit unsigned integer formed from concatenating
@@ -257,7 +259,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -266,23 +269,24 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr)                                                                                     \
+    if(!((uiA64)&UINT64_C(0x0000800000000000)))                                                                                            \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && ! defined softfloat_commonNaNToF128UI
+#if defined INLINE && !defined softfloat_commonNaNToF128UI
 INLINE
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) {
-{
     struct uint128 uiZ;
     uiZ.v64 = defaultNaNF128UI64;
     uiZ.v0 = defaultNaNF128UI0;
     return uiZ;
 }
 #else
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 #endif
 
 /*----------------------------------------------------------------------------
@@ -294,13 +298,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
 
 #else
 
@@ -315,26 +313,23 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_extF80MToCommonNaN(aSPtr, zPtr)                                                                                          \
+    if(!((aSPtr)->signif & UINT64_C(0x4000000000000000)))                                                                                  \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && ! defined softfloat_commonNaNToExtF80M
+#if defined INLINE && !defined softfloat_commonNaNToExtF80M
 INLINE
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) {
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
-{
     zSPtr->signExp = defaultNaNExtF80UI64;
     zSPtr->signif = defaultNaNExtF80UI0;
 }
 #else
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -343,12 +338,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -366,7 +356,9 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+#define softfloat_f128MToCommonNaN(aWPtr, zPtr)                                                                                            \
+    if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000)))                                                                          \
+    softfloat_raiseFlags(softfloat_flag_invalid)
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -374,19 +366,16 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-#if defined INLINE && ! defined softfloat_commonNaNToF128M
+#if defined INLINE && !defined softfloat_commonNaNToF128M
 INLINE
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) {
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+    zWPtr[indexWord(4, 3)] = defaultNaNF128UI96;
-{
+    zWPtr[indexWord(4, 2)] = defaultNaNF128UI64;
-    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord(4, 1)] = defaultNaNF128UI32;
-    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord(4, 0)] = defaultNaNF128UI0;
-    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
-    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
 }
 #else
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 #endif
 
 /*----------------------------------------------------------------------------
@@ -397,11 +386,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
-

softfloat/source/ARM-VFPv2/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -62,11 +62,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
 #define ui64_fromNegOverflow 0
 #define ui64_fromNaN 0
-#define i64_fromPosOverflow  INT64_C( 0x7FFFFFFFFFFFFFFF )
+#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF)
-#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
 #define i64_fromNaN 0
 
 /*----------------------------------------------------------------------------
@@ -92,7 +92,7 @@ struct commonNaN {
 | 16-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
@@ -100,13 +100,13 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -127,7 +126,7 @@ uint_fast16_t
 | 32-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
@@ -135,13 +134,13 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 )
+#define defaultNaNF64UI UINT64_C(0x7FF8000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -170,13 +169,13 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
 #define defaultNaNExtF80UI64 0x7FFF
-#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 80-bit unsigned integer formed from concatenating
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,16 +214,14 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000)
-#define defaultNaNF128UI0  UINT64_C( 0 )
+#define defaultNaNF128UI0 UINT64_C(0)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 128-bit unsigned integer formed from concatenating
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,15 +256,13 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
-

softfloat/source/RISCV/specialize.h

@@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef specialize_h
 #define specialize_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitiveTypes.h"
 #include "softfloat.h"
+#include <stdbool.h>
+#include <stdint.h>
 
 /*----------------------------------------------------------------------------
 | Default value for 'softfloat_detectTininess'.
@@ -55,19 +55,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define ui32_fromNegOverflow UINT32_C(0x0)
 #define ui32_fromNaN UINT32_C(0xFFFFFFFF)
 #define i32_fromPosOverflow INT64_C(0x7FFFFFFF)
-#define i32_fromNegOverflow  (-INT64_C(0x7FFFFFFF)-1)
+#define i32_fromNegOverflow (-INT64_C(0x7FFFFFFF) - 1)
 #define i32_fromNaN INT64_C(0x7FFFFFFF)
 
 /*----------------------------------------------------------------------------
 | The values to return on conversions to 64-bit integer formats that raise an
 | invalid exception.
 *----------------------------------------------------------------------------*/
-#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define ui64_fromNegOverflow UINT64_C( 0x0 )
+#define ui64_fromNegOverflow UINT64_C(0x0)
-#define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF)
+#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF)
-#define i64_fromPosOverflow   INT64_C( 0x7FFFFFFFFFFFFFFF)
+#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF)
-#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF)-1)
+#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1)
-#define i64_fromNaN           INT64_C( 0x7FFFFFFFFFFFFFFF)
+#define i64_fromNaN INT64_C(0x7FFFFFFFFFFFFFFF)
 
 /*----------------------------------------------------------------------------
 | "Common NaN" structure, used to transfer NaN representations from one format
@@ -92,7 +92,7 @@ struct commonNaN {
 | 16-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
@@ -100,13 +100,13 @@ struct commonNaN {
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
@@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast16_t
+uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB);
- softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 32-bit floating-point NaN.
@@ -127,7 +126,7 @@ uint_fast16_t
 | 32-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
@@ -135,13 +134,13 @@ uint_fast16_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
@@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast32_t
+uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB);
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 64-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 )
+#define defaultNaNF64UI UINT64_C(0x7FF8000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
 | 64-bit floating-point signaling NaN.
 | Note:  This macro evaluates its argument more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+#define softfloat_isSigNaNF64UI(uiA)                                                                                                       \
+    ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF)))
 
 /*----------------------------------------------------------------------------
 | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
@@ -170,13 +169,13 @@ uint_fast32_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr);
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
@@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
 | the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
 | signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-uint_fast64_t
+uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB);
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 80-bit extended floating-point NaN.
 *----------------------------------------------------------------------------*/
 #define defaultNaNExtF80UI64 0xFFFF
-#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 80-bit unsigned integer formed from concatenating
@@ -199,7 +197,8 @@ uint_fast64_t
 | floating-point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+#define softfloat_isSigNaNExtF80UI(uiA64, uiA0)                                                                                            \
+    ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
@@ -215,16 +214,14 @@ uint_fast64_t
 | location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 | result.  If either original floating-point value is a signaling NaN, the
 | invalid exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNExtF80UI(
-     uint_fast16_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast16_t uiB64,
-     uint_fast64_t uiB0
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
 *----------------------------------------------------------------------------*/
-#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000)
-#define defaultNaNF128UI0  UINT64_C( 0 )
+#define defaultNaNF128UI0 UINT64_C(0)
 
 /*----------------------------------------------------------------------------
 | Returns true when the 128-bit unsigned integer formed from concatenating
@@ -255,7 +246,8 @@ struct uint128
 | point signaling NaN.
 | Note:  This macro evaluates its arguments more than once.
 *----------------------------------------------------------------------------*/
-#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+#define softfloat_isSigNaNF128UI(uiA64, uiA0)                                                                                              \
+    ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF))))
 
 /*----------------------------------------------------------------------------
 | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
@@ -264,15 +256,13 @@ struct uint128
 | pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
 | is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr);
- softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
 | NaN, and returns the bit pattern of this value as an unsigned integer.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*);
 
 /*----------------------------------------------------------------------------
 | Interpreting the unsigned integer formed from concatenating 'uiA64' and
@@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
 | If either original floating-point value is a signaling NaN, the invalid
 | exception is raised.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0);
- softfloat_propagateNaNF128UI(
-     uint_fast64_t uiA64,
-     uint_fast64_t uiA0,
-     uint_fast64_t uiB64,
-     uint_fast64_t uiB0
- );
 
 #else
 
@@ -304,18 +288,14 @@ struct uint128
 | common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
 | NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr);
- softfloat_extF80MToCommonNaN(
-     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
 | floating-point NaN, and stores this NaN at the location pointed to by
 | 'zSPtr'.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr);
- softfloat_commonNaNToExtF80M(
-     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 80-bit extended floating-point values
@@ -323,12 +303,7 @@ void
 | at the location pointed to by 'zSPtr'.  If either original floating-point
 | value is a signaling NaN, the invalid exception is raised.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr);
- softfloat_propagateNaNExtF80M(
-     const struct extFloat80M *aSPtr,
-     const struct extFloat80M *bSPtr,
-     struct extFloat80M *zSPtr
- );
 
 /*----------------------------------------------------------------------------
 | The bit pattern for a default generated 128-bit floating-point NaN.
@@ -346,8 +321,7 @@ void
 | four 32-bit elements that concatenate in the platform's normal endian order
 | to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr);
- softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
 
 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -355,8 +329,7 @@ void
 | 'zWPtr' points to an array of four 32-bit elements that concatenate in the
 | platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr);
- softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
 
 /*----------------------------------------------------------------------------
 | Assuming at least one of the two 128-bit floating-point values pointed to by
@@ -366,11 +339,8 @@ void
 | and 'zWPtr' points to an array of four 32-bit elements that concatenate in
 | the platform's normal endian order to form a 128-bit floating-point value.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr);
- softfloat_propagateNaNF128M(
-     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
 
 #endif
 
 #endif
-

softfloat/source/include/internals.h

@@ -37,242 +37,205 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef internals_h
 #define internals_h 1
 
-#include <stdbool.h>
-#include <stdint.h>
 #include "primitives.h"
 #include "softfloat_types.h"
+#include <stdbool.h>
+#include <stdint.h>
 
-union ui16_f16 { uint16_t ui; float16_t f; };
+union ui16_f16 {
-union ui32_f32 { uint32_t ui; float32_t f; };
+    uint16_t ui;
-union ui64_f64 { uint64_t ui; float64_t f; };
+    float16_t f;
-
+};
-#ifdef SOFTFLOAT_FAST_INT64
+union ui32_f32 {
-union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; };
+    uint32_t ui;
-union ui128_f128 { struct uint128 ui; float128_t f; };
+    float32_t f;
-#endif
+};
-
+union ui64_f64 {
-enum {
+    uint64_t ui;
-    softfloat_mulAdd_subC    = 1,
+    float64_t f;
-    softfloat_mulAdd_subProd = 2
 };
 
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
-
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast64_t
+union extF80M_extF80 {
- softfloat_roundToUI64(
+    struct extFloat80M fM;
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+    extFloat80_t f;
-#else
+};
-uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
+union ui128_f128 {
+    struct uint128 ui;
+    float128_t f;
+};
 #endif
 
-int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
+enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 };
+
+/*----------------------------------------------------------------------------
+ *----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_roundToUI32(bool, uint_fast64_t, uint_fast8_t, bool);
 
 #ifdef SOFTFLOAT_FAST_INT64
-int_fast64_t
+uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
- softfloat_roundToI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
-int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
+uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool);
+#endif
+
+int_fast32_t softfloat_roundToI32(bool, uint_fast64_t, uint_fast8_t, bool);
+
+#ifdef SOFTFLOAT_FAST_INT64
+int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool);
+#else
+int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool);
 #endif
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signF16UI( a ) ((bool) ((uint16_t) (a)>>15))
+#define signF16UI(a) ((bool)((uint16_t)(a) >> 15))
-#define expF16UI( a ) ((int_fast8_t) ((a)>>10) & 0x1F)
+#define expF16UI(a) ((int_fast8_t)((a) >> 10) & 0x1F)
-#define fracF16UI( a ) ((a) & 0x03FF)
+#define fracF16UI(a) ((a)&0x03FF)
-#define packToF16UI( sign, exp, sig ) (((uint16_t) (sign)<<15) + ((uint16_t) (exp)<<10) + (sig))
+#define packToF16UI(sign, exp, sig) (((uint16_t)(sign) << 15) + ((uint16_t)(exp) << 10) + (sig))
 
-#define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF))
+#define isNaNF16UI(a) (((~(a)&0x7C00) == 0) && ((a)&0x03FF))
 
-struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; };
+struct exp8_sig16 {
-struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t );
+    int_fast8_t exp;
+    uint_fast16_t sig;
+};
+struct exp8_sig16 softfloat_normSubnormalF16Sig(uint_fast16_t);
 
-float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t );
+float16_t softfloat_roundPackToF16(bool, int_fast16_t, uint_fast16_t);
-float16_t softfloat_normRoundPackToF16( bool, int_fast16_t, uint_fast16_t );
+float16_t softfloat_normRoundPackToF16(bool, int_fast16_t, uint_fast16_t);
 
-float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t );
+float16_t softfloat_addMagsF16(uint_fast16_t, uint_fast16_t);
-float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t );
+float16_t softfloat_subMagsF16(uint_fast16_t, uint_fast16_t);
-float16_t
+float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t);
- softfloat_mulAddF16(
-     uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signF32UI( a ) ((bool) ((uint32_t) (a)>>31))
+#define signF32UI(a) ((bool)((uint32_t)(a) >> 31))
-#define expF32UI( a ) ((int_fast16_t) ((a)>>23) & 0xFF)
+#define expF32UI(a) ((int_fast16_t)((a) >> 23) & 0xFF)
-#define fracF32UI( a ) ((a) & 0x007FFFFF)
+#define fracF32UI(a) ((a)&0x007FFFFF)
-#define packToF32UI( sign, exp, sig ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<23) + (sig))
+#define packToF32UI(sign, exp, sig) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 23) + (sig))
 
-#define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
+#define isNaNF32UI(a) (((~(a)&0x7F800000) == 0) && ((a)&0x007FFFFF))
 
-struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
+struct exp16_sig32 {
-struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
+    int_fast16_t exp;
+    uint_fast32_t sig;
+};
+struct exp16_sig32 softfloat_normSubnormalF32Sig(uint_fast32_t);
 
-float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
+float32_t softfloat_roundPackToF32(bool, int_fast16_t, uint_fast32_t);
-float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );
+float32_t softfloat_normRoundPackToF32(bool, int_fast16_t, uint_fast32_t);
 
-float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
+float32_t softfloat_addMagsF32(uint_fast32_t, uint_fast32_t);
-float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t );
+float32_t softfloat_subMagsF32(uint_fast32_t, uint_fast32_t);
-float32_t
+float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t);
- softfloat_mulAddF32(
-     uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signF64UI( a ) ((bool) ((uint64_t) (a)>>63))
+#define signF64UI(a) ((bool)((uint64_t)(a) >> 63))
-#define expF64UI( a ) ((int_fast16_t) ((a)>>52) & 0x7FF)
+#define expF64UI(a) ((int_fast16_t)((a) >> 52) & 0x7FF)
-#define fracF64UI( a ) ((a) & UINT64_C( 0x000FFFFFFFFFFFFF ))
+#define fracF64UI(a) ((a)&UINT64_C(0x000FFFFFFFFFFFFF))
-#define packToF64UI( sign, exp, sig ) ((uint64_t) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<52) + (sig)))
+#define packToF64UI(sign, exp, sig) ((uint64_t)(((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 52) + (sig)))
 
-#define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
+#define isNaNF64UI(a) (((~(a)&UINT64_C(0x7FF0000000000000)) == 0) && ((a)&UINT64_C(0x000FFFFFFFFFFFFF)))
 
-struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
+struct exp16_sig64 {
-struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
+    int_fast16_t exp;
+    uint_fast64_t sig;
+};
+struct exp16_sig64 softfloat_normSubnormalF64Sig(uint_fast64_t);
 
-float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
+float64_t softfloat_roundPackToF64(bool, int_fast16_t, uint_fast64_t);
-float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );
+float64_t softfloat_normRoundPackToF64(bool, int_fast16_t, uint_fast64_t);
 
-float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
+float64_t softfloat_addMagsF64(uint_fast64_t, uint_fast64_t, bool);
-float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );
+float64_t softfloat_subMagsF64(uint_fast64_t, uint_fast64_t, bool);
-float64_t
+float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
- softfloat_mulAddF64(
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signExtF80UI64( a64 ) ((bool) ((uint16_t) (a64)>>15))
+#define signExtF80UI64(a64) ((bool)((uint16_t)(a64) >> 15))
-#define expExtF80UI64( a64 ) ((a64) & 0x7FFF)
+#define expExtF80UI64(a64) ((a64)&0x7FFF)
-#define packToExtF80UI64( sign, exp ) ((uint_fast16_t) (sign)<<15 | (exp))
+#define packToExtF80UI64(sign, exp) ((uint_fast16_t)(sign) << 15 | (exp))
 
-#define isNaNExtF80UI( a64, a0 ) ((((a64) & 0x7FFF) == 0x7FFF) && ((a0) & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+#define isNaNExtF80UI(a64, a0) ((((a64)&0x7FFF) == 0x7FFF) && ((a0)&UINT64_C(0x7FFFFFFFFFFFFFFF)))
 
 #ifdef SOFTFLOAT_FAST_INT64
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 
-struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
+struct exp32_sig64 {
-struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
+    int_fast32_t exp;
+    uint64_t sig;
+};
+struct exp32_sig64 softfloat_normSubnormalExtF80Sig(uint_fast64_t);
 
-extFloat80_t
+extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
- softfloat_roundPackToExtF80(
+extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
-extFloat80_t
- softfloat_normRoundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 
-extFloat80_t
+extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
- softfloat_addMagsExtF80(
+extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool);
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
-extFloat80_t
- softfloat_subMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signF128UI64( a64 ) ((bool) ((uint64_t) (a64)>>63))
+#define signF128UI64(a64) ((bool)((uint64_t)(a64) >> 63))
-#define expF128UI64( a64 ) ((int_fast32_t) ((a64)>>48) & 0x7FFF)
+#define expF128UI64(a64) ((int_fast32_t)((a64) >> 48) & 0x7FFF)
-#define fracF128UI64( a64 ) ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))
+#define fracF128UI64(a64) ((a64)&UINT64_C(0x0000FFFFFFFFFFFF))
-#define packToF128UI64( sign, exp, sig64 ) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<48) + (sig64))
+#define packToF128UI64(sign, exp, sig64) (((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 48) + (sig64))
 
-#define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
+#define isNaNF128UI(a64, a0) (((~(a64)&UINT64_C(0x7FFF000000000000)) == 0) && (a0 || ((a64)&UINT64_C(0x0000FFFFFFFFFFFF))))
 
-struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
+struct exp32_sig128 {
-struct exp32_sig128
+    int_fast32_t exp;
- softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
+    struct uint128 sig;
+};
+struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t);
 
-float128_t
+float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t);
- softfloat_roundPackToF128(
+float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t);
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t );
-float128_t
- softfloat_normRoundPackToF128(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t );
 
-float128_t
+float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
- softfloat_addMagsF128(
+float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool);
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t);
-float128_t
- softfloat_subMagsF128(
-     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
-float128_t
- softfloat_mulAddF128(
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast64_t,
-     uint_fast8_t
- );
 
 #else
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
 
-bool
+bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*);
- softfloat_tryPropagateNaNExtF80M(
+void softfloat_invalidExtF80M(struct extFloat80M*);
-     const struct extFloat80M *,
-     const struct extFloat80M *,
-     struct extFloat80M *
- );
-void softfloat_invalidExtF80M( struct extFloat80M * );
 
-int softfloat_normExtF80SigM( uint64_t * );
+int softfloat_normExtF80SigM(uint64_t*);
 
-void
+void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
- softfloat_roundPackMToExtF80M(
+void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*);
-     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
-void
- softfloat_normRoundPackMToExtF80M(
-     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
 
-void
+void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool);
- softfloat_addExtF80M(
-     const struct extFloat80M *,
-     const struct extFloat80M *,
-     struct extFloat80M *,
-     bool
- );
 
-int
+int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*);
- softfloat_compareNonnormExtF80M(
-     const struct extFloat80M *, const struct extFloat80M * );
 
 /*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
+ *----------------------------------------------------------------------------*/
-#define signF128UI96( a96 ) ((bool) ((uint32_t) (a96)>>31))
+#define signF128UI96(a96) ((bool)((uint32_t)(a96) >> 31))
-#define expF128UI96( a96 ) ((int32_t) ((a96)>>16) & 0x7FFF)
+#define expF128UI96(a96) ((int32_t)((a96) >> 16) & 0x7FFF)
-#define fracF128UI96( a96 ) ((a96) & 0x0000FFFF)
+#define fracF128UI96(a96) ((a96)&0x0000FFFF)
-#define packToF128UI96( sign, exp, sig96 ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<16) + (sig96))
+#define packToF128UI96(sign, exp, sig96) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 16) + (sig96))
 
-bool softfloat_isNaNF128M( const uint32_t * );
+bool softfloat_isNaNF128M(const uint32_t*);
 
-bool
+bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*);
- softfloat_tryPropagateNaNF128M(
+void softfloat_invalidF128M(uint32_t*);
-     const uint32_t *, const uint32_t *, uint32_t * );
-void softfloat_invalidF128M( uint32_t * );
 
-int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * );
+int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*);
 
-void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
+void softfloat_roundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*);
-void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
+void softfloat_normRoundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*);
 
-void
+void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool);
- softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool );
+void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t);
-void
- softfloat_mulAddF128M(
-     const uint32_t *,
-     const uint32_t *,
-     const uint32_t *,
-     uint32_t *,
-     uint_fast8_t
- );
 
 #endif
 
 #endif
-

softfloat/source/include/opts-GCC.h

@@ -39,70 +39,70 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifdef INLINE
 
-#include <stdint.h>
 #include "primitiveTypes.h"
+#include <stdint.h>
 
 #ifdef SOFTFLOAT_BUILTIN_CLZ
 
-INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; }
-    { return a ? __builtin_clz( a ) - 16 : 16; }
 #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
 
-INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; }
-    { return a ? __builtin_clz( a ) : 32; }
 #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
 
-INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
+INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; }
-    { return a ? __builtin_clzll( a ) : 64; }
 #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
 
 #endif
 
 #ifdef SOFTFLOAT_INTRINSIC_INT128
 
-INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
-{
+    union {
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+        unsigned __int128 ui;
-    uZ.ui = (unsigned __int128) a * ((uint_fast64_t) b<<32);
+        struct uint128 s;
+    } uZ;
+    uZ.ui = (unsigned __int128)a * ((uint_fast64_t)b << 32);
     return uZ.s;
 }
 #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
 
-INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
+INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) {
-{
+    union {
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+        unsigned __int128 ui;
-    uZ.ui = (unsigned __int128) a * b;
+        struct uint128 s;
+    } uZ;
+    uZ.ui = (unsigned __int128)a * b;
     return uZ.s;
 }
 #define softfloat_mul64To128 softfloat_mul64To128
 
 INLINE
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
-{
+    union {
-    union { unsigned __int128 ui; struct uint128 s; } uZ;
+        unsigned __int128 ui;
-    uZ.ui = ((unsigned __int128) a64<<64 | a0) * b;
+        struct uint128 s;
+    } uZ;
+    uZ.ui = ((unsigned __int128)a64 << 64 | a0) * b;
     return uZ.s;
 }
 #define softfloat_mul128By32 softfloat_mul128By32
 
 INLINE
-void
+void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) {
- softfloat_mul128To256M(
-     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
-{
     unsigned __int128 z0, mid1, mid, z128;
-    z0 = (unsigned __int128) a0 * b0;
+    z0 = (unsigned __int128)a0 * b0;
-    mid1 = (unsigned __int128) a64 * b0;
+    mid1 = (unsigned __int128)a64 * b0;
-    mid = mid1 + (unsigned __int128) a0 * b64;
+    mid = mid1 + (unsigned __int128)a0 * b64;
-    z128 = (unsigned __int128) a64 * b64;
+    z128 = (unsigned __int128)a64 * b64;
-    z128 += (unsigned __int128) (mid < mid1)<<64 | mid>>64;
+    z128 += (unsigned __int128)(mid < mid1) << 64 | mid >> 64;
     mid <<= 64;
     z0 += mid;
     z128 += (z0 < mid);
-    zPtr[indexWord( 4, 0 )] = z0;
+    zPtr[indexWord(4, 0)] = z0;
-    zPtr[indexWord( 4, 1 )] = z0>>64;
+    zPtr[indexWord(4, 1)] = z0 >> 64;
-    zPtr[indexWord( 4, 2 )] = z128;
+    zPtr[indexWord(4, 2)] = z128;
-    zPtr[indexWord( 4, 3 )] = z128>>64;
+    zPtr[indexWord(4, 3)] = z128 >> 64;
 }
 #define softfloat_mul128To256M softfloat_mul128To256M
 
@@ -111,4 +111,3 @@ void
 #endif
 
 #endif
-

softfloat/source/include/primitiveTypes.h

@@ -42,13 +42,27 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifdef SOFTFLOAT_FAST_INT64
 
 #ifdef LITTLEENDIAN
-struct uint128 { uint64_t v0, v64; };
+struct uint128 {
-struct uint64_extra { uint64_t extra, v; };
+    uint64_t v0, v64;
-struct uint128_extra { uint64_t extra; struct uint128 v; };
+};
+struct uint64_extra {
+    uint64_t extra, v;
+};
+struct uint128_extra {
+    uint64_t extra;
+    struct uint128 v;
+};
 #else
-struct uint128 { uint64_t v64, v0; };
+struct uint128 {
-struct uint64_extra { uint64_t v, extra; };
+    uint64_t v64, v0;
-struct uint128_extra { struct uint128 v; uint64_t extra; };
+};
+struct uint64_extra {
+    uint64_t v, extra;
+};
+struct uint128_extra {
+    struct uint128 v;
+    uint64_t extra;
+};
 #endif
 
 #endif
@@ -59,27 +73,28 @@ struct uint128_extra { struct uint128 v; uint64_t extra; };
 *----------------------------------------------------------------------------*/
 #ifdef LITTLEENDIAN
 #define wordIncr 1
-#define indexWord( total, n ) (n)
+#define indexWord(total, n) (n)
-#define indexWordHi( total ) ((total) - 1)
+#define indexWordHi(total) ((total)-1)
-#define indexWordLo( total ) 0
+#define indexWordLo(total) 0
-#define indexMultiword( total, m, n ) (n)
+#define indexMultiword(total, m, n) (n)
-#define indexMultiwordHi( total, n ) ((total) - (n))
+#define indexMultiwordHi(total, n) ((total) - (n))
-#define indexMultiwordLo( total, n ) 0
+#define indexMultiwordLo(total, n) 0
-#define indexMultiwordHiBut( total, n ) (n)
+#define indexMultiwordHiBut(total, n) (n)
-#define indexMultiwordLoBut( total, n ) 0
+#define indexMultiwordLoBut(total, n) 0
-#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 }
+#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+    { v0, v1, v2, v3 }
 #else
 #define wordIncr -1
-#define indexWord( total, n ) ((total) - 1 - (n))
+#define indexWord(total, n) ((total)-1 - (n))
-#define indexWordHi( total ) 0
+#define indexWordHi(total) 0
-#define indexWordLo( total ) ((total) - 1)
+#define indexWordLo(total) ((total)-1)
-#define indexMultiword( total, m, n ) ((total) - 1 - (m))
+#define indexMultiword(total, m, n) ((total)-1 - (m))
-#define indexMultiwordHi( total, n ) 0
+#define indexMultiwordHi(total, n) 0
-#define indexMultiwordLo( total, n ) ((total) - (n))
+#define indexMultiwordLo(total, n) ((total) - (n))
-#define indexMultiwordHiBut( total, n ) 0
+#define indexMultiwordHiBut(total, n) 0
-#define indexMultiwordLoBut( total, n ) (n)
+#define indexMultiwordLoBut(total, n) (n)
-#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 }
+#define INIT_UINTM4(v3, v2, v1, v0)                                                                                                        \
+    { v3, v2, v1, v0 }
 #endif
 
 #endif
-

softfloat/source/include/primitives.h

@@ -37,9 +37,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifndef primitives_h
 #define primitives_h 1
 
+#include "primitiveTypes.h"
 #include <stdbool.h>
 #include <stdint.h>
-#include "primitiveTypes.h"
 
 #ifndef softfloat_shortShiftRightJam64
 /*----------------------------------------------------------------------------
@@ -50,10 +50,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
+uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist) { return a >> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); }
-    { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
 #else
-uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
+uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist);
 #endif
 #endif
 
@@ -68,13 +67,11 @@ uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
+INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) {
-{
+    return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0);
-    return
-        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
 }
 #else
-uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
+uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist);
 #endif
 #endif
 
@@ -89,13 +86,11 @@ uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
 | is zero or nonzero.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
+INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) {
-{
+    return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0);
-    return
-        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
 }
 #else
-uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
+uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist);
 #endif
 #endif
 
@@ -112,10 +107,9 @@ extern const uint_least8_t softfloat_countLeadingZeros8[256];
 | 'a'.  If 'a' is zero, 16 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) {
-{
     uint_fast8_t count = 8;
-    if ( 0x100 <= a ) {
+    if(0x100 <= a) {
         count = 0;
         a >>= 8;
     }
@@ -123,7 +117,7 @@ INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
     return count;
 }
 #else
-uint_fast8_t softfloat_countLeadingZeros16( uint16_t a );
+uint_fast8_t softfloat_countLeadingZeros16(uint16_t a);
 #endif
 #endif
 
@@ -133,22 +127,21 @@ uint_fast8_t softfloat_countLeadingZeros16( uint16_t a );
 | 'a'.  If 'a' is zero, 32 is returned.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) {
-{
     uint_fast8_t count = 0;
-    if ( a < 0x10000 ) {
+    if(a < 0x10000) {
         count = 16;
         a <<= 16;
     }
-    if ( a < 0x1000000 ) {
+    if(a < 0x1000000) {
         count += 8;
         a <<= 8;
     }
-    count += softfloat_countLeadingZeros8[a>>24];
+    count += softfloat_countLeadingZeros8[a >> 24];
     return count;
 }
 #else
-uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
+uint_fast8_t softfloat_countLeadingZeros32(uint32_t a);
 #endif
 #endif
 
@@ -157,7 +150,7 @@ uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
 | Returns the number of leading 0 bits before the most-significant 1 bit of
 | 'a'.  If 'a' is zero, 64 is returned.
 *----------------------------------------------------------------------------*/
-uint_fast8_t softfloat_countLeadingZeros64( uint64_t a );
+uint_fast8_t softfloat_countLeadingZeros64(uint64_t a);
 #endif
 
 extern const uint16_t softfloat_approxRecip_1k0s[16];
@@ -176,9 +169,9 @@ extern const uint16_t softfloat_approxRecip_1k1s[16];
 | (units in the last place).
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_DIV64TO32
-#define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a)))
+#define softfloat_approxRecip32_1(a) ((uint32_t)(UINT64_C(0x7FFFFFFFFFFFFFFF) / (uint32_t)(a)))
 #else
-uint32_t softfloat_approxRecip32_1( uint32_t a );
+uint32_t softfloat_approxRecip32_1(uint32_t a);
 #endif
 #endif
 
@@ -204,7 +197,7 @@ extern const uint16_t softfloat_approxRecipSqrt_1k1s[16];
 | returned is also always within the range 0.5 to 1; thus, the most-
 | significant bit of the result is always set.
 *----------------------------------------------------------------------------*/
-uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
+uint32_t softfloat_approxRecipSqrt32_1(unsigned int oddExpA, uint32_t a);
 #endif
 
 #ifdef SOFTFLOAT_FAST_INT64
@@ -222,10 +215,9 @@ uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
 INLINE
-bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); }
-    { return (a64 == b64) && (a0 == b0); }
 #else
-bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
 #endif
 
@@ -237,10 +229,9 @@ bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
-    { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
-bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
 #endif
 
@@ -252,10 +243,9 @@ bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
-    { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
-bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
 #endif
 #endif
 
@@ -266,17 +256,14 @@ bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
+struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
- softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
     struct uint128 z;
-    z.v64 = a64<<dist | a0>>(-dist & 63);
+    z.v64 = a64 << dist | a0 >> (-dist & 63);
-    z.v0 = a0<<dist;
+    z.v0 = a0 << dist;
     return z;
 }
 #else
-struct uint128
+struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
- softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -287,17 +274,14 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
+struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
- softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
     struct uint128 z;
-    z.v64 = a64>>dist;
+    z.v64 = a64 >> dist;
-    z.v0 = a64<<(-dist & 63) | a0>>dist;
+    z.v0 = a64 << (-dist & 63) | a0 >> dist;
     return z;
 }
 #else
-struct uint128
+struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
- softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -308,19 +292,14 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra
+struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) {
- softfloat_shortShiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast8_t dist )
-{
     struct uint64_extra z;
-    z.v = a>>dist;
+    z.v = a >> dist;
-    z.extra = a<<(-dist & 63) | (extra != 0);
+    z.extra = a << (-dist & 63) | (extra != 0);
     return z;
 }
 #else
-struct uint64_extra
+struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist);
- softfloat_shortShiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -334,22 +313,15 @@ struct uint64_extra
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128
+struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) {
- softfloat_shortShiftRightJam128(
-     uint64_t a64, uint64_t a0, uint_fast8_t dist )
-{
     uint_fast8_t negDist = -dist;
     struct uint128 z;
-    z.v64 = a64>>dist;
+    z.v64 = a64 >> dist;
-    z.v0 =
+    z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0);
-        a64<<(negDist & 63) | a0>>dist
-            | ((uint64_t) (a0<<(negDist & 63)) != 0);
     return z;
 }
 #else
-struct uint128
+struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist);
- softfloat_shortShiftRightJam128(
-     uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
 #endif
 
@@ -360,21 +332,16 @@ struct uint128
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
 INLINE
-struct uint128_extra
+struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) {
- softfloat_shortShiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
-{
     uint_fast8_t negDist = -dist;
     struct uint128_extra z;
-    z.v.v64 = a64>>dist;
+    z.v.v64 = a64 >> dist;
-    z.v.v0 = a64<<(negDist & 63) | a0>>dist;
+    z.v.v0 = a64 << (negDist & 63) | a0 >> dist;
-    z.extra = a0<<(negDist & 63) | (extra != 0);
+    z.extra = a0 << (negDist & 63) | (extra != 0);
     return z;
 }
 #else
-struct uint128_extra
+struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist);
- softfloat_shortShiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist );
 #endif
 #endif
 
@@ -397,14 +364,11 @@ struct uint128_extra
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint64_extra
+struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) {
- softfloat_shiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast32_t dist )
-{
     struct uint64_extra z;
-    if ( dist < 64 ) {
+    if(dist < 64) {
-        z.v = a>>dist;
+        z.v = a >> dist;
-        z.extra = a<<(-dist & 63);
+        z.extra = a << (-dist & 63);
     } else {
         z.v = 0;
         z.extra = (dist == 64) ? a : (a != 0);
@@ -413,9 +377,7 @@ struct uint64_extra
     return z;
 }
 #else
-struct uint64_extra
+struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist);
- softfloat_shiftRightJam64Extra(
-     uint64_t a, uint64_t extra, uint_fast32_t dist );
 #endif
 #endif
 
@@ -430,8 +392,7 @@ struct uint64_extra
 | greater than 128, the result will be either 0 or 1, depending on whether the
 | original 128 bits are all zeros.
 *----------------------------------------------------------------------------*/
-struct uint128
+struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist);
- softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam128Extra
@@ -452,9 +413,7 @@ struct uint128
 | is modified as described above and returned in the 'extra' field of the
 | result.)
 *----------------------------------------------------------------------------*/
-struct uint128_extra
+struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist);
- softfloat_shiftRightJam128Extra(
-     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist );
 #endif
 
 #ifndef softfloat_shiftRightJam256M
@@ -470,9 +429,7 @@ struct uint128_extra
 | is greater than 256, the stored result will be either 0 or 1, depending on
 | whether the original 256 bits are all zeros.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr);
- softfloat_shiftRightJam256M(
-     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_add128
@@ -483,17 +440,14 @@ void
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
+struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
     struct uint128 z;
     z.v0 = a0 + b0;
     z.v64 = a64 + b64 + (z.v0 < a0);
     return z;
 }
 #else
-struct uint128
+struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -505,9 +459,7 @@ struct uint128
 | an array of four 64-bit elements that concatenate in the platform's normal
 | endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
- softfloat_add256M(
-     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_sub128
@@ -518,9 +470,7 @@ void
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-struct uint128
+struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) {
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
     struct uint128 z;
     z.v0 = a0 - b0;
     z.v64 = a64 - b64;
@@ -528,8 +478,7 @@ struct uint128
     return z;
 }
 #else
-struct uint128
+struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0);
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
 
@@ -542,9 +491,7 @@ struct uint128
 | 64-bit elements that concatenate in the platform's normal endian order to
 | form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr);
- softfloat_sub256M(
-     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
 #endif
 
 #ifndef softfloat_mul64ByShifted32To128
@@ -552,17 +499,16 @@ void
 | Returns the 128-bit product of 'a', 'b', and 2^32.
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
-INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) {
-{
     uint_fast64_t mid;
     struct uint128 z;
-    mid = (uint_fast64_t) (uint32_t) a * b;
+    mid = (uint_fast64_t)(uint32_t)a * b;
-    z.v0 = mid<<32;
+    z.v0 = mid << 32;
-    z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32);
+    z.v64 = (uint_fast64_t)(uint32_t)(a >> 32) * b + (mid >> 32);
     return z;
 }
 #else
-struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
+struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b);
 #endif
 #endif
 
@@ -570,7 +516,7 @@ struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
 /*----------------------------------------------------------------------------
 | Returns the 128-bit product of 'a' and 'b'.
 *----------------------------------------------------------------------------*/
-struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
+struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b);
 #endif
 
 #ifndef softfloat_mul128By32
@@ -581,19 +527,18 @@ struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
 INLINE
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) {
-{
     struct uint128 z;
     uint_fast64_t mid;
     uint_fast32_t carry;
     z.v0 = a0 * b;
-    mid = (uint_fast64_t) (uint32_t) (a0>>32) * b;
+    mid = (uint_fast64_t)(uint32_t)(a0 >> 32) * b;
-    carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid);
+    carry = (uint32_t)((uint_fast32_t)(z.v0 >> 32) - (uint_fast32_t)mid);
-    z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32);
+    z.v64 = a64 * b + (uint_fast32_t)((mid + carry) >> 32);
     return z;
 }
 #else
-struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b );
+struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b);
 #endif
 #endif
 
@@ -605,9 +550,7 @@ struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b );
 | Argument 'zPtr' points to an array of four 64-bit elements that concatenate
 | in the platform's normal endian order to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr);
- softfloat_mul128To256M(
-     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr );
 #endif
 
 #else
@@ -626,7 +569,7 @@ void
 | Each of 'aPtr' and 'bPtr' points to an array of three 32-bit elements that
 | concatenate in the platform's normal endian order to form a 96-bit integer.
 *----------------------------------------------------------------------------*/
-int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr );
+int_fast8_t softfloat_compare96M(const uint32_t* aPtr, const uint32_t* bPtr);
 #endif
 
 #ifndef softfloat_compare128M
@@ -638,8 +581,7 @@ int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr );
 | Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
 | concatenate in the platform's normal endian order to form a 128-bit integer.
 *----------------------------------------------------------------------------*/
-int_fast8_t
+int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr);
- softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr );
 #endif
 
 #ifndef softfloat_shortShiftLeft64To96M
@@ -652,19 +594,14 @@ int_fast8_t
 *----------------------------------------------------------------------------*/
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
 INLINE
-void
+void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr) {
- softfloat_shortShiftLeft64To96M(
+    zPtr[indexWord(3, 0)] = (uint32_t)a << dist;
-     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
-{
-    zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist;
     a >>= 32 - dist;
-    zPtr[indexWord( 3, 2 )] = a>>32;
+    zPtr[indexWord(3, 2)] = a >> 32;
-    zPtr[indexWord( 3, 1 )] = a;
+    zPtr[indexWord(3, 1)] = a;
 }
 #else
-void
+void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr);
- softfloat_shortShiftLeft64To96M(
-     uint64_t a, uint_fast8_t dist, uint32_t *zPtr );
 #endif
 #endif
 
@@ -678,13 +615,7 @@ void
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
- softfloat_shortShiftLeftM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint_fast8_t dist,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_shortShiftLeft96M
@@ -692,7 +623,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftLeftM' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftLeft96M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 3, aPtr, dist, zPtr )
+#define softfloat_shortShiftLeft96M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(3, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shortShiftLeft128M
@@ -700,7 +631,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftLeftM' with
 | 'size_words' = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftLeft128M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 4, aPtr, dist, zPtr )
+#define softfloat_shortShiftLeft128M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(4, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shortShiftLeft160M
@@ -708,7 +639,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftLeftM' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftLeft160M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 5, aPtr, dist, zPtr )
+#define softfloat_shortShiftLeft160M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(5, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftLeftM
@@ -722,13 +653,7 @@ void
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
- softfloat_shiftLeftM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_shiftLeft96M
@@ -736,7 +661,7 @@ void
 | This function or macro is the same as 'softfloat_shiftLeftM' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftLeft96M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 3, aPtr, dist, zPtr )
+#define softfloat_shiftLeft96M(aPtr, dist, zPtr) softfloat_shiftLeftM(3, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftLeft128M
@@ -744,7 +669,7 @@ void
 | This function or macro is the same as 'softfloat_shiftLeftM' with
 | 'size_words' = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftLeft128M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 4, aPtr, dist, zPtr )
+#define softfloat_shiftLeft128M(aPtr, dist, zPtr) softfloat_shiftLeftM(4, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftLeft160M
@@ -752,7 +677,7 @@ void
 | This function or macro is the same as 'softfloat_shiftLeftM' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftLeft160M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 5, aPtr, dist, zPtr )
+#define softfloat_shiftLeft160M(aPtr, dist, zPtr) softfloat_shiftLeftM(5, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shortShiftRightM
@@ -765,13 +690,7 @@ void
 | that concatenate in the platform's normal endian order to form an N-bit
 | integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr);
- softfloat_shortShiftRightM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint_fast8_t dist,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_shortShiftRight128M
@@ -779,7 +698,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftRightM' with
 | 'size_words' = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftRight128M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 4, aPtr, dist, zPtr )
+#define softfloat_shortShiftRight128M(aPtr, dist, zPtr) softfloat_shortShiftRightM(4, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shortShiftRight160M
@@ -787,7 +706,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftRightM' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftRight160M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 5, aPtr, dist, zPtr )
+#define softfloat_shortShiftRight160M(aPtr, dist, zPtr) softfloat_shortShiftRightM(5, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shortShiftRightJamM
@@ -801,9 +720,7 @@ void
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*);
- softfloat_shortShiftRightJamM(
-     uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * );
 #endif
 
 #ifndef softfloat_shortShiftRightJam160M
@@ -811,7 +728,7 @@ void
 | This function or macro is the same as 'softfloat_shortShiftRightJamM' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_shortShiftRightJam160M( aPtr, dist, zPtr ) softfloat_shortShiftRightJamM( 5, aPtr, dist, zPtr )
+#define softfloat_shortShiftRightJam160M(aPtr, dist, zPtr) softfloat_shortShiftRightJamM(5, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftRightM
@@ -825,13 +742,7 @@ void
 |   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
 | greater than N, the stored result will be 0.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
- softfloat_shiftRightM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_shiftRight96M
@@ -839,7 +750,7 @@ void
 | This function or macro is the same as 'softfloat_shiftRightM' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftRight96M( aPtr, dist, zPtr ) softfloat_shiftRightM( 3, aPtr, dist, zPtr )
+#define softfloat_shiftRight96M(aPtr, dist, zPtr) softfloat_shiftRightM(3, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftRightJamM
@@ -856,13 +767,7 @@ void
 | is greater than N, the stored result will be either 0 or 1, depending on
 | whether the original N bits are all zeros.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr);
- softfloat_shiftRightJamM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     uint32_t dist,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_shiftRightJam96M
@@ -870,7 +775,7 @@ void
 | This function or macro is the same as 'softfloat_shiftRightJamM' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftRightJam96M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 3, aPtr, dist, zPtr )
+#define softfloat_shiftRightJam96M(aPtr, dist, zPtr) softfloat_shiftRightJamM(3, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftRightJam128M
@@ -878,7 +783,7 @@ void
 | This function or macro is the same as 'softfloat_shiftRightJamM' with
 | 'size_words' = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftRightJam128M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 4, aPtr, dist, zPtr )
+#define softfloat_shiftRightJam128M(aPtr, dist, zPtr) softfloat_shiftRightJamM(4, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_shiftRightJam160M
@@ -886,7 +791,7 @@ void
 | This function or macro is the same as 'softfloat_shiftRightJamM' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_shiftRightJam160M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 5, aPtr, dist, zPtr )
+#define softfloat_shiftRightJam160M(aPtr, dist, zPtr) softfloat_shiftRightJamM(5, aPtr, dist, zPtr)
 #endif
 
 #ifndef softfloat_addM
@@ -898,13 +803,7 @@ void
 | elements that concatenate in the platform's normal endian order to form an
 | N-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
- softfloat_addM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_add96M
@@ -912,7 +811,7 @@ void
 | This function or macro is the same as 'softfloat_addM' with 'size_words'
 | = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_add96M( aPtr, bPtr, zPtr ) softfloat_addM( 3, aPtr, bPtr, zPtr )
+#define softfloat_add96M(aPtr, bPtr, zPtr) softfloat_addM(3, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_add128M
@@ -920,7 +819,7 @@ void
 | This function or macro is the same as 'softfloat_addM' with 'size_words'
 | = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_add128M( aPtr, bPtr, zPtr ) softfloat_addM( 4, aPtr, bPtr, zPtr )
+#define softfloat_add128M(aPtr, bPtr, zPtr) softfloat_addM(4, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_add160M
@@ -928,7 +827,7 @@ void
 | This function or macro is the same as 'softfloat_addM' with 'size_words'
 | = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_add160M( aPtr, bPtr, zPtr ) softfloat_addM( 5, aPtr, bPtr, zPtr )
+#define softfloat_add160M(aPtr, bPtr, zPtr) softfloat_addM(5, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_addCarryM
@@ -940,14 +839,7 @@ void
 | points to a 'size_words'-long array of 32-bit elements that concatenate in
 | the platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-uint_fast8_t
+uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr);
- softfloat_addCarryM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint_fast8_t carry,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_addComplCarryM
@@ -956,14 +848,8 @@ uint_fast8_t
 | the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed
 | before the addition.
 *----------------------------------------------------------------------------*/
-uint_fast8_t
+uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry,
- softfloat_addComplCarryM(
+                                      uint32_t* zPtr);
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint_fast8_t carry,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_addComplCarry96M
@@ -971,7 +857,7 @@ uint_fast8_t
 | This function or macro is the same as 'softfloat_addComplCarryM' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_addComplCarry96M( aPtr, bPtr, carry, zPtr ) softfloat_addComplCarryM( 3, aPtr, bPtr, carry, zPtr )
+#define softfloat_addComplCarry96M(aPtr, bPtr, carry, zPtr) softfloat_addComplCarryM(3, aPtr, bPtr, carry, zPtr)
 #endif
 
 #ifndef softfloat_negXM
@@ -981,7 +867,7 @@ uint_fast8_t
 | points to a 'size_words'-long array of 32-bit elements that concatenate in
 | the platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
+void softfloat_negXM(uint_fast8_t size_words, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_negX96M
@@ -989,7 +875,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_negXM' with 'size_words'
 | = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_negX96M( zPtr ) softfloat_negXM( 3, zPtr )
+#define softfloat_negX96M(zPtr) softfloat_negXM(3, zPtr)
 #endif
 
 #ifndef softfloat_negX128M
@@ -997,7 +883,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_negXM' with 'size_words'
 | = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_negX128M( zPtr ) softfloat_negXM( 4, zPtr )
+#define softfloat_negX128M(zPtr) softfloat_negXM(4, zPtr)
 #endif
 
 #ifndef softfloat_negX160M
@@ -1005,7 +891,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_negXM' with 'size_words'
 | = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_negX160M( zPtr ) softfloat_negXM( 5, zPtr )
+#define softfloat_negX160M(zPtr) softfloat_negXM(5, zPtr)
 #endif
 
 #ifndef softfloat_negX256M
@@ -1013,7 +899,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_negXM' with 'size_words'
 | = 8 (N = 256).
 *----------------------------------------------------------------------------*/
-#define softfloat_negX256M( zPtr ) softfloat_negXM( 8, zPtr )
+#define softfloat_negX256M(zPtr) softfloat_negXM(8, zPtr)
 #endif
 
 #ifndef softfloat_sub1XM
@@ -1024,7 +910,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
 | elements that concatenate in the platform's normal endian order to form an
 | N-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
+void softfloat_sub1XM(uint_fast8_t size_words, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_sub1X96M
@@ -1032,7 +918,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_sub1XM' with 'size_words'
 | = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_sub1X96M( zPtr ) softfloat_sub1XM( 3, zPtr )
+#define softfloat_sub1X96M(zPtr) softfloat_sub1XM(3, zPtr)
 #endif
 
 #ifndef softfloat_sub1X160M
@@ -1040,7 +926,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
 | This function or macro is the same as 'softfloat_sub1XM' with 'size_words'
 | = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_sub1X160M( zPtr ) softfloat_sub1XM( 5, zPtr )
+#define softfloat_sub1X160M(zPtr) softfloat_sub1XM(5, zPtr)
 #endif
 
 #ifndef softfloat_subM
@@ -1052,13 +938,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
 | array of 32-bit elements that concatenate in the platform's normal endian
 | order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
- softfloat_subM(
-     uint_fast8_t size_words,
-     const uint32_t *aPtr,
-     const uint32_t *bPtr,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_sub96M
@@ -1066,7 +946,7 @@ void
 | This function or macro is the same as 'softfloat_subM' with 'size_words'
 | = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_sub96M( aPtr, bPtr, zPtr ) softfloat_subM( 3, aPtr, bPtr, zPtr )
+#define softfloat_sub96M(aPtr, bPtr, zPtr) softfloat_subM(3, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_sub128M
@@ -1074,7 +954,7 @@ void
 | This function or macro is the same as 'softfloat_subM' with 'size_words'
 | = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_sub128M( aPtr, bPtr, zPtr ) softfloat_subM( 4, aPtr, bPtr, zPtr )
+#define softfloat_sub128M(aPtr, bPtr, zPtr) softfloat_subM(4, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_sub160M
@@ -1082,7 +962,7 @@ void
 | This function or macro is the same as 'softfloat_subM' with 'size_words'
 | = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_sub160M( aPtr, bPtr, zPtr ) softfloat_subM( 5, aPtr, bPtr, zPtr )
+#define softfloat_sub160M(aPtr, bPtr, zPtr) softfloat_subM(5, aPtr, bPtr, zPtr)
 #endif
 
 #ifndef softfloat_mul64To128M
@@ -1092,7 +972,7 @@ void
 | elements that concatenate in the platform's normal endian order to form a
 | 128-bit integer.
 *----------------------------------------------------------------------------*/
-void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr );
+void softfloat_mul64To128M(uint64_t a, uint64_t b, uint32_t* zPtr);
 #endif
 
 #ifndef softfloat_mul128MTo256M
@@ -1104,9 +984,7 @@ void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr );
 | Argument 'zPtr' points to an array of eight 32-bit elements that concatenate
 | to form a 256-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr);
- softfloat_mul128MTo256M(
-     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr );
 #endif
 
 #ifndef softfloat_remStepMBy32
@@ -1119,15 +997,8 @@ void
 | to a 'size_words'-long array of 32-bit elements that concatenate in the
 | platform's normal endian order to form an N-bit integer.
 *----------------------------------------------------------------------------*/
-void
+void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q,
- softfloat_remStepMBy32(
+                            uint32_t* zPtr);
-     uint_fast8_t size_words,
-     const uint32_t *remPtr,
-     uint_fast8_t dist,
-     const uint32_t *bPtr,
-     uint32_t q,
-     uint32_t *zPtr
- );
 #endif
 
 #ifndef softfloat_remStep96MBy32
@@ -1135,7 +1006,7 @@ void
 | This function or macro is the same as 'softfloat_remStepMBy32' with
 | 'size_words' = 3 (N = 96).
 *----------------------------------------------------------------------------*/
-#define softfloat_remStep96MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 3, remPtr, dist, bPtr, q, zPtr )
+#define softfloat_remStep96MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(3, remPtr, dist, bPtr, q, zPtr)
 #endif
 
 #ifndef softfloat_remStep128MBy32
@@ -1143,7 +1014,7 @@ void
 | This function or macro is the same as 'softfloat_remStepMBy32' with
 | 'size_words' = 4 (N = 128).
 *----------------------------------------------------------------------------*/
-#define softfloat_remStep128MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 4, remPtr, dist, bPtr, q, zPtr )
+#define softfloat_remStep128MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(4, remPtr, dist, bPtr, q, zPtr)
 #endif
 
 #ifndef softfloat_remStep160MBy32
@@ -1151,10 +1022,9 @@ void
 | This function or macro is the same as 'softfloat_remStepMBy32' with
 | 'size_words' = 5 (N = 160).
 *----------------------------------------------------------------------------*/
-#define softfloat_remStep160MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 5, remPtr, dist, bPtr, q, zPtr )
+#define softfloat_remStep160MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(5, remPtr, dist, bPtr, q, zPtr)
 #endif
 
 #endif
 
 #endif
-

softfloat/source/include/softfloat.h

@@ -34,7 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 =============================================================================*/
 
-
 /*============================================================================
 | Note:  If SoftFloat is made available as a general library for programs to
 | use, it is strongly recommended that a platform-specific version of this
@@ -42,13 +41,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | eliminates all dependencies on compile-time macros.
 *============================================================================*/
 
-
 #ifndef softfloat_h
 #define softfloat_h 1
 
+#include "softfloat_types.h"
 #include <stdbool.h>
 #include <stdint.h>
-#include "softfloat_types.h"
 
 #ifndef THREAD_LOCAL
 #define THREAD_LOCAL
@@ -58,10 +56,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | Software floating-point underflow tininess-detection mode.
 *----------------------------------------------------------------------------*/
 extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum {
+enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 };
-    softfloat_tininess_beforeRounding = 0,
-    softfloat_tininess_afterRounding  = 1
-};
 
 /*----------------------------------------------------------------------------
 | Software floating-point rounding mode.  (Mode "odd" is supported only if
@@ -92,152 +87,152 @@ enum {
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
 *----------------------------------------------------------------------------*/
-void softfloat_raiseFlags( uint_fast8_t );
+void softfloat_raiseFlags(uint_fast8_t);
 
 /*----------------------------------------------------------------------------
 | Integer-to-floating-point conversion routines.
 *----------------------------------------------------------------------------*/
-float16_t ui32_to_f16( uint32_t );
+float16_t ui32_to_f16(uint32_t);
-float32_t ui32_to_f32( uint32_t );
+float32_t ui32_to_f32(uint32_t);
-float64_t ui32_to_f64( uint32_t );
+float64_t ui32_to_f64(uint32_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t ui32_to_extF80( uint32_t );
+extFloat80_t ui32_to_extF80(uint32_t);
-float128_t ui32_to_f128( uint32_t );
+float128_t ui32_to_f128(uint32_t);
 #endif
-void ui32_to_extF80M( uint32_t, extFloat80_t * );
+void ui32_to_extF80M(uint32_t, extFloat80_t*);
-void ui32_to_f128M( uint32_t, float128_t * );
+void ui32_to_f128M(uint32_t, float128_t*);
-float16_t ui64_to_f16( uint64_t );
+float16_t ui64_to_f16(uint64_t);
-float32_t ui64_to_f32( uint64_t );
+float32_t ui64_to_f32(uint64_t);
-float64_t ui64_to_f64( uint64_t );
+float64_t ui64_to_f64(uint64_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t ui64_to_extF80( uint64_t );
+extFloat80_t ui64_to_extF80(uint64_t);
-float128_t ui64_to_f128( uint64_t );
+float128_t ui64_to_f128(uint64_t);
 #endif
-void ui64_to_extF80M( uint64_t, extFloat80_t * );
+void ui64_to_extF80M(uint64_t, extFloat80_t*);
-void ui64_to_f128M( uint64_t, float128_t * );
+void ui64_to_f128M(uint64_t, float128_t*);
-float16_t i32_to_f16( int32_t );
+float16_t i32_to_f16(int32_t);
-float32_t i32_to_f32( int32_t );
+float32_t i32_to_f32(int32_t);
-float64_t i32_to_f64( int32_t );
+float64_t i32_to_f64(int32_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t i32_to_extF80( int32_t );
+extFloat80_t i32_to_extF80(int32_t);
-float128_t i32_to_f128( int32_t );
+float128_t i32_to_f128(int32_t);
 #endif
-void i32_to_extF80M( int32_t, extFloat80_t * );
+void i32_to_extF80M(int32_t, extFloat80_t*);
-void i32_to_f128M( int32_t, float128_t * );
+void i32_to_f128M(int32_t, float128_t*);
-float16_t i64_to_f16( int64_t );
+float16_t i64_to_f16(int64_t);
-float32_t i64_to_f32( int64_t );
+float32_t i64_to_f32(int64_t);
-float64_t i64_to_f64( int64_t );
+float64_t i64_to_f64(int64_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t i64_to_extF80( int64_t );
+extFloat80_t i64_to_extF80(int64_t);
-float128_t i64_to_f128( int64_t );
+float128_t i64_to_f128(int64_t);
 #endif
-void i64_to_extF80M( int64_t, extFloat80_t * );
+void i64_to_extF80M(int64_t, extFloat80_t*);
-void i64_to_f128M( int64_t, float128_t * );
+void i64_to_f128M(int64_t, float128_t*);
 
 /*----------------------------------------------------------------------------
 | 16-bit (half-precision) floating-point operations.
 *----------------------------------------------------------------------------*/
-uint_fast32_t f16_to_ui32( float16_t, uint_fast8_t, bool );
+uint_fast32_t f16_to_ui32(float16_t, uint_fast8_t, bool);
-uint_fast64_t f16_to_ui64( float16_t, uint_fast8_t, bool );
+uint_fast64_t f16_to_ui64(float16_t, uint_fast8_t, bool);
-int_fast32_t f16_to_i32( float16_t, uint_fast8_t, bool );
+int_fast32_t f16_to_i32(float16_t, uint_fast8_t, bool);
-int_fast64_t f16_to_i64( float16_t, uint_fast8_t, bool );
+int_fast64_t f16_to_i64(float16_t, uint_fast8_t, bool);
-uint_fast32_t f16_to_ui32_r_minMag( float16_t, bool );
+uint_fast32_t f16_to_ui32_r_minMag(float16_t, bool);
-uint_fast64_t f16_to_ui64_r_minMag( float16_t, bool );
+uint_fast64_t f16_to_ui64_r_minMag(float16_t, bool);
-int_fast32_t f16_to_i32_r_minMag( float16_t, bool );
+int_fast32_t f16_to_i32_r_minMag(float16_t, bool);
-int_fast64_t f16_to_i64_r_minMag( float16_t, bool );
+int_fast64_t f16_to_i64_r_minMag(float16_t, bool);
-float32_t f16_to_f32( float16_t );
+float32_t f16_to_f32(float16_t);
-float64_t f16_to_f64( float16_t );
+float64_t f16_to_f64(float16_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t f16_to_extF80( float16_t );
+extFloat80_t f16_to_extF80(float16_t);
-float128_t f16_to_f128( float16_t );
+float128_t f16_to_f128(float16_t);
 #endif
-void f16_to_extF80M( float16_t, extFloat80_t * );
+void f16_to_extF80M(float16_t, extFloat80_t*);
-void f16_to_f128M( float16_t, float128_t * );
+void f16_to_f128M(float16_t, float128_t*);
-float16_t f16_roundToInt( float16_t, uint_fast8_t, bool );
+float16_t f16_roundToInt(float16_t, uint_fast8_t, bool);
-float16_t f16_add( float16_t, float16_t );
+float16_t f16_add(float16_t, float16_t);
-float16_t f16_sub( float16_t, float16_t );
+float16_t f16_sub(float16_t, float16_t);
-float16_t f16_mul( float16_t, float16_t );
+float16_t f16_mul(float16_t, float16_t);
-float16_t f16_mulAdd( float16_t, float16_t, float16_t );
+float16_t f16_mulAdd(float16_t, float16_t, float16_t);
-float16_t f16_div( float16_t, float16_t );
+float16_t f16_div(float16_t, float16_t);
-float16_t f16_rem( float16_t, float16_t );
+float16_t f16_rem(float16_t, float16_t);
-float16_t f16_sqrt( float16_t );
+float16_t f16_sqrt(float16_t);
-bool f16_eq( float16_t, float16_t );
+bool f16_eq(float16_t, float16_t);
-bool f16_le( float16_t, float16_t );
+bool f16_le(float16_t, float16_t);
-bool f16_lt( float16_t, float16_t );
+bool f16_lt(float16_t, float16_t);
-bool f16_eq_signaling( float16_t, float16_t );
+bool f16_eq_signaling(float16_t, float16_t);
-bool f16_le_quiet( float16_t, float16_t );
+bool f16_le_quiet(float16_t, float16_t);
-bool f16_lt_quiet( float16_t, float16_t );
+bool f16_lt_quiet(float16_t, float16_t);
-bool f16_isSignalingNaN( float16_t );
+bool f16_isSignalingNaN(float16_t);
 
 /*----------------------------------------------------------------------------
 | 32-bit (single-precision) floating-point operations.
 *----------------------------------------------------------------------------*/
-uint_fast32_t f32_to_ui32( float32_t, uint_fast8_t, bool );
+uint_fast32_t f32_to_ui32(float32_t, uint_fast8_t, bool);
-uint_fast64_t f32_to_ui64( float32_t, uint_fast8_t, bool );
+uint_fast64_t f32_to_ui64(float32_t, uint_fast8_t, bool);
-int_fast32_t f32_to_i32( float32_t, uint_fast8_t, bool );
+int_fast32_t f32_to_i32(float32_t, uint_fast8_t, bool);
-int_fast64_t f32_to_i64( float32_t, uint_fast8_t, bool );
+int_fast64_t f32_to_i64(float32_t, uint_fast8_t, bool);
-uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool );
+uint_fast32_t f32_to_ui32_r_minMag(float32_t, bool);
-uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool );
+uint_fast64_t f32_to_ui64_r_minMag(float32_t, bool);
-int_fast32_t f32_to_i32_r_minMag( float32_t, bool );
+int_fast32_t f32_to_i32_r_minMag(float32_t, bool);
-int_fast64_t f32_to_i64_r_minMag( float32_t, bool );
+int_fast64_t f32_to_i64_r_minMag(float32_t, bool);
-float16_t f32_to_f16( float32_t );
+float16_t f32_to_f16(float32_t);
-float64_t f32_to_f64( float32_t );
+float64_t f32_to_f64(float32_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t f32_to_extF80( float32_t );
+extFloat80_t f32_to_extF80(float32_t);
-float128_t f32_to_f128( float32_t );
+float128_t f32_to_f128(float32_t);
 #endif
-void f32_to_extF80M( float32_t, extFloat80_t * );
+void f32_to_extF80M(float32_t, extFloat80_t*);
-void f32_to_f128M( float32_t, float128_t * );
+void f32_to_f128M(float32_t, float128_t*);
-float32_t f32_roundToInt( float32_t, uint_fast8_t, bool );
+float32_t f32_roundToInt(float32_t, uint_fast8_t, bool);
-float32_t f32_add( float32_t, float32_t );
+float32_t f32_add(float32_t, float32_t);
-float32_t f32_sub( float32_t, float32_t );
+float32_t f32_sub(float32_t, float32_t);
-float32_t f32_mul( float32_t, float32_t );
+float32_t f32_mul(float32_t, float32_t);
-float32_t f32_mulAdd( float32_t, float32_t, float32_t );
+float32_t f32_mulAdd(float32_t, float32_t, float32_t);
-float32_t f32_div( float32_t, float32_t );
+float32_t f32_div(float32_t, float32_t);
-float32_t f32_rem( float32_t, float32_t );
+float32_t f32_rem(float32_t, float32_t);
-float32_t f32_sqrt( float32_t );
+float32_t f32_sqrt(float32_t);
-bool f32_eq( float32_t, float32_t );
+bool f32_eq(float32_t, float32_t);
-bool f32_le( float32_t, float32_t );
+bool f32_le(float32_t, float32_t);
-bool f32_lt( float32_t, float32_t );
+bool f32_lt(float32_t, float32_t);
-bool f32_eq_signaling( float32_t, float32_t );
+bool f32_eq_signaling(float32_t, float32_t);
-bool f32_le_quiet( float32_t, float32_t );
+bool f32_le_quiet(float32_t, float32_t);
-bool f32_lt_quiet( float32_t, float32_t );
+bool f32_lt_quiet(float32_t, float32_t);
-bool f32_isSignalingNaN( float32_t );
+bool f32_isSignalingNaN(float32_t);
 
 /*----------------------------------------------------------------------------
 | 64-bit (double-precision) floating-point operations.
 *----------------------------------------------------------------------------*/
-uint_fast32_t f64_to_ui32( float64_t, uint_fast8_t, bool );
+uint_fast32_t f64_to_ui32(float64_t, uint_fast8_t, bool);
-uint_fast64_t f64_to_ui64( float64_t, uint_fast8_t, bool );
+uint_fast64_t f64_to_ui64(float64_t, uint_fast8_t, bool);
-int_fast32_t f64_to_i32( float64_t, uint_fast8_t, bool );
+int_fast32_t f64_to_i32(float64_t, uint_fast8_t, bool);
-int_fast64_t f64_to_i64( float64_t, uint_fast8_t, bool );
+int_fast64_t f64_to_i64(float64_t, uint_fast8_t, bool);
-uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool );
+uint_fast32_t f64_to_ui32_r_minMag(float64_t, bool);
-uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool );
+uint_fast64_t f64_to_ui64_r_minMag(float64_t, bool);
-int_fast32_t f64_to_i32_r_minMag( float64_t, bool );
+int_fast32_t f64_to_i32_r_minMag(float64_t, bool);
-int_fast64_t f64_to_i64_r_minMag( float64_t, bool );
+int_fast64_t f64_to_i64_r_minMag(float64_t, bool);
-float16_t f64_to_f16( float64_t );
+float16_t f64_to_f16(float64_t);
-float32_t f64_to_f32( float64_t );
+float32_t f64_to_f32(float64_t);
 #ifdef SOFTFLOAT_FAST_INT64
-extFloat80_t f64_to_extF80( float64_t );
+extFloat80_t f64_to_extF80(float64_t);
-float128_t f64_to_f128( float64_t );
+float128_t f64_to_f128(float64_t);
 #endif
-void f64_to_extF80M( float64_t, extFloat80_t * );
+void f64_to_extF80M(float64_t, extFloat80_t*);
-void f64_to_f128M( float64_t, float128_t * );
+void f64_to_f128M(float64_t, float128_t*);
-float64_t f64_roundToInt( float64_t, uint_fast8_t, bool );
+float64_t f64_roundToInt(float64_t, uint_fast8_t, bool);
-float64_t f64_add( float64_t, float64_t );
+float64_t f64_add(float64_t, float64_t);
-float64_t f64_sub( float64_t, float64_t );
+float64_t f64_sub(float64_t, float64_t);
-float64_t f64_mul( float64_t, float64_t );
+float64_t f64_mul(float64_t, float64_t);
-float64_t f64_mulAdd( float64_t, float64_t, float64_t );
+float64_t f64_mulAdd(float64_t, float64_t, float64_t);
-float64_t f64_div( float64_t, float64_t );
+float64_t f64_div(float64_t, float64_t);
-float64_t f64_rem( float64_t, float64_t );
+float64_t f64_rem(float64_t, float64_t);
-float64_t f64_sqrt( float64_t );
+float64_t f64_sqrt(float64_t);
-bool f64_eq( float64_t, float64_t );
+bool f64_eq(float64_t, float64_t);
-bool f64_le( float64_t, float64_t );
+bool f64_le(float64_t, float64_t);
-bool f64_lt( float64_t, float64_t );
+bool f64_lt(float64_t, float64_t);
-bool f64_eq_signaling( float64_t, float64_t );
+bool f64_eq_signaling(float64_t, float64_t);
-bool f64_le_quiet( float64_t, float64_t );
+bool f64_le_quiet(float64_t, float64_t);
-bool f64_lt_quiet( float64_t, float64_t );
+bool f64_lt_quiet(float64_t, float64_t);
-bool f64_isSignalingNaN( float64_t );
+bool f64_isSignalingNaN(float64_t);
 
 /*----------------------------------------------------------------------------
 | Rounding precision for 80-bit extended double-precision floating-point.
@@ -249,124 +244,118 @@ extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision;
 | 80-bit extended double-precision floating-point operations.
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool );
+uint_fast32_t extF80_to_ui32(extFloat80_t, uint_fast8_t, bool);
-uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool );
+uint_fast64_t extF80_to_ui64(extFloat80_t, uint_fast8_t, bool);
-int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool );
+int_fast32_t extF80_to_i32(extFloat80_t, uint_fast8_t, bool);
-int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool );
+int_fast64_t extF80_to_i64(extFloat80_t, uint_fast8_t, bool);
-uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool );
+uint_fast32_t extF80_to_ui32_r_minMag(extFloat80_t, bool);
-uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool );
+uint_fast64_t extF80_to_ui64_r_minMag(extFloat80_t, bool);
-int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool );
+int_fast32_t extF80_to_i32_r_minMag(extFloat80_t, bool);
-int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool );
+int_fast64_t extF80_to_i64_r_minMag(extFloat80_t, bool);
-float16_t extF80_to_f16( extFloat80_t );
+float16_t extF80_to_f16(extFloat80_t);
-float32_t extF80_to_f32( extFloat80_t );
+float32_t extF80_to_f32(extFloat80_t);
-float64_t extF80_to_f64( extFloat80_t );
+float64_t extF80_to_f64(extFloat80_t);
-float128_t extF80_to_f128( extFloat80_t );
+float128_t extF80_to_f128(extFloat80_t);
-extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool );
+extFloat80_t extF80_roundToInt(extFloat80_t, uint_fast8_t, bool);
-extFloat80_t extF80_add( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_add(extFloat80_t, extFloat80_t);
-extFloat80_t extF80_sub( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_sub(extFloat80_t, extFloat80_t);
-extFloat80_t extF80_mul( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_mul(extFloat80_t, extFloat80_t);
-extFloat80_t extF80_div( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_div(extFloat80_t, extFloat80_t);
-extFloat80_t extF80_rem( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_rem(extFloat80_t, extFloat80_t);
-extFloat80_t extF80_sqrt( extFloat80_t );
+extFloat80_t extF80_sqrt(extFloat80_t);
-bool extF80_eq( extFloat80_t, extFloat80_t );
+bool extF80_eq(extFloat80_t, extFloat80_t);
-bool extF80_le( extFloat80_t, extFloat80_t );
+bool extF80_le(extFloat80_t, extFloat80_t);
-bool extF80_lt( extFloat80_t, extFloat80_t );
+bool extF80_lt(extFloat80_t, extFloat80_t);
-bool extF80_eq_signaling( extFloat80_t, extFloat80_t );
+bool extF80_eq_signaling(extFloat80_t, extFloat80_t);
-bool extF80_le_quiet( extFloat80_t, extFloat80_t );
+bool extF80_le_quiet(extFloat80_t, extFloat80_t);
-bool extF80_lt_quiet( extFloat80_t, extFloat80_t );
+bool extF80_lt_quiet(extFloat80_t, extFloat80_t);
-bool extF80_isSignalingNaN( extFloat80_t );
+bool extF80_isSignalingNaN(extFloat80_t);
 #endif
-uint_fast32_t extF80M_to_ui32( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast32_t extF80M_to_ui32(const extFloat80_t*, uint_fast8_t, bool);
-uint_fast64_t extF80M_to_ui64( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast64_t extF80M_to_ui64(const extFloat80_t*, uint_fast8_t, bool);
-int_fast32_t extF80M_to_i32( const extFloat80_t *, uint_fast8_t, bool );
+int_fast32_t extF80M_to_i32(const extFloat80_t*, uint_fast8_t, bool);
-int_fast64_t extF80M_to_i64( const extFloat80_t *, uint_fast8_t, bool );
+int_fast64_t extF80M_to_i64(const extFloat80_t*, uint_fast8_t, bool);
-uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *, bool );
+uint_fast32_t extF80M_to_ui32_r_minMag(const extFloat80_t*, bool);
-uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *, bool );
+uint_fast64_t extF80M_to_ui64_r_minMag(const extFloat80_t*, bool);
-int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *, bool );
+int_fast32_t extF80M_to_i32_r_minMag(const extFloat80_t*, bool);
-int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *, bool );
+int_fast64_t extF80M_to_i64_r_minMag(const extFloat80_t*, bool);
-float16_t extF80M_to_f16( const extFloat80_t * );
+float16_t extF80M_to_f16(const extFloat80_t*);
-float32_t extF80M_to_f32( const extFloat80_t * );
+float32_t extF80M_to_f32(const extFloat80_t*);
-float64_t extF80M_to_f64( const extFloat80_t * );
+float64_t extF80M_to_f64(const extFloat80_t*);
-void extF80M_to_f128M( const extFloat80_t *, float128_t * );
+void extF80M_to_f128M(const extFloat80_t*, float128_t*);
-void
+void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*);
- extF80M_roundToInt(
+void extF80M_add(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
-     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
+void extF80M_sub(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
-void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_mul(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
-void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_div(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
-void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_rem(const extFloat80_t*, const extFloat80_t*, extFloat80_t*);
-void extF80M_div( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_sqrt(const extFloat80_t*, extFloat80_t*);
-void extF80M_rem( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+bool extF80M_eq(const extFloat80_t*, const extFloat80_t*);
-void extF80M_sqrt( const extFloat80_t *, extFloat80_t * );
+bool extF80M_le(const extFloat80_t*, const extFloat80_t*);
-bool extF80M_eq( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_lt(const extFloat80_t*, const extFloat80_t*);
-bool extF80M_le( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_eq_signaling(const extFloat80_t*, const extFloat80_t*);
-bool extF80M_lt( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_le_quiet(const extFloat80_t*, const extFloat80_t*);
-bool extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_lt_quiet(const extFloat80_t*, const extFloat80_t*);
-bool extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_isSignalingNaN(const extFloat80_t*);
-bool extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * );
-bool extF80M_isSignalingNaN( const extFloat80_t * );
 
 /*----------------------------------------------------------------------------
 | 128-bit (quadruple-precision) floating-point operations.
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_INT64
-uint_fast32_t f128_to_ui32( float128_t, uint_fast8_t, bool );
+uint_fast32_t f128_to_ui32(float128_t, uint_fast8_t, bool);
-uint_fast64_t f128_to_ui64( float128_t, uint_fast8_t, bool );
+uint_fast64_t f128_to_ui64(float128_t, uint_fast8_t, bool);
-int_fast32_t f128_to_i32( float128_t, uint_fast8_t, bool );
+int_fast32_t f128_to_i32(float128_t, uint_fast8_t, bool);
-int_fast64_t f128_to_i64( float128_t, uint_fast8_t, bool );
+int_fast64_t f128_to_i64(float128_t, uint_fast8_t, bool);
-uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool );
+uint_fast32_t f128_to_ui32_r_minMag(float128_t, bool);
-uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool );
+uint_fast64_t f128_to_ui64_r_minMag(float128_t, bool);
-int_fast32_t f128_to_i32_r_minMag( float128_t, bool );
+int_fast32_t f128_to_i32_r_minMag(float128_t, bool);
-int_fast64_t f128_to_i64_r_minMag( float128_t, bool );
+int_fast64_t f128_to_i64_r_minMag(float128_t, bool);
-float16_t f128_to_f16( float128_t );
+float16_t f128_to_f16(float128_t);
-float32_t f128_to_f32( float128_t );
+float32_t f128_to_f32(float128_t);
-float64_t f128_to_f64( float128_t );
+float64_t f128_to_f64(float128_t);
-extFloat80_t f128_to_extF80( float128_t );
+extFloat80_t f128_to_extF80(float128_t);
-float128_t f128_roundToInt( float128_t, uint_fast8_t, bool );
+float128_t f128_roundToInt(float128_t, uint_fast8_t, bool);
-float128_t f128_add( float128_t, float128_t );
+float128_t f128_add(float128_t, float128_t);
-float128_t f128_sub( float128_t, float128_t );
+float128_t f128_sub(float128_t, float128_t);
-float128_t f128_mul( float128_t, float128_t );
+float128_t f128_mul(float128_t, float128_t);
-float128_t f128_mulAdd( float128_t, float128_t, float128_t );
+float128_t f128_mulAdd(float128_t, float128_t, float128_t);
-float128_t f128_div( float128_t, float128_t );
+float128_t f128_div(float128_t, float128_t);
-float128_t f128_rem( float128_t, float128_t );
+float128_t f128_rem(float128_t, float128_t);
-float128_t f128_sqrt( float128_t );
+float128_t f128_sqrt(float128_t);
-bool f128_eq( float128_t, float128_t );
+bool f128_eq(float128_t, float128_t);
-bool f128_le( float128_t, float128_t );
+bool f128_le(float128_t, float128_t);
-bool f128_lt( float128_t, float128_t );
+bool f128_lt(float128_t, float128_t);
-bool f128_eq_signaling( float128_t, float128_t );
+bool f128_eq_signaling(float128_t, float128_t);
-bool f128_le_quiet( float128_t, float128_t );
+bool f128_le_quiet(float128_t, float128_t);
-bool f128_lt_quiet( float128_t, float128_t );
+bool f128_lt_quiet(float128_t, float128_t);
-bool f128_isSignalingNaN( float128_t );
+bool f128_isSignalingNaN(float128_t);
 #endif
-uint_fast32_t f128M_to_ui32( const float128_t *, uint_fast8_t, bool );
+uint_fast32_t f128M_to_ui32(const float128_t*, uint_fast8_t, bool);
-uint_fast64_t f128M_to_ui64( const float128_t *, uint_fast8_t, bool );
+uint_fast64_t f128M_to_ui64(const float128_t*, uint_fast8_t, bool);
-int_fast32_t f128M_to_i32( const float128_t *, uint_fast8_t, bool );
+int_fast32_t f128M_to_i32(const float128_t*, uint_fast8_t, bool);
-int_fast64_t f128M_to_i64( const float128_t *, uint_fast8_t, bool );
+int_fast64_t f128M_to_i64(const float128_t*, uint_fast8_t, bool);
-uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *, bool );
+uint_fast32_t f128M_to_ui32_r_minMag(const float128_t*, bool);
-uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *, bool );
+uint_fast64_t f128M_to_ui64_r_minMag(const float128_t*, bool);
-int_fast32_t f128M_to_i32_r_minMag( const float128_t *, bool );
+int_fast32_t f128M_to_i32_r_minMag(const float128_t*, bool);
-int_fast64_t f128M_to_i64_r_minMag( const float128_t *, bool );
+int_fast64_t f128M_to_i64_r_minMag(const float128_t*, bool);
-float16_t f128M_to_f16( const float128_t * );
+float16_t f128M_to_f16(const float128_t*);
-float32_t f128M_to_f32( const float128_t * );
+float32_t f128M_to_f32(const float128_t*);
-float64_t f128M_to_f64( const float128_t * );
+float64_t f128M_to_f64(const float128_t*);
-void f128M_to_extF80M( const float128_t *, extFloat80_t * );
+void f128M_to_extF80M(const float128_t*, extFloat80_t*);
-void f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * );
+void f128M_roundToInt(const float128_t*, uint_fast8_t, bool, float128_t*);
-void f128M_add( const float128_t *, const float128_t *, float128_t * );
+void f128M_add(const float128_t*, const float128_t*, float128_t*);
-void f128M_sub( const float128_t *, const float128_t *, float128_t * );
+void f128M_sub(const float128_t*, const float128_t*, float128_t*);
-void f128M_mul( const float128_t *, const float128_t *, float128_t * );
+void f128M_mul(const float128_t*, const float128_t*, float128_t*);
-void
+void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*);
- f128M_mulAdd(
+void f128M_div(const float128_t*, const float128_t*, float128_t*);
-     const float128_t *, const float128_t *, const float128_t *, float128_t *
+void f128M_rem(const float128_t*, const float128_t*, float128_t*);
- );
+void f128M_sqrt(const float128_t*, float128_t*);
-void f128M_div( const float128_t *, const float128_t *, float128_t * );
+bool f128M_eq(const float128_t*, const float128_t*);
-void f128M_rem( const float128_t *, const float128_t *, float128_t * );
+bool f128M_le(const float128_t*, const float128_t*);
-void f128M_sqrt( const float128_t *, float128_t * );
+bool f128M_lt(const float128_t*, const float128_t*);
-bool f128M_eq( const float128_t *, const float128_t * );
+bool f128M_eq_signaling(const float128_t*, const float128_t*);
-bool f128M_le( const float128_t *, const float128_t * );
+bool f128M_le_quiet(const float128_t*, const float128_t*);
-bool f128M_lt( const float128_t *, const float128_t * );
+bool f128M_lt_quiet(const float128_t*, const float128_t*);
-bool f128M_eq_signaling( const float128_t *, const float128_t * );
+bool f128M_isSignalingNaN(const float128_t*);
-bool f128M_le_quiet( const float128_t *, const float128_t * );
-bool f128M_lt_quiet( const float128_t *, const float128_t * );
-bool f128M_isSignalingNaN( const float128_t * );
 
 #endif
-

softfloat/source/include/softfloat_types.h

@@ -47,10 +47,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | the types below may, if desired, be defined as aliases for the native types
 | (typically 'float' and 'double', and possibly 'long double').
 *----------------------------------------------------------------------------*/
-typedef struct { uint16_t v; } float16_t;
+typedef struct {
-typedef struct { uint32_t v; } float32_t;
+    uint16_t v;
-typedef struct { uint64_t v; } float64_t;
+} float16_t;
-typedef struct { uint64_t v[2]; } float128_t;
+typedef struct {
+    uint32_t v;
+} float32_t;
+typedef struct {
+    uint64_t v;
+} float64_t;
+typedef struct {
+    uint64_t v[2];
+} float128_t;
 
 /*----------------------------------------------------------------------------
 | The format of an 80-bit extended floating-point number in memory.  This
@@ -58,9 +66,15 @@ typedef struct { uint64_t v[2]; } float128_t;
 | named 'signif'.
 *----------------------------------------------------------------------------*/
 #ifdef LITTLEENDIAN
-struct extFloat80M { uint64_t signif; uint16_t signExp; };
+struct extFloat80M {
+    uint64_t signif;
+    uint16_t signExp;
+};
 #else
-struct extFloat80M { uint16_t signExp; uint64_t signif; };
+struct extFloat80M {
+    uint16_t signExp;
+    uint64_t signif;
+};
 #endif
 
 /*----------------------------------------------------------------------------
@@ -78,4 +92,3 @@ struct extFloat80M { uint16_t signExp; uint64_t signif; };
 typedef struct extFloat80M extFloat80_t;
 
 #endif
-

src-gen/.gitignore

@@ -0,0 +1,3 @@
+/iss
+/vm
+/sysc

src/iss/arch/hwl.h

@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_M_P_HWL_H
 #define _RISCV_HART_M_P_HWL_H
 
+#include "riscv_hart_common.h"
 #include <iss/vm_types.h>
 
 namespace iss {
@@ -46,49 +47,71 @@ public:
     using this_class = hwl<BASE>;
     using reg_t = typename BASE::reg_t;
 
-    hwl();
+    hwl(feature_config cfg = feature_config{});
     virtual ~hwl() = default;
 
 protected:
-    iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
+    iss::status read_custom_csr_reg(unsigned addr, reg_t& val) override;
     iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
 };
 
-
+template <typename BASE>
-template<typename BASE>
+inline hwl<BASE>::hwl(feature_config cfg)
-inline hwl<BASE>::hwl() {
+: BASE(cfg) {
-    for (unsigned addr = 0x800; addr < 0x803; ++addr){
+    for(unsigned addr = 0x800; addr < 0x803; ++addr) {
         this->register_custom_csr_rd(addr);
         this->register_custom_csr_wr(addr);
     }
-    for (unsigned addr = 0x804; addr < 0x807; ++addr){
+    for(unsigned addr = 0x804; addr < 0x807; ++addr) {
         this->register_custom_csr_rd(addr);
         this->register_custom_csr_wr(addr);
     }
 }
 
-template<typename BASE>
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t& val) {
-inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
+    switch(addr) {
-    switch(addr){
+    case 0x800:
-    case 0x800: val = this->reg.lpstart0; break;
+        val = this->reg.lpstart0;
-    case 0x801: val = this->reg.lpend0;   break;
+        break;
-    case 0x802: val = this->reg.lpcount0; break;
+    case 0x801:
-    case 0x804: val = this->reg.lpstart1; break;
+        val = this->reg.lpend0;
-    case 0x805: val = this->reg.lpend1;   break;
+        break;
-    case 0x806: val = this->reg.lpcount1; break;
+    case 0x802:
+        val = this->reg.lpcount0;
+        break;
+    case 0x804:
+        val = this->reg.lpstart1;
+        break;
+    case 0x805:
+        val = this->reg.lpend1;
+        break;
+    case 0x806:
+        val = this->reg.lpcount1;
+        break;
     }
     return iss::Ok;
 }
 
-template<typename BASE>
+template <typename BASE> inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
-inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+    switch(addr) {
-    switch(addr){
+    case 0x800:
-    case 0x800: this->reg.lpstart0 = val; break;
+        this->reg.lpstart0 = val;
-    case 0x801: this->reg.lpend0   = val; break;
+        break;
-    case 0x802: this->reg.lpcount0 = val; break;
+    case 0x801:
-    case 0x804: this->reg.lpstart1 = val; break;
+        this->reg.lpend0 = val;
-    case 0x805: this->reg.lpend1   = val; break;
+        break;
-    case 0x806: this->reg.lpcount1 = val; break;
+    case 0x802:
+        this->reg.lpcount0 = val;
+        break;
+    case 0x804:
+        this->reg.lpstart1 = val;
+        break;
+    case 0x805:
+        this->reg.lpend1 = val;
+        break;
+    case 0x806:
+        this->reg.lpcount1 = val;
+        break;
     }
     return iss::Ok;
 }
@@ -96,5 +119,4 @@ inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg
 } // namespace arch
 } // namespace iss
 
-
 #endif /* _RISCV_HART_M_P_H */

src/iss/arch/riscv_hart_common.h

@@ -35,15 +35,29 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
-#include "iss/arch_if.h"
 #include <cstdint>
+#include <elfio/elfio.hpp>
+#include <fmt/format.h>
+#include <iss/arch_if.h>
+#include <iss/log_categories.h>
+#include <string>
+#include <unordered_map>
+#include <util/logging.h>
+
+#if defined(__GNUC__)
+#define likely(x) ::__builtin_expect(!!(x), 1)
+#define unlikely(x) ::__builtin_expect(!!(x), 0)
+#else
+#define likely(x) x
+#define unlikely(x) x
+#endif
 
 namespace iss {
 namespace arch {
 
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
 
-enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
+enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
 
 enum riscv_csr {
     /* user-level CSR */
@@ -51,12 +65,18 @@ enum riscv_csr {
     ustatus = 0x000,
     uie = 0x004,
     utvec = 0x005,
+    utvt = 0x007, // CLIC
     // User Trap Handling
     uscratch = 0x040,
     uepc = 0x041,
     ucause = 0x042,
     utval = 0x043,
     uip = 0x044,
+    uxnti = 0x045,        // CLIC
+    uintstatus = 0xCB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh = 0x047,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw = 0x048,  // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
     // User Floating-Point CSRs
     fflags = 0x001,
     frm = 0x002,
@@ -106,19 +126,18 @@ enum riscv_csr {
     mie = 0x304,
     mtvec = 0x305,
     mcounteren = 0x306,
-    mtvt = 0x307, //CLIC
+    mtvt = 0x307, // CLIC
     // Machine Trap Handling
     mscratch = 0x340,
     mepc = 0x341,
     mcause = 0x342,
     mtval = 0x343,
     mip = 0x344,
-    mxnti = 0x345, //CLIC
+    mxnti = 0x345,        // CLIC
-    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus = 0xFB1,   // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh = 0x347,   // MRW Interrupt-level threshold (CLIC) - addr subject to change
     mscratchcsw = 0x348,  // MRW Conditional scratch swap on priv mode change (CLIC)
     mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
-    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
@@ -170,7 +189,6 @@ enum riscv_csr {
     dscratch1 = 0x7B3
 };
 
-
 enum {
     PGSHIFT = 12,
     PTE_PPN_SHIFT = 10,
@@ -188,7 +206,7 @@ enum {
 
 template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
 
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4 };
 
 enum {
     ISA_A = 1,
@@ -216,10 +234,13 @@ struct vm_info {
 
 struct feature_config {
     uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
     unsigned clic_num_irq{16};
     unsigned clic_num_trigger{0};
     uint64_t tcm_base{0x10000000};
     uint64_t tcm_size{0x8000};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
 };
 
 class trap_load_access_fault : public trap_access {
@@ -248,19 +269,19 @@ public:
     : trap_access(15 << 16, badaddr) {}
 };
 
-inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
+inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t* const data, unsigned length) {
     auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
-    switch (offs & 0x3) {
+    switch(offs & 0x3) {
     case 0:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(data + i) = *(reg_ptr + i);
         break;
     case 1:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(data + i) = *(reg_ptr + 1 + i);
         break;
     case 2:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(data + i) = *(reg_ptr + 2 + i);
         break;
     case 3:
@@ -269,28 +290,83 @@ inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, u
     }
 }
 
-inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
+inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const data, unsigned length) {
     auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
-    switch (offs & 0x3) {
+    switch(offs & 0x3) {
     case 0:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(reg_ptr + i) = *(data + i);
         break;
     case 1:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(reg_ptr + 1 + i) = *(data + i);
         break;
     case 2:
-        for (auto i = 0U; i < length; ++i)
+        for(auto i = 0U; i < length; ++i)
             *(reg_ptr + 2 + i) = *(data + i);
         break;
     case 3:
-        *(reg_ptr + 3) = *data ;
+        *(reg_ptr + 3) = *data;
         break;
     }
 }
+struct riscv_hart_common {
+    riscv_hart_common(){};
+    ~riscv_hart_common(){};
+    std::unordered_map<std::string, uint64_t> symbol_table;
 
-}
+    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
-}
+        if(!symbol_table.empty())
+            return symbol_table;
+        FILE* fp = fopen(name.c_str(), "r");
+        if(fp) {
+            std::array<char, 5> buf;
+            auto n = fread(buf.data(), 1, 4, fp);
+            fclose(fp);
+            if(n != 4)
+                throw std::runtime_error("input file has insufficient size");
+            buf[4] = 0;
+            if(strcmp(buf.data() + 1, "ELF") == 0) {
+                // Create elfio reader
+                ELFIO::elfio reader;
+                // Load ELF data
+                if(!reader.load(name))
+                    throw std::runtime_error("could not process elf file");
+                // check elf properties
+                if(reader.get_type() != ET_EXEC)
+                    throw std::runtime_error("wrong elf type in file");
+                if(reader.get_machine() != EM_RISCV)
+                    throw std::runtime_error("wrong elf machine in file");
+                const auto sym_sec = reader.sections[".symtab"];
+                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
+                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
+                    auto sym_no = symbols.get_symbols_num();
+                    std::string name;
+                    ELFIO::Elf64_Addr value = 0;
+                    ELFIO::Elf_Xword size = 0;
+                    unsigned char bind = 0;
+                    unsigned char type = 0;
+                    ELFIO::Elf_Half section = 0;
+                    unsigned char other = 0;
+                    for(auto i = 0U; i < sym_no; ++i) {
+                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                        if(name != "") {
+                            this->symbol_table[name] = value;
+#ifndef NDEBUG
+                            CPPLOG(DEBUG) << "Found Symbol " << name;
+#endif
+                        }
+                    }
+                }
+                return symbol_table;
+            }
+            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
+        } else
+            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    };
+};
+
+} // namespace arch
+} // namespace iss
 
 #endif

src/iss/arch/tgc5c.cpp

@@ -30,40 +30,41 @@
  *
  *******************************************************************************/
 
+// clang-format off
+#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
-constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
 
-tgc_c::tgc_c()  = default;
+tgc5c::tgc5c()  = default;
 
-tgc_c::~tgc_c() = default;
+tgc5c::~tgc5c() = default;
 
-void tgc_c::reset(uint64_t address) {
+void tgc5c::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
+    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
         *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    trap_state=0;
+    reg.trap_state=0;
-    icount=0;
+    reg.icount=0;
 }
 
-uint8_t *tgc_c::get_regs_base_ptr() {
+uint8_t *tgc5c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }
 
-tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
+tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
-    return phys_addr_t(pc); // change logical address to physical address
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
 }
-
+// clang-format on

src/iss/arch/tgc_mapper.h

@@ -0,0 +1,57 @@
+#ifndef _ISS_ARCH_TGC_MAPPER_H
+#define _ISS_ARCH_TGC_MAPPER_H
+
+#include "riscv_hart_m_p.h"
+#include "tgc5c.h"
+using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
+#ifdef CORE_TGC5A
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5a.h>
+using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
+#endif
+#ifdef CORE_TGC5B
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5b.h>
+using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
+#endif
+#ifdef CORE_TGC5C_XRB_NN
+#include "hwl.h"
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc5c_xrb_nn.h>
+using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
+#endif
+#ifdef CORE_TGC5D
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d.h>
+using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5D_XRB_MAC
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d_xrb_mac.h>
+using tgc5d_xrb_mac_plat_type =
+    iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac,
+                               (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5D_XRB_NN
+#include "hwl.h"
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5d_xrb_nn.h>
+using tgc5d_xrb_nn_plat_type =
+    iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn,
+                                              (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
+#endif
+#ifdef CORE_TGC5E
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5e.h>
+using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC5X
+#include "riscv_hart_mu_p.h"
+#include <iss/arch/tgc5x.h>
+using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC |
+                                                                                             iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+#endif
+
+#endif

src/iss/arch/wt_cache.h

@@ -0,0 +1,171 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_WT_CACHE_H
+#define _RISCV_HART_M_P_WT_CACHE_H
+
+#include <iss/vm_types.h>
+#include <map>
+#include <memory>
+#include <util/ities.h>
+#include <vector>
+
+namespace iss {
+namespace arch {
+namespace cache {
+
+enum class state { INVALID, VALID };
+struct line {
+    uint64_t tag_addr{0};
+    state st{state::INVALID};
+    std::vector<uint8_t> data;
+    line(unsigned line_sz)
+    : data(line_sz) {}
+};
+struct set {
+    std::vector<line> ways;
+    set(unsigned ways_count, line const& l)
+    : ways(ways_count, l) {}
+};
+struct cache {
+    std::vector<set> sets;
+
+    cache(unsigned size, unsigned line_sz, unsigned ways) {
+        line const ref_line{line_sz};
+        set const ref_set{ways, ref_line};
+        sets.resize(size / (ways * line_sz), ref_set);
+    }
+};
+
+struct wt_policy {
+    bool is_cacheline_hit(cache& c);
+};
+} // namespace cache
+
+// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
+template <typename BASE> class wt_cache : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = wt_cache<BASE>;
+    using reg_t = typename BASE::reg_t;
+    using mem_read_f = typename BASE::mem_read_f;
+    using mem_write_f = typename BASE::mem_write_f;
+    using phys_addr_t = typename BASE::phys_addr_t;
+
+    wt_cache(feature_config cfg = feature_config{});
+    virtual ~wt_cache() = default;
+
+    unsigned size{4096};
+    unsigned line_sz{64};
+    unsigned ways{1};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+
+protected:
+    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t* const);
+    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const* const);
+    std::function<mem_read_f> cache_mem_rd_delegate;
+    std::function<mem_write_f> cache_mem_wr_delegate;
+    std::unique_ptr<cache::cache> dcache_ptr;
+    std::unique_ptr<cache::cache> icache_ptr;
+    size_t get_way_select() { return 0; }
+};
+
+template <typename BASE>
+inline wt_cache<BASE>::wt_cache(feature_config cfg)
+: BASE(cfg)
+, io_address{cfg.io_address}
+, io_addr_mask{cfg.io_addr_mask} {
+    auto cb = base_class::replace_mem_access(
+        [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l, d); },
+        [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l, d); });
+    cache_mem_rd_delegate = cb.first;
+    cache_mem_wr_delegate = cb.second;
+}
+
+template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+    if(!icache_ptr) {
+        icache_ptr.reset(new cache::cache(size, line_sz, ways));
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    }
+    if((a.val & io_addr_mask) != io_address) {
+        auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
+        auto tag_addr = a.val >> util::ilog2(line_sz);
+        auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr];
+        for(auto& cl : set.ways) {
+            if(cl.st == cache::state::VALID && cl.tag_addr == tag_addr) {
+                auto start_addr = a.val & (line_sz - 1);
+                for(auto i = 0U; i < l; ++i)
+                    d[i] = cl.data[start_addr + i];
+                return iss::Ok;
+            }
+        }
+        auto& cl = set.ways[get_way_select()];
+        phys_addr_t cl_addr{a};
+        cl_addr.val = tag_addr << util::ilog2(line_sz);
+        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
+        cl.tag_addr = tag_addr;
+        cl.st = cache::state::VALID;
+        auto start_addr = a.val & (line_sz - 1);
+        for(auto i = 0U; i < l; ++i)
+            d[i] = cl.data[start_addr + i];
+        return iss::Ok;
+    } else
+        return cache_mem_rd_delegate(a, l, d);
+}
+
+template <typename BASE> iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+    if(!dcache_ptr)
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    auto res = cache_mem_wr_delegate(a, l, d);
+    if(res == iss::Ok && ((a.val & io_addr_mask) != io_address)) {
+        auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
+        auto tag_addr = a.val >> util::ilog2(line_sz);
+        auto& set = dcache_ptr->sets[set_addr];
+        for(auto& cl : set.ways) {
+            if(cl.st == cache::state::VALID && cl.tag_addr == tag_addr) {
+                auto start_addr = a.val & (line_sz - 1);
+                for(auto i = 0U; i < l; ++i)
+                    cl.data[start_addr + i] = d[i];
+                break;
+            }
+        }
+    }
+    return res;
+}
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */

src/iss/debugger/riscv_target_adapter.h

@@ -53,20 +53,20 @@ using namespace iss::debugger;
 
 template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
 public:
-    riscv_target_adapter(server_if *srv, iss::arch_if *core)
+    riscv_target_adapter(server_if* srv, iss::arch_if* core)
     : target_adapter_base(srv)
     , core(core) {}
 
     /*============== Thread Control ===============================*/
 
     /* Set generic thread */
-    status set_gen_thread(rp_thread_ref &thread) override;
+    status set_gen_thread(rp_thread_ref& thread) override;
 
     /* Set control thread */
-    status set_ctrl_thread(rp_thread_ref &thread) override;
+    status set_ctrl_thread(rp_thread_ref& thread) override;
 
     /* Get thread status */
-    status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
+    status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
 
     /*============= Register Access ================================*/
 
@@ -74,79 +74,77 @@ public:
      target byte order. If  register is not available
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
-    status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
+    status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
 
     /* Write all registers. buf is 4-byte aligned and it is in target
      byte order */
-    status write_registers(const std::vector<uint8_t> &data) override;
+    status write_registers(const std::vector<uint8_t>& data) override;
 
     /* Read one register. buf is 4-byte aligned and it is in
      target byte order. If  register is not available
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
-    status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
+    status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
-                                std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
-    status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
+    status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
 
     /*=================== Memory Access =====================*/
 
     /* Read memory, buf is 4-bytes aligned and it is in target
      byte order */
-    status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
+    status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
 
     /* Write memory, buf is 4-bytes aligned and it is in target
      byte order */
-    status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
+    status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
 
-    status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
+    status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
 
-    status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
+    status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
-                             size_t &num, bool &done) override;
+                             bool& done) override;
 
-    status current_thread_query(rp_thread_ref &thread) override;
+    status current_thread_query(rp_thread_ref& thread) override;
 
-    status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
+    status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
 
-    status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
+    status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
 
-    status raw_query(std::string in_buf, std::string &out_buf) override;
+    status raw_query(std::string in_buf, std::string& out_buf) override;
 
-    status threadinfo_query(int first, std::string &out_buf) override;
+    status threadinfo_query(int first, std::string& out_buf) override;
 
-    status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
+    status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
 
-    status packetsize_query(std::string &out_buf) override;
+    status packetsize_query(std::string& out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function<void(unsigned)> stop_callback) override;
-                            std::function<void(unsigned)> stop_callback) override;
 
-    status target_xml_query(std::string &out_buf) override;
+    status target_xml_query(std::string& out_buf) override;
 
 protected:
-    static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
+    static inline constexpr addr_t map_addr(const addr_t& i) { return i; }
 
-    iss::arch_if *core;
+    iss::arch_if* core;
     rp_thread_ref thread_idx;
 };
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
     thread_idx = thread;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
     thread_idx = thread;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
     alive = 1;
     return Ok;
 }
@@ -158,10 +156,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  * set if all threads are processed.
  */
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
+status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result,
-                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+                                                     size_t max_num, size_t& num, bool& done) {
-                                                     bool &done) {
+    if(first == 0) {
-    if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
         num = 1;
@@ -171,58 +168,57 @@ status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_
         return NotSupported;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
     thread = thread_idx;
     return Ok;
 }
 
-template <typename ARCH>
+template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
-status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
+    CPPLOG(TRACE) << "reading target registers";
-    LOG(TRACE) << "reading target registers";
     // return idx<0?:;
     data.clear();
     avail.clear();
-    const uint8_t *reg_base = core->get_regs_base_ptr();
+    const uint8_t* reg_base = core->get_regs_base_ptr();
-    auto start_reg=arch::traits<ARCH>::X0;
+    auto start_reg = arch::traits<ARCH>::X0;
-    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t reg_no = start_reg; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
-        for (size_t j = 0; j < reg_width; ++j) {
+        for(size_t j = 0; j < reg_width; ++j) {
             data.push_back(*(reg_base + offset + j));
             avail.push_back(0xff);
         }
     }
     // work around fill with F type registers
-//    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
-//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-//            for (size_t j = 0; j < reg_width; ++j) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
-//                data.push_back(0x0);
+    //                data.push_back(0x0);
-//                avail.push_back(0x00);
+    //                avail.push_back(0x00);
-//            }
+    //            }
-//            // if(arch::traits<ARCH>::XLEN < 64)
+    //            // if(arch::traits<ARCH>::XLEN < 64)
-//            //     for(unsigned j=0; j<4; ++j){
+    //            //     for(unsigned j=0; j<4; ++j){
-//            //         data.push_back(0x0);
+    //            //         data.push_back(0x0);
-//            //         avail.push_back(0x00);
+    //            //         avail.push_back(0x00);
-//            //     }
+    //            //     }
-//        }
+    //        }
-//    }
+    //    }
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
-    auto start_reg=arch::traits<ARCH>::X0;
+    auto start_reg = arch::traits<ARCH>::X0;
-    auto *reg_base = core->get_regs_base_ptr();
+    auto* reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    bool e_ext = arch::traits<ARCH>::PC<32;
+    bool e_ext = arch::traits<ARCH>::PC < 32;
-    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
-        if(e_ext && reg_no>15){
+        if(e_ext && reg_no > 15) {
-            if(reg_no==32){
+            if(reg_no == 32) {
                 auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
                 auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
                 std::copy(iter, iter + reg_width, reg_base);
             } else {
-                const uint64_t zero_val=0;
+                const uint64_t zero_val = 0;
                 auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
                 auto iter = (uint8_t*)&zero_val;
                 std::copy(iter, iter + reg_width, reg_base);
@@ -239,12 +235,11 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 }
 
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
+status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
-                                                        std::vector<uint8_t> &avail) {
+    if(reg_no < 65) {
-    if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
-        auto *reg_base = core->get_regs_base_ptr();
+        auto* reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         data.resize(reg_width);
         avail.resize(reg_width);
@@ -261,10 +256,9 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
     return data.size() > 0 ? Ok : Err;
 }
 
-template <typename ARCH>
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
-status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
+    if(reg_no < 65) {
-    if (reg_no < 65) {
+        auto* reg_base = core->get_regs_base_ptr();
-        auto *reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
@@ -275,41 +269,36 @@ status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, co
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
     auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
     auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
     auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
     auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
 
 template <typename ARCH>
-status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
+status riscv_target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
     return NotSupported;
 }
 
-template <typename ARCH>
+template <typename ARCH> status riscv_target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
-status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
     text = 0;
     data = 0;
     bss = 0;
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; }
-    return NotSupported;
-}
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; }
-    return NotSupported;
-}
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
-    if (first) {
+    if(first) {
         out_buf = fmt::format("m{:x}", thread_idx.val);
     } else {
         out_buf = "l";
@@ -317,8 +306,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int
     return Ok;
 }
 
-template <typename ARCH>
+template <typename ARCH> status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
-status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
     std::array<char, 20> buf;
     memset(buf.data(), 0, 20);
     sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
@@ -326,48 +314,61 @@ status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &th
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
     out_buf = "PacketSize=1000";
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+        CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
-               << saddr.val << std::dec;
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Ok;
-}
-
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
-    if (handle) {
-        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
                       << std::dec;
-        // TODO: check length of addr range
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-        target_adapter_base::bp_lut.removeEntry(handle);
-        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+    }
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
         return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+        if(handle) {
+            CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
+            // TODO: check length of addr range
+            target_adapter_base::bp_lut.removeEntry(handle);
+            CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            return Ok;
+        }
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        return Err;
+    }
+    }
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
                                                     std::function<void(unsigned)> stop_callback) {
-    auto *reg_base = core->get_regs_base_ptr();
+    auto* reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
-    const uint8_t *iter = reinterpret_cast<const uint8_t *>(&addr);
+    const uint8_t* iter = reinterpret_cast<const uint8_t*>(&addr);
     std::copy(iter, iter + reg_width, reg_base);
     return resume_from_current(step, sig, thread, stop_callback);
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
     const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
                           "<target><architecture>riscv:rv32</architecture>"
                           //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
@@ -454,7 +455,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
 </target>
 
  */
-}
+} // namespace debugger
-}
+} // namespace iss
 
 #endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/iss/factory.h

@@ -0,0 +1,106 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_
+
+#include <algorithm>
+#include <functional>
+#include <iss/iss.h>
+#include <memory>
+#include <string>
+#include <unordered_map>
+#include <vector>
+
+namespace iss {
+
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr = std::unique_ptr<iss::vm_if>;
+
+template <typename PLAT> std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port) {
+    using core_type = typename PLAT::core;
+    core_type* lcpu = new PLAT();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_TCC
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+    return {nullptr, nullptr};
+}
+
+class core_factory {
+    using cpu_ptr = std::unique_ptr<iss::arch_if>;
+    using vm_ptr = std::unique_ptr<iss::vm_if>;
+    using base_t = std::tuple<cpu_ptr, vm_ptr>;
+    using create_fn = std::function<base_t(unsigned, void*)>;
+    using registry_t = std::unordered_map<std::string, create_fn>;
+
+    registry_t registry;
+
+    core_factory() = default;
+    core_factory(const core_factory&) = delete;
+    core_factory& operator=(const core_factory&) = delete;
+
+public:
+    static core_factory& instance() {
+        static core_factory bf;
+        return bf;
+    }
+
+    bool register_creator(const std::string& className, create_fn const& fn) {
+        registry[className] = fn;
+        return true;
+    }
+
+    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+        registry_t::const_iterator regEntry = registry.find(className);
+        if(regEntry != registry.end())
+            return regEntry->second(gdb_port, init_data);
+        return {nullptr, nullptr};
+    }
+
+    std::vector<std::string> get_names() {
+        std::vector<std::string> keys{registry.size()};
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
+                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
+        return keys;
+    }
+};
+
+} // namespace iss
+
+#endif /* _ISS_FACTORY_H_ */

src/iss/plugin/README.md

@@ -0,0 +1,8 @@
+# pctrace
+
+Trace functionality to allow visualizing coverage in lcov and cachegrind tools. Use environment variables NOCOMPRES and REGDUMP to toggle functionality.
+- NOCOMPRES: any value turns off the LZ4 compression
+- REGDUMP: any value switches to tracing the registers instead. Also turns off compression.
+
+Known Bugs: 
+- currently does not work correctly with jit backends, the plugin cant tell if instructions are compressed. Additionaly the cost of instrs that raise a trap is not known. It takes the cost of the instrid -1 (0 at the moment).

src/iss/plugin/cycle_estimate.cpp

@@ -0,0 +1,114 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "cycle_estimate.h"
+#include <iss/plugin/calculator.h>
+#include <yaml-cpp/yaml.h>
+
+#include <fstream>
+#include <iss/arch_if.h>
+#include <util/logging.h>
+
+using namespace std;
+
+iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
+: instr_if(nullptr)
+, config_file_name(config_file_name) {}
+
+iss::plugin::cycle_estimate::~cycle_estimate() = default;
+
+bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    assert(instr_if && "No instrumentation interface available but callback executed");
+    reg_base_ptr = reinterpret_cast<uint32_t*>(vm.get_arch()->get_regs_base_ptr());
+    if(!instr_if)
+        return false;
+    const string core_name = instr_if->core_type_name();
+    if(config_file_name.length() > 0) {
+        std::ifstream is(config_file_name);
+        if(is.is_open()) {
+            try {
+                auto root = YAML::LoadAll(is);
+                if(root.size() != 1) {
+                    CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
+                }
+                for(auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for(auto const& instr : instructions) {
+                        auto idx = instr.second["index"].as<unsigned>();
+                        if(delays.size() <= idx)
+                            delays.resize(idx + 1);
+                        auto& res = delays[idx];
+                        res.is_branch = instr.second["branch"].as<bool>();
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken = delay[0].as<uint64_t>();
+                            res.taken = delay[1].as<uint64_t>();
+                        } else {
+                            try {
+                                res.not_taken = delay.as<uint64_t>();
+                                res.taken = res.not_taken;
+                            } catch(const YAML::BadConversion& e) {
+                                res.f = iss::plugin::calculator(reg_base_ptr, delay.as<std::string>());
+                            }
+                        }
+                    }
+                }
+            } catch(YAML::ParserException& e) {
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
+            return false;
+        }
+    }
+    return true;
+}
+
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
+    size_t instr_id = instr_info.instr_id;
+    auto& entry = instr_id < delays.size() ? delays[instr_id] : illegal_desc;
+    if(instr_info.phase_id == PRE_SYNC) {
+        if(entry.f)
+            current_delay = entry.f(instr_if->get_instr_word());
+    } else {
+        if(!entry.f)
+            current_delay = instr_if->is_branch_taken() ? entry.taken : entry.not_taken;
+        if(current_delay > 1)
+            instr_if->update_last_instr_cycles(current_delay);
+        current_delay = 1;
+    }
+}

src/iss/plugin/cycle_estimate.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,6 +37,7 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
+#include <functional>
 #include <string>
 #include <unordered_map>
 #include <vector>
@@ -45,46 +46,44 @@ namespace iss {
 
 namespace plugin {
 
-class cycle_estimate: public iss::vm_plugin {
+class cycle_estimate : public vm_plugin {
-	BEGIN_BF_DECL(instr_desc, uint32_t)
+    struct instr_desc {
-		BF_FIELD(taken, 24, 8)
+        size_t size{0};
-		BF_FIELD(not_taken, 16, 8)
+        bool is_branch{false};
-        BF_FIELD(is_branch, 8, 8)
+        unsigned not_taken{1};
-        BF_FIELD(size, 0, 8)
+        unsigned taken{1};
-		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
+        std::function<unsigned(uint64_t)> f;
-			this->size=size;
+    };
-			this->taken=taken;
-			this->not_taken=not_taken;
-			this->is_branch=branch;
-		}
-	END_BF_DECL();
 
 public:
     cycle_estimate() = delete;
 
-    cycle_estimate(const cycle_estimate &) = delete;
+    cycle_estimate(const cycle_estimate&) = delete;
 
-    cycle_estimate(const cycle_estimate &&) = delete;
+    cycle_estimate(const cycle_estimate&&) = delete;
 
     cycle_estimate(std::string const& config_file_name);
 
     virtual ~cycle_estimate();
 
-    cycle_estimate &operator=(const cycle_estimate &) = delete;
+    cycle_estimate& operator=(const cycle_estimate&) = delete;
 
-    cycle_estimate &operator=(const cycle_estimate &&) = delete;
+    cycle_estimate& operator=(const cycle_estimate&&) = delete;
 
-    bool registration(const char *const version, vm_if &arch) override;
+    bool registration(const char* const version, vm_if& arch) override;
 
-    sync_type get_sync() override { return POST_SYNC; };
+    sync_type get_sync() override { return ALL_SYNC; };
 
-    void callback(instr_info_t instr_info, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;
 
 private:
-    iss::instrumentation_if *instr_if;
+    iss::instrumentation_if* instr_if{nullptr};
+    uint32_t* reg_base_ptr{nullptr};
+    instr_desc illegal_desc{};
     std::vector<instr_desc> delays;
+    unsigned current_delay{0};
     struct pair_hash {
-        size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
+        size_t operator()(const std::pair<uint64_t, uint64_t>& p) const {
             std::hash<uint64_t> hash;
             return hash(p.first) + hash(p.second);
         }
@@ -92,7 +91,7 @@ private:
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
     std::string config_file_name;
 };
-}
+} // namespace plugin
-}
+} // namespace iss
 
 #endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

src/iss/plugin/instruction_count.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,64 +32,65 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "iss/plugin/instruction_count.h"
+#include "instruction_count.h"
-#include "iss/instrumentation_if.h"
+#include <iss/instrumentation_if.h>
+#include <yaml-cpp/yaml.h>
 
+#include <fstream>
 #include <iss/arch_if.h>
 #include <util/logging.h>
-#include <fstream>
 
 iss::plugin::instruction_count::instruction_count(std::string config_file_name) {
-    if (config_file_name.length() > 0) {
+    if(config_file_name.length() > 0) {
         std::ifstream is(config_file_name);
-        if (is.is_open()) {
+        if(is.is_open()) {
             try {
-                is >> root;
+                auto root = YAML::LoadAll(is);
-            } catch (Json::RuntimeError &e) {
+                if(root.size() != 1) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                    CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
+                }
+                for(auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for(auto const& instr : instructions) {
+                        instr_delay res;
+                        res.instr_name = instr.first.as<std::string>();
+                        res.size = instr.second["encoding"].as<std::string>().size() - 2; // not counting 0b
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken_delay = delay[0].as<uint64_t>();
+                            res.taken_delay = delay[1].as<uint64_t>();
+                        } else {
+                            res.not_taken_delay = delay.as<uint64_t>();
+                            res.taken_delay = res.not_taken_delay;
+                        }
+                        delays.push_back(std::move(res));
+                    }
+                }
+                rep_counts.resize(delays.size());
+            } catch(YAML::ParserException& e) {
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
         }
     }
 }
 
 iss::plugin::instruction_count::~instruction_count() {
-	size_t idx=0;
+    size_t idx = 0;
-	for(auto it:delays){
+    for(auto it : delays) {
-		if(rep_counts[idx]>0)
+        if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0))
-			LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
+            CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx];
         idx++;
     }
 }
 
 bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
     auto instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
+    if(!instr_if)
-	const std::string  core_name = instr_if->core_type_name();
+        return false;
-    Json::Value &val = root[core_name];
-    if(!val.isNull() && val.isArray()){
-    	delays.reserve(val.size());
-    	for(auto it:val){
-    		auto name = it["name"];
-    		auto size = it["size"];
-    		auto delay = it["delay"];
-    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
-    		if(delay.isUInt()){
-				const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
-				delays.push_back(entry);
-    		} else {
-				const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
-				delays.push_back(entry);
-    		}
-    	}
-    	rep_counts.resize(delays.size());
-    } else {
-        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
-    }
     return true;
 }
 
-void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) { rep_counts[instr_info.instr_id]++; }
-	rep_counts[instr_info.instr_id]++;
-}

src/iss/plugin/instruction_count.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,8 +36,8 @@
 #define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
 
 #include <iss/vm_plugin.h>
-#include <json/json.h>
 #include <string>
+#include <vector>
 
 namespace iss {
 namespace plugin {
@@ -53,30 +53,29 @@ class instruction_count : public iss::vm_plugin {
 public:
     instruction_count() = delete;
 
-    instruction_count(const instruction_count &) = delete;
+    instruction_count(const instruction_count&) = delete;
 
-    instruction_count(const instruction_count &&) = delete;
+    instruction_count(const instruction_count&&) = delete;
 
     instruction_count(std::string config_file_name);
 
     virtual ~instruction_count();
 
-    instruction_count &operator=(const instruction_count &) = delete;
+    instruction_count& operator=(const instruction_count&) = delete;
 
-    instruction_count &operator=(const instruction_count &&) = delete;
+    instruction_count& operator=(const instruction_count&&) = delete;
 
-    bool registration(const char *const version, vm_if &arch) override;
+    bool registration(const char* const version, vm_if& arch) override;
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;
 
 private:
-    Json::Value root;
     std::vector<instr_delay> delays;
     std::vector<uint64_t> rep_counts;
 };
-}
+} // namespace plugin
-}
+} // namespace iss
 
 #endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */

src/iss/semihosting/semihosting.cpp

@@ -0,0 +1,297 @@
+#include "semihosting.h"
+#include <chrono>
+#include <cstdint>
+#include <iss/vm_types.h>
+#include <map>
+#include <stdexcept>
+// explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h
+
+const char* SYS_OPEN_MODES_STRS[] = {"r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b"};
+
+template <typename T> T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len = 4) {
+    uint8_t bytes[4];
+    auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]);
+    // auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+
+    if(res != iss::Ok) {
+        return 0; // TODO THROW ERROR
+    } else
+        return static_cast<T>(bytes[0]) | (static_cast<T>(bytes[1]) << 8) | (static_cast<T>(bytes[2]) << 16) |
+               (static_cast<T>(bytes[3]) << 24);
+}
+
+template <typename T> std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len) {
+    std::vector<uint8_t> buffer(str_len);
+    for(int i = 0; i < str_len; i++) {
+        buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1);
+    }
+    std::string str(buffer.begin(), buffer.end());
+    return str;
+}
+
+template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) {
+    static std::map<T, FILE*> openFiles;
+    static T file_count = 3;
+    static T semihostingErrno;
+
+    switch(static_cast<semihosting_syscalls>(*call_number)) {
+    case semihosting_syscalls::SYS_CLOCK: {
+        auto end = std::chrono::high_resolution_clock::now(); // end measurement
+        auto elapsed = end - timeVar;
+        auto millis = std::chrono::duration_cast<std::chrono::milliseconds>(elapsed).count();
+        *call_number = millis; // TODO get time now
+        break;
+    }
+    case semihosting_syscalls::SYS_CLOSE: {
+        T file_handle = *parameter;
+        if(openFiles.size() <= file_handle && file_handle < 0) {
+            semihostingErrno = EBADF;
+            return;
+        }
+        auto file = openFiles[file_handle];
+        openFiles.erase(file_handle);
+        if(!(file == stdin || file == stdout || file == stderr)) {
+            int i = fclose(file);
+            *call_number = i;
+        } else {
+            *call_number = -1;
+            semihostingErrno = EINTR;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_ELAPSED: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ERRNO: {
+        *call_number = semihostingErrno;
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT: {
+
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT");
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT_EXTENDED: {
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT_EXTENDED");
+        break;
+    }
+    case semihosting_syscalls::SYS_FLEN: {
+        T file_handle = *parameter;
+        auto file = openFiles[file_handle];
+
+        size_t currentPos = ftell(file);
+        if(currentPos < 0)
+            throw std::runtime_error("SYS_FLEN negative value");
+        fseek(file, 0, SEEK_END);
+        size_t length = ftell(file);
+        fseek(file, currentPos, SEEK_SET);
+        *call_number = (T)length;
+        break;
+    }
+    case semihosting_syscalls::SYS_GET_CMDLINE: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_HEAPINFO: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ISERROR: {
+        T value = *parameter;
+        *call_number = (value != 0);
+        break;
+    }
+    case semihosting_syscalls::SYS_ISTTY: {
+        T file_handle = *parameter;
+        *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2);
+        break;
+    }
+    case semihosting_syscalls::SYS_OPEN: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T mode = sh_read_field<T>(arch_if_ptr, 4 + (*parameter));
+        T path_len = sh_read_field<T>(arch_if_ptr, 8 + (*parameter));
+
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        // TODO LOG INFO
+
+        if(mode >= 12) {
+            // TODO throw ERROR
+            return;
+        }
+
+        FILE* file = nullptr;
+        if(path_str == ":tt") {
+            if(mode < 4)
+                file = stdin;
+            else if(mode < 8)
+                file = stdout;
+            else
+                file = stderr;
+        } else {
+            file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]);
+            if(file == nullptr) {
+                // TODO throw error
+                return;
+            }
+        }
+        T file_handle = file_count++;
+        openFiles[file_handle] = file;
+        *call_number = file_handle;
+        break;
+    }
+    case semihosting_syscalls::SYS_READ: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+
+        std::vector<uint8_t> buffer(count);
+        size_t num_read = 0;
+        if(file == stdin) {
+            // when reading from stdin: mimic behaviour from read syscall
+            // and return on newline.
+            while(num_read < count) {
+                char c = fgetc(file);
+                buffer[num_read] = c;
+                num_read++;
+                if(c == '\n')
+                    break;
+            }
+        } else {
+            num_read = fread(buffer.data(), 1, count, file);
+        }
+        buffer.resize(num_read);
+        for(int i = 0; i < num_read; i++) {
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr + i, 1, &buffer[i]);
+            if(res != iss::Ok)
+                return;
+        }
+        *call_number = count - num_read;
+        break;
+    }
+    case semihosting_syscalls::SYS_READC: {
+        uint8_t character = getchar();
+        // character = getchar();
+        /*if(character != iss::Ok)
+            std::cout << "Not OK";
+            return;*/
+        *call_number = character;
+        break;
+    }
+    case semihosting_syscalls::SYS_REMOVE: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        if(remove(path_str.c_str()) < 0)
+            *call_number = -1;
+        break;
+    }
+    case semihosting_syscalls::SYS_RENAME: {
+        T path_str_addr_old = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len_old = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T path_str_addr_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+        T path_len_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 12);
+
+        std::string path_str_old = sh_read_string<T>(arch_if_ptr, path_str_addr_old, path_len_old);
+        std::string path_str_new = sh_read_string<T>(arch_if_ptr, path_str_addr_new, path_len_new);
+        rename(path_str_old.c_str(), path_str_new.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_SEEK: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, *parameter);
+        T pos = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        auto file = openFiles[file_handle];
+
+        int retval = fseek(file, pos, SEEK_SET);
+        if(retval < 0)
+            throw std::runtime_error("SYS_SEEK negative return value");
+
+        break;
+    }
+    case semihosting_syscalls::SYS_SYSTEM: {
+        T cmd_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T cmd_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        std::string cmd = sh_read_string<T>(arch_if_ptr, cmd_addr, cmd_len);
+        system(cmd.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_TICKFREQ: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_TIME: {
+        // returns time in seconds scince 01.01.1970 00:00
+        *call_number = time(NULL);
+        break;
+    }
+    case semihosting_syscalls::SYS_TMPNAM: {
+        T buffer_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T identifier = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        T buffer_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 2);
+
+        if(identifier > 255) {
+            *call_number = -1;
+            return;
+        }
+        std::stringstream ss;
+        ss << "tmp/file-" << std::setfill('0') << std::setw(3) << identifier;
+        std::string filename = ss.str();
+
+        for(int i = 0; i < buffer_len; i++) {
+            uint8_t character = filename[i];
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i, 1, &character);
+            if(res != iss::Ok)
+                return;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+        std::string str = sh_read_string<T>(arch_if_ptr, addr, count);
+        fwrite(&str[0], 1, count, file);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITEC: {
+        uint8_t character;
+        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+        if(res != iss::Ok)
+            return;
+        putchar(character);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE0: {
+        uint8_t character;
+        while(1) {
+            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+            if(res != iss::Ok)
+                return;
+            if(character == 0)
+                break;
+            putchar(character);
+            (*parameter)++;
+        }
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x100: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x1FF: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    default:
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+}
+template class semihosting_callback<uint32_t>;
+template class semihosting_callback<uint64_t>;

src/iss/semihosting/semihosting.h

@@ -0,0 +1,61 @@
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+#include <chrono>
+#include <functional>
+#include <iss/arch_if.h>
+/*
+ * According to:
+ * "Semihosting for AArch32 and AArch64, Release 2.0"
+ * https://static.docs.arm.com/100863/0200/semihosting.pdf
+ * from ARM Ltd.
+ *
+ * The available semihosting operation numbers passed in A0 are allocated
+ * as follows:
+ * - 0x00-0x31 Used by ARM.
+ * - 0x32-0xFF Reserved for future use by ARM.
+ * - 0x100-0x1FF Reserved for user applications. These are not used by ARM.
+ *   However, if you are writing your own SVC operations, you are advised
+ *   to use a different SVC number rather than using the semihosted
+ *   SVC number and these operation type numbers.
+ * - 0x200-0xFFFFFFFF Undefined and currently unused. It is recommended
+ *   that you do not use these.
+ */
+enum class semihosting_syscalls {
+
+    SYS_OPEN = 0x01,
+    SYS_CLOSE = 0x02,
+    SYS_WRITEC = 0x03,
+    SYS_WRITE0 = 0x04,
+    SYS_WRITE = 0x05,
+    SYS_READ = 0x06,
+    SYS_READC = 0x07,
+    SYS_ISERROR = 0x08,
+    SYS_ISTTY = 0x09,
+    SYS_SEEK = 0x0A,
+    SYS_FLEN = 0x0C,
+    SYS_TMPNAM = 0x0D,
+    SYS_REMOVE = 0x0E,
+    SYS_RENAME = 0x0F,
+    SYS_CLOCK = 0x10,
+    SYS_TIME = 0x11,
+    SYS_SYSTEM = 0x12,
+    SYS_ERRNO = 0x13,
+    SYS_GET_CMDLINE = 0x15,
+    SYS_HEAPINFO = 0x16,
+    SYS_EXIT = 0x18,
+    SYS_EXIT_EXTENDED = 0x20,
+    SYS_ELAPSED = 0x30,
+    SYS_TICKFREQ = 0x31,
+    USER_CMD_0x100 = 0x100,
+    USER_CMD_0x1FF = 0x1FF,
+};
+
+template <typename T> struct semihosting_callback {
+    std::chrono::high_resolution_clock::time_point timeVar;
+    semihosting_callback()
+    : timeVar(std::chrono::high_resolution_clock::now()) {}
+    void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter);
+};
+
+template <typename T> using semihosting_cb_t = std::function<void(iss::arch_if*, T*, T*)>;
+#endif

src/main.cpp

@@ -30,27 +30,33 @@
  *
  *******************************************************************************/
 
+#include <array>
+#include <cstdint>
 #include <iostream>
 #include <iss/factory.h>
+#include <iss/semihosting/semihosting.h>
+#include <string>
+#include <unordered_map>
+#include <vector>
 
+#include "iss/arch/tgc_mapper.h"
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
-#include <iss/arch/tgc_mapper.h>
 #ifdef WITH_LLVM
-#include <iss/llvm/jit_helper.h>
+#include <iss/llvm/jit_init.h>
 #endif
+#include "iss/plugin/cycle_estimate.h"
+#include "iss/plugin/instruction_count.h"
 #include <iss/log_categories.h>
-#include <iss/plugin/cycle_estimate.h>
+#ifndef WIN32
-#include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>
 #include <iss/plugin/loader.h>
+#endif
 #if defined(HAS_LUA)
 #include <iss/plugin/lua.h>
 #endif
 
 namespace po = boost::program_options;
-
+int main(int argc, char* argv[]) {
-int main(int argc, char *argv[]) {
     /*
      *  Define and parse the program options
      */
@@ -59,7 +65,7 @@ int main(int argc, char *argv[]) {
     // clang-format off
     desc.add_options()
         ("help,h", "Print help message")
-        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
+        ("verbose,v", po::value<int>()->default_value(4), "Sets logging verbosity")
         ("logfile,l", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
@@ -69,19 +75,19 @@ int main(int argc, char *argv[]) {
         ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
+        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit")
-        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
+        ("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
     try {
         po::store(parsed, clim); // can throw
         // --help option
-        if (clim.count("help")) {
+        if(clim.count("help")) {
-            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
+            std::cout << "DBT-RISE-TGC simulator for TGC RISC-V cores" << std::endl << desc << std::endl;
             return 0;
         }
         po::notify(clim); // throws on error, so do after help in case
-    } catch (po::error &e) {
+    } catch(po::error& e) {
         // there are problems
         std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
         std::cerr << desc << std::endl;
@@ -91,19 +97,17 @@ int main(int argc, char *argv[]) {
 
     LOGGER(DEFAULT)::print_time() = false;
     LOGGER(connection)::print_time() = false;
-    if (clim.count("verbose")) {
     auto l = logging::as_log_level(clim["verbose"].as<int>());
     LOGGER(DEFAULT)::reporting_level() = l;
     LOGGER(connection)::reporting_level() = l;
-    }
+    if(clim.count("logfile")) {
-    if (clim.count("logfile")) {
         // configure the connection logger
         auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
         LOG_OUTPUT(DEFAULT)::stream() = f;
         LOG_OUTPUT(connection)::stream() = f;
     }
 
-    std::vector<iss::vm_plugin *> plugin_list;
+    std::vector<iss::vm_plugin*> plugin_list;
     auto res = 0;
     try {
 #ifdef WITH_LLVM
@@ -111,125 +115,145 @@ int main(int argc, char *argv[]) {
         iss::init_jit_debug(argc, argv);
 #endif
         bool dump = clim.count("dump-ir");
+        auto& f = iss::core_factory::instance();
         // instantiate the simulator
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
+        semihosting_callback<uint32_t> cb{};
+        semihosting_cb_t<uint32_t> semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) { cb(i, a0, a1); };
         std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgc_c") {
+        if(isa_opt.size() == 0 || isa_opt == "?") {
+            auto list = f.get_names();
+            std::sort(std::begin(list), std::end(list));
+            std::cout << "Available implementations (core|platform|backend):\n  - " << util::join(list, "\n  - ") << std::endl;
+            return 0;
+        } else if(isa_opt.find('|') != std::string::npos) {
             std::tie(cpu, vm) =
-                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+                f.create(isa_opt + "|" + clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>(), &semihosting_cb);
-        } else
+        } else {
-#ifdef CORE_TGC_B
+            auto base_isa = isa_opt.substr(0, 5);
-        if (isa_opt == "tgc_b") {
+            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
-            std::tie(cpu, vm) =
+                isa_opt += "|mu_p_clic_pmp|" + clim["backend"].as<std::string>();
-                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+            } else {
-        } else
+                isa_opt += "|m_p|" + clim["backend"].as<std::string>();
-#endif
+            }
-#ifdef CORE_TGC_C_XRB_NN
+            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
-        if (isa_opt == "tgc_c_xrb_nn") {
+        }
-            std::tie(cpu, vm) =
+        if(!cpu) {
-                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+            CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
-        } else
+            return 127;
-#endif
+        }
-#ifdef CORE_TGC_D
+        if(!vm) {
-        if (isa_opt == "tgc_d") {
+            CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
-            std::tie(cpu, vm) =
+            return 127;
-                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        }
-        } else
+        if(clim.count("plugin")) {
-#endif
+            for(std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
-#ifdef CORE_TGC_D_XRB_MAC
+                std::string plugin_name = opt_val;
-        if (isa_opt == "tgc_d_xrb_mac") {
+                std::string arg{""};
-            std::tie(cpu, vm) =
+                std::size_t found = opt_val.find('=');
-                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+                if(found != std::string::npos) {
-        } else
+                    plugin_name = opt_val.substr(0, found);
-#endif
+                    arg = opt_val.substr(found + 1, opt_val.size());
-#ifdef CORE_TGC_D_XRB_NN
+                }
-        if (isa_opt == "tgc_d_xrb_nn") {
+#if defined(WITH_PLUGINS)
-            std::tie(cpu, vm) =
+                if(plugin_name == "ic") {
-                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+                    auto* ic_plugin = new iss::plugin::instruction_count(arg);
-        } else
+                    vm->register_plugin(*ic_plugin);
-#endif
+                    plugin_list.push_back(ic_plugin);
-#ifdef CORE_TGC_E
+                } else if(plugin_name == "ce") {
-        if (isa_opt == "tgc_e") {
+                    auto* ce_plugin = new iss::plugin::cycle_estimate(arg);
-            std::tie(cpu, vm) =
+                    vm->register_plugin(*ce_plugin);
-                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+                    plugin_list.push_back(ce_plugin);
                 } else
 #endif
                 {
-            LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
+#if !defined(WIN32)
-            return 127;
+                    std::vector<char const*> a{};
-        }
+                    if(arg.length())
-        if (clim.count("plugin")) {
+                        a.push_back({arg.c_str()});
-            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
-                std::string plugin_name=opt_val;
-                std::string filename{"cycles.txt"};
-                std::size_t found = opt_val.find('=');
-                if (found != std::string::npos) {
-                    plugin_name = opt_val.substr(0, found);
-                    filename = opt_val.substr(found + 1, opt_val.size());
-                }
-                if (plugin_name == "ic") {
-                    auto *ic_plugin = new iss::plugin::instruction_count(filename);
-                    vm->register_plugin(*ic_plugin);
-                    plugin_list.push_back(ic_plugin);
-                } else if (plugin_name == "ce") {
-                    auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
-                    vm->register_plugin(*ce_plugin);
-                    plugin_list.push_back(ce_plugin);
-                } else if (plugin_name == "pctrace") {
-                    auto *plugin = new iss::plugin::cov(filename);
-                    vm->register_plugin(*plugin);
-                    plugin_list.push_back(plugin);
-               } else {
-                    std::array<char const*, 1> a{{filename.c_str()}};
                     iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                     auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
-                    if(plugin){
+                    if(plugin) {
                         vm->register_plugin(*plugin);
                         plugin_list.push_back(plugin);
-                    } else {
+                    } else
-                        LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+#endif
+                    {
+                        CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                         return 127;
                     }
                 }
             }
         }
-        if (clim.count("disass")) {
+        if(clim.count("disass")) {
             vm->setDisassEnabled(true);
             LOGGER(disass)::reporting_level() = logging::INFO;
             LOGGER(disass)::print_time() = false;
             auto file_name = clim["disass"].as<std::string>();
-            if (file_name.length() > 0) {
+            if(file_name.length() > 0) {
                 LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
                 LOGGER(disass)::print_severity() = false;
             }
         }
         uint64_t start_address = 0;
-        if (clim.count("mem"))
+        if(clim.count("mem"))
             vm->get_arch()->load_file(clim["mem"].as<std::string>());
-        if (clim.count("elf"))
+        if(clim.count("elf"))
-            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
+            for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if (start_addr.second) start_address = start_addr.first;
+                if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                    start_address = start_addr.first;
             }
-        for (std::string input : args) {
+        for(std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if (start_addr.second) start_address = start_addr.first;
+            if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                start_address = start_addr.first;
         }
-        if (clim.count("reset")) {
+        if(clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();
             start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
         }
         vm->reset(start_address);
         auto cycles = clim["instructions"].as<uint64_t>();
         res = vm->start(cycles, dump);
-    } catch (std::exception &e) {
+
-        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+        auto instr_if = vm->get_arch()->get_instrumentation_if();
-                   << std::endl;
+        // this assumes a single input file
+        std::unordered_map<std::string, uint64_t> sym_table;
+        if(args.empty())
+            sym_table = instr_if->get_symbol_table(clim["elf"].as<std::vector<std::string>>()[0]);
+        else
+            sym_table = instr_if->get_symbol_table(args[0]);
+        if(sym_table.find("begin_signature") != std::end(sym_table) && sym_table.find("end_signature") != std::end(sym_table)) {
+            auto start_addr = sym_table["begin_signature"];
+            auto end_addr = sym_table["end_signature"];
+            std::array<uint8_t, 4> data;
+            std::ofstream file;
+            std::string filename = fmt::format("{}.signature", isa_opt);
+            std::replace(std::begin(filename), std::end(filename), '|', '_');
+            // default riscof requires this filename
+            filename = "DUT-tgc.signature";
+            file.open(filename, std::ios::out);
+            if(!file.is_open()) {
+                LOG(ERR) << "Error opening file " << filename << std::endl;
+                return 1;
+            }
+            for(auto addr = start_addr; addr < end_addr; addr += data.size()) {
+                vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(),
+                                     data.data()); // FIXME: get space from iss::arch::traits<ARCH>::mem_type_e::MEM
+
+                // TODO : obey Target endianess
+                uint32_t to_print = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
+                file << std::hex << fmt::format("{:08x}", to_print) << std::dec << std::endl;
+            }
+        }
+    } catch(std::exception& e) {
+        CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
         res = 2;
     }
-    // cleanup to let plugins report of needed
+    // cleanup to let plugins report if needed
-    for (auto *p : plugin_list) {
+    for(auto* p : plugin_list) {
         delete p;
     }
     return res;

src/plugin/cycle_estimate.cpp

@@ -1,118 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
-
-#include "iss/plugin/cycle_estimate.h"
-
-#include <iss/arch_if.h>
-#include <util/logging.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
-#include <fstream>
-
-using namespace rapidjson;
-using namespace std;
-
-iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
-: instr_if(nullptr)
-, config_file_name(config_file_name)
-{
-}
-
-iss::plugin::cycle_estimate::~cycle_estimate() {
-}
-
-bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
-    instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-    const string  core_name = instr_if->core_type_name();
-    if (config_file_name.length() > 0) {
-        ifstream is(config_file_name);
-        if (is.is_open()) {
-            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
-                       }
-                    } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
-                   }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
-               }
-            } catch (runtime_error &e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
-                return false;
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
-            return false;
-        }
-    }
-    return true;
-
-}
-
-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
-    assert(instr_if && "No instrumentation interface available but callback executed");
-    auto entry = delays[instr_info.instr_id];
-    bool taken = exc_info.branch_taken;
-    if (exc_info.branch_taken && (entry.taken > 1))
-        instr_if->set_curr_instr_cycles(entry.taken);
-    else if (entry.not_taken > 1)
-        instr_if->set_curr_instr_cycles(entry.not_taken);
-}

src/plugin/pctrace.cpp

@@ -1,180 +0,0 @@
-#include <iss/arch_if.h>
-#include <iss/plugin/pctrace.h>
-#include <util/logging.h>
-#include <util/ities.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
-#include <fstream>
-#include <iostream>
-#ifdef WITH_LZ4
-#include <lz4frame.h>
-#endif
-
-namespace iss {
-namespace plugin {
-
-using namespace rapidjson;
-using namespace std;
-
-#ifdef WITH_LZ4
-class lz4compress_steambuf: public std::streambuf {
-public:
-    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
-    : sink(sink)
-    , src_buf(buf_size)
-    , dest_buf(LZ4F_compressBound(buf_size, nullptr))
-    {
-        auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
-        if (LZ4F_isError(errCode) != 0)
-            throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
-        size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
-        setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
-        sink.write(dest_buf.data(), ret);
-    }
-
-    ~lz4compress_steambuf() {
-        close();
-    }
-
-    void close() {
-        if (closed)
-            return;
-        sync();
-        auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
-        sink.write(dest_buf.data(), ret);
-        LZ4F_freeCompressionContext(ctx);
-        closed = true;
-    }
-
-private:
-    int_type overflow(int_type ch) override {
-        compress_and_write();
-        *pptr() = static_cast<char_type>(ch);
-        pbump(1);
-        return ch;
-    }
-
-    int_type sync() override {
-        compress_and_write();
-        return 0;
-    }
-
-    void compress_and_write() {
-        if (closed)
-            throw std::runtime_error("Cannot write to closed stream");
-        if(auto orig_size = pptr() - pbase()){
-            auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
-            if (LZ4F_isError(ret) != 0)
-                throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
-            if(ret) sink.write(dest_buf.data(), ret);
-            pbump(-orig_size);
-        }
-    }
-
-    std::ostream &sink;
-    std::vector<char> src_buf;
-    std::vector<char> dest_buf;
-    LZ4F_compressionContext_t ctx{ nullptr };
-    bool closed{ false };
-};
-#endif
-
-cov::cov(std::string const &filename)
-: instr_if(nullptr)
-, filename(filename)
-, output("output.trc")
-#ifdef WITH_LZ4
-, strbuf(new lz4compress_steambuf(output, 4096))
-, ostr(strbuf.get())
-#endif
-{ }
-
-cov::~cov() { }
-
-bool cov::registration(const char *const version, vm_if& vm) {
-    instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-    const string  core_name = instr_if->core_type_name();
-    if (filename.length() > 0) {
-        ifstream is(filename);
-        if (is.is_open()) {
-            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
-
-                        }
-                    } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
-                    }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
-                }
-            } catch (runtime_error &e) {
-                LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
-                return false;
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << filename;
-            return false;
-        }
-    }
-    return true;
-}
-
-void cov::callback(instr_info_t iinfo, const exec_info& einfo) {
-    auto delay = 0;
-    size_t id = iinfo.instr_id;
-    auto entry = delays[id];
-    auto instr = instr_if->get_instr_word();
-    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
-    bool taken = einfo.branch_taken;
-    bool compressed = (instr&0x3)!=0x3;
-    if (einfo.branch_taken) {
-        delay = entry.taken;
-        if(entry.taken > 1)
-            instr_if->set_curr_instr_cycles(entry.taken);
-    } else {
-        delay = entry.not_taken;
-        if (entry.not_taken > 1)
-            instr_if->set_curr_instr_cycles(entry.not_taken);
-    }
-#ifndef WITH_LZ4
-    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#else
-    auto rdbuf=ostr.rdbuf();
-    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#endif
-}
-}
-}

src/sysc/core_complex.cpp

@@ -37,23 +37,28 @@
 #include <iss/debugger/target_adapter_if.h>
 #include <iss/iss.h>
 #include <iss/vm_types.h>
+#include "iss_factory.h"
+#ifndef WIN32
 #include <iss/plugin/loader.h>
-#include <sysc/core_complex.h>
+#endif
+#include "sc_core_adapter_if.h"
 #include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
 #include <sstream>
 #include <array>
+#include <numeric>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>
 
 // clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN)                                                                                                                    \
-if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
+    if(type == STR(CN)) {                                                                                                                  \
+        std::tie(cpu, vm) = create_core<CN##_plat_type>(backend, gdb_port, hart_id);                                                       \
+    } else
 
 #ifdef HAS_SCV
 #include <scv.h>
@@ -83,150 +88,23 @@ using namespace sc_core;
 
 namespace {
 iss::debugger::encoder_decoder encdec;
-
 std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-}
+} // namespace
 
-template<typename PLAT>
+int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter) {
-class core_wrapper_t : public PLAT {
+    if(argc > 1) {
-public:
+        if(strcasecmp(argv[1], "print_time") == 0) {
-    using reg_t       = typename arch::traits<typename PLAT::core>::reg_t;
-    using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
-    using heart_state_t = typename PLAT::hart_state_type;
-    core_wrapper_t(core_complex *owner)
-    : owner(owner) { }
-
-    uint32_t get_mode() { return this->reg.PRIV; }
-
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
-
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
-
-    heart_state_t &get_state() { return this->state; }
-
-    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART) owner->sync(this->icount);
-    }
-
-    sync_type needed_sync() const override { return PRE_SYNC; }
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        if (!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
-              << this->icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->name())<<"disass: "
-                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
-                << std::setfill(' ') << std::left << instr << s.str();
-        }
-    };
-
-    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
-        }
-    }
-
-    status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
-            // clear MTIP on mtimecmp write
-            if (addr.val == 0x2004000) {
-                reg_t val;
-                this->read_csr(arch::mip, val);
-                if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
-            }
-            return res;
-        }
-    }
-
-    status read_csr(unsigned addr, reg_t &val) override {
-#ifndef CWR_SYSTEMC
-        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret?Ok:Err;
-#else
-		if((addr==arch::time || addr==arch::timeh)){
-			uint64_t time_val = owner->mtime_i.read();
-			if (addr == iss::arch::time) {
-				val = static_cast<reg_t>(time_val);
-			} else if (addr == iss::arch::timeh) {
-				if (sizeof(reg_t) != 4) return iss::Err;
-				val = static_cast<reg_t>(time_val >> 32);
-			}
-			return Ok;
-#endif
-        } else {
-            return PLAT::read_csr(addr, val);
-        }
-    }
-
-    void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
-        }
-        PLAT::wait_until(flags);
-    }
-
-    void local_irq(short id, bool value) {
-        reg_t mask = 0;
-        switch (id) {
-        case 16: // SW
-            mask = 1 << 3;
-            break;
-        case 17: // timer
-            mask = 1 << 7;
-            break;
-        case 18: // external
-            mask = 1 << 11;
-            break;
-        default:
-            /* do nothing*/
-            break;
-        }
-        if (value) {
-            this->csr[arch::mip] |= mask;
-            wfi_evt.notify();
-        } else
-            this->csr[arch::mip] &= ~mask;
-        this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->pending_trap;
-    }
-
-private:
-    core_complex *const owner;
-    sc_event wfi_evt;
-};
-
-int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
-             debugger::target_adapter_if *tgt_adapter) {
-    if (argc > 1) {
-        if (strcasecmp(argv[1], "print_time") == 0) {
             std::string t = sc_time_stamp().to_string();
             of(t.c_str());
             std::array<char, 64> buf;
             encdec.enc_string(t.c_str(), buf.data(), 63);
             df(buf.data());
             return Ok;
-        } else if (strcasecmp(argv[1], "break") == 0) {
+        } else if(strcasecmp(argv[1], "break") == 0) {
             sc_time t;
-            if (argc == 4) {
+            if(argc == 4) {
                 t = scc::parse_from_string(argv[2], argv[3]);
-            } else if (argc == 3) {
+            } else if(argc == 3) {
                 t = scc::parse_from_string(argv[2]);
             } else
                 return Err;
@@ -243,15 +121,19 @@ int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func
 }
 
 using cpu_ptr = std::unique_ptr<iss::arch_if>;
-using vm_ptr= std::unique_ptr<iss::vm_if>;
+using vm_ptr = std::unique_ptr<iss::vm_if>;
 
 class core_wrapper {
 public:
-    core_wrapper(core_complex *owner) : owner(owner) { }
+    core_wrapper(core_complex* owner)
+    : owner(owner) {}
 
-    void reset(uint64_t addr){vm->reset(addr);}
+    void reset(uint64_t addr) { vm->reset(addr); }
-    inline void start(){vm->start();}
+    inline void start(bool dump = false) { vm->start(std::numeric_limits<uint64_t>::max(), dump); }
-    inline std::pair<uint64_t, bool> load_file(std::string const& name){ return cpu->load_file(name);};
+    inline std::pair<uint64_t, bool> load_file(std::string const& name) {
+        iss::arch_if* cc = cpu->get_arch_if();
+        return cc->load_file(name);
+    };
 
     std::function<unsigned(void)> get_mode;
     std::function<uint64_t(void)> get_state;
@@ -259,91 +141,88 @@ public:
     std::function<void(bool)> set_interrupt_execution;
     std::function<void(short, bool)> local_irq;
 
-    template<typename PLAT>
+    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
-    std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
+        auto& f = sysc::iss_factory::instance();
-        auto* lcpu = new core_wrapper_t<PLAT>(owner);
+        if(type.size() == 0 || type == "?") {
-        lcpu->set_mhartid(hart_id);
+            std::cout << "Available cores: " << util::join(f.get_names(), ", ") << std::endl;
-        get_mode = [lcpu]() { return lcpu->get_mode(); };
+            sc_core::sc_stop();
-        get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
+        } else if(type.find('|') != std::string::npos) {
-        get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
+            std::tie(cpu, vm) = f.create(type + "|" + backend);
-        set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
+        } else {
-        local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
+            auto base_isa = type.substr(0, 5);
-        if(backend == "interp")
+            if(base_isa == "tgc5d" || base_isa == "tgc5e") {
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
+                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
-#ifdef WITH_LLVM
+            } else {
-        if(backend == "llvm")
+                std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
-            return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-#ifdef WITH_TCC
-        if(backend == "tcc")
-    s        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-#endif
-        return {nullptr, nullptr};
             }
+        }
+        if(!cpu) {
+            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend;
+        }
+        if(!vm) {
+            SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend;
+        }
+        auto* sc_cpu_if = reinterpret_cast<sc_core_adapter_if*>(cpu.get());
+        sc_cpu_if->set_mhartid(hart_id);
+        get_mode = [sc_cpu_if]() { return sc_cpu_if->get_mode(); };
+        get_state = [sc_cpu_if]() { return sc_cpu_if->get_state(); };
+        get_interrupt_execution = [sc_cpu_if]() { return sc_cpu_if->get_interrupt_execution(); };
+        set_interrupt_execution = [sc_cpu_if](bool b) { return sc_cpu_if->set_interrupt_execution(b); };
+        local_irq = [sc_cpu_if](short s, bool b) { return sc_cpu_if->local_irq(s, b); };
 
-    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
+        auto* srv = debugger::server<debugger::gdb_session>::get();
-        CREATE_CORE(tgc_c)
+        if(srv)
-#ifdef CORE_TGC_B
+            tgt_adapter = srv->get_target();
-        CREATE_CORE(tgc_b)
+        if(tgt_adapter)
-#endif
+            tgt_adapter->add_custom_command({"sysc",
-#ifdef CORE_TGC_D
+                                             [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int {
-        CREATE_CORE(tgc_d)
+                                                 return cmd_sysc(argc, argv, of, df, tgt_adapter);
-#endif
+                                             },
-#ifdef CORE_TGC_D_XRB_MAC
-        CREATE_CORE(tgc_d_xrb_mac)
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-        CREATE_CORE(tgc_d_xrb_nn)
-#endif
-        {
-            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
-        }
-        auto *srv = debugger::server<debugger::gdb_session>::get();
-        if (srv) tgt_adapter = srv->get_target();
-        if (tgt_adapter)
-            tgt_adapter->add_custom_command(
-                {"sysc", [this](int argc, char *argv[], debugger::out_func of,
-                                debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
                                              "SystemC sub-commands: break <time>, print_time"});
-
     }
 
-    core_complex * const owner;
+    core_complex* const owner;
     vm_ptr vm{nullptr};
-    cpu_ptr cpu{nullptr};
+    sc_cpu_ptr cpu{nullptr};
-    iss::debugger::target_adapter_if *tgt_adapter{nullptr};
+    iss::debugger::target_adapter_if* tgt_adapter{nullptr};
 };
 
 struct core_trace {
     //! transaction recording database
-    scv_tr_db *m_db{nullptr};
+    scv_tr_db* m_db{nullptr};
     //! blocking transaction recording stream handle
-    scv_tr_stream *stream_handle{nullptr};
+    scv_tr_stream* stream_handle{nullptr};
     //! transaction generator handle for blocking transactions
-    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle{nullptr};
+    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
     scv_tr_handle tr_handle;
 };
 
-SC_HAS_PROCESS(core_complex);// NOLINT
+SC_HAS_PROCESS(core_complex); // NOLINT
 #ifndef CWR_SYSTEMC
 core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
+, fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
-, write_lut(tlm_dmi_ext())
+, write_lut(tlm_dmi_ext()) {
-{
     init();
 }
 #endif
 
-void core_complex::init(){
+void core_complex::init() {
-	trc=new core_trace();
+    trc = new core_trace();
-    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+    ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+        auto lut_entry = fetch_lut.getEntry(start);
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            fetch_lut.removeEntry(lut_entry);
+        }
+    });
+    dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = read_lut.getEntry(start);
-        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
             read_lut.removeEntry(lut_entry);
         }
         lut_entry = write_lut.getEntry(start);
-        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
             write_lut.removeEntry(lut_entry);
         }
     });
@@ -355,91 +234,91 @@ void core_complex::init(){
     sensitive << sw_irq_i;
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
-    SC_METHOD(global_irq_cb);
+    SC_METHOD(ext_irq_cb);
-    sensitive << global_irq_i;
+    sensitive << ext_irq_i;
-    trc->m_db=scv_tr_db::get_default_db();
+    SC_METHOD(local_irq_cb);
+    for(auto pin : local_irq_i)
+        sensitive << pin;
+    trc->m_db = scv_tr_db::get_default_db();
 
     SC_METHOD(forward);
 #ifndef CWR_SYSTEMC
-	sensitive<<clk_i;
+    sensitive << clk_i;
 #else
-	sensitive<<curr_clk;
+    sensitive << curr_clk;
     t2t.reset(new scc::tick2time{"t2t"});
     t2t->clk_i(clk_i);
     t2t->clk_o(curr_clk);
 #endif
 }
 
-core_complex::~core_complex(){
+core_complex::~core_complex() {
     delete cpu;
     delete trc;
-    for (auto *p : plugin_list)
+    for(auto* p : plugin_list)
         delete p;
 }
 
-void core_complex::trace(sc_trace_file *trf) const {}
+void core_complex::trace(sc_trace_file* trf) const {}
 
 void core_complex::before_end_of_elaboration() {
-    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
+    SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
     // cpu = scc::make_unique<core_wrapper>(this);
     cpu = new core_wrapper(this);
     cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
-    sc_assert(cpu->vm!=nullptr);
+    sc_assert(cpu->vm != nullptr);
     cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
-    if (GET_PROP_VALUE(plugins).length()) {
+    if(GET_PROP_VALUE(plugins).length()) {
         auto p = util::split(GET_PROP_VALUE(plugins), ';');
-        for (std::string const& opt_val : p) {
+        for(std::string const& opt_val : p) {
-            std::string plugin_name=opt_val;
+            std::string plugin_name = opt_val;
             std::string filename{"cycles.txt"};
             std::size_t found = opt_val.find('=');
-            if (found != std::string::npos) {
+            if(found != std::string::npos) {
                 plugin_name = opt_val.substr(0, found);
                 filename = opt_val.substr(found + 1, opt_val.size());
             }
-            if (plugin_name == "ic") {
+            if(plugin_name == "ic") {
-                auto *plugin = new iss::plugin::instruction_count(filename);
+                auto* plugin = new iss::plugin::instruction_count(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
-            } else if (plugin_name == "ce") {
+            } else if(plugin_name == "ce") {
-                auto *plugin = new iss::plugin::cycle_estimate(filename);
+                auto* plugin = new iss::plugin::cycle_estimate(filename);
-                cpu->vm->register_plugin(*plugin);
-                plugin_list.push_back(plugin);
-            } else if (plugin_name == "pctrace") {
-                auto *plugin = new iss::plugin::cov(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
             } else {
+#ifndef WIN32
                 std::array<char const*, 1> a{{filename.c_str()}};
                 iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                 auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
-                if(plugin){
+                if(plugin) {
                     cpu->vm->register_plugin(*plugin);
                     plugin_list.push_back(plugin);
                 } else
+#endif
                     SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
             }
         }
     }
-
 }
 
 void core_complex::start_of_simulation() {
-    quantum_keeper.reset();
+    // quantum_keeper.reset();
-    if (GET_PROP_VALUE(elf_file).size() > 0) {
+    if(GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
         string s;
-        while (getline(is, s, ',')) {
+        while(getline(is, s, ',')) {
             std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
 #ifndef CWR_SYSTEMC
-            if (reset_address.is_default_value() && start_addr.second == true)
+            if(reset_address.is_default_value() && start_addr.second == true)
                 reset_address.set_value(start_addr.first);
 #else
-            if (start_addr.second == true)
+            if(start_addr.second == true)
-                reset_address=start_addr.first;
+                reset_address = start_addr.first;
 #endif
         }
     }
-    if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
+    if(trc->m_db != nullptr && trc->stream_handle == nullptr) {
         string basename(this->name());
         trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);
         trc->instr_tr_handle = new scv_tr_generator<>("execute", *trc->stream_handle);
@@ -447,8 +326,10 @@ void core_complex::start_of_simulation() {
 }
 
 bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-    if (trc->m_db == nullptr) return false;
+    if(trc->m_db == nullptr)
-    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
+        return false;
+    if(trc->tr_handle.is_active())
+        trc->tr_handle.end_transaction();
     trc->tr_handle = trc->instr_tr_handle->begin_transaction();
     trc->tr_handle.record_attribute("PC", pc);
     trc->tr_handle.record_attribute("INSTR", instr_str);
@@ -469,87 +350,111 @@ void core_complex::forward() {
 
 void core_complex::set_clock_period(sc_core::sc_time period) {
     curr_clk = period;
-    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
+    if(period == SC_ZERO_TIME)
+        cpu->set_interrupt_execution(true);
 }
 
 void core_complex::rst_cb() {
-    if (rst_i.read()) cpu->set_interrupt_execution(true);
+    if(rst_i.read())
+        cpu->set_interrupt_execution(true);
 }
 
-void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
+void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
 
-void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
+void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
 
-void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
+void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+
+void core_complex::local_irq_cb() {
+    for(auto i = 0U; i < local_irq_i.size(); ++i) {
+        if(local_irq_i[i].event()) {
+            cpu->local_irq(16 + i, local_irq_i[i].read());
+        }
+    }
+}
 
 void core_complex::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
-        if (rst_i.read()) {
+        wait(SC_ZERO_TIME);
+        if(rst_i.read()) {
             cpu->reset(GET_PROP_VALUE(reset_address));
             wait(rst_i.negedge_event());
         }
-        while (curr_clk.read() == SC_ZERO_TIME) {
+        while(curr_clk.read() == SC_ZERO_TIME) {
             wait(curr_clk.value_changed_event());
         }
+        quantum_keeper.reset();
         cpu->set_interrupt_execution(false);
-        cpu->start();
+        cpu->start(dump_ir);
-    } while (cpu->get_interrupt_execution());
+    } while(cpu->get_interrupt_execution());
     sc_stop();
 }
 
-bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
+bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
-    auto lut_entry = read_lut.getEntry(addr);
+    auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
+    auto lut_entry = dmi_lut.getEntry(addr);
-        addr + length <= lut_entry.get_end_address() + 1) {
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        if(is_fetch)
+            ibus_inc += lut_entry.get_read_latency() / curr_clk;
+        else
+            dbus_inc += lut_entry.get_read_latency() / curr_clk;
         return true;
     } else {
+        auto& sckt = is_fetch ? ibus : dbus;
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_READ_COMMAND);
         gp.set_address(addr);
         gp.set_data_ptr(data);
         gp.set_data_length(length);
         gp.set_streaming_width(length);
-        sc_time delay=quantum_keeper.get_local_time();
+        sc_time delay = quantum_keeper.get_local_time();
-        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+        if(trc->m_db != nullptr && trc->tr_handle.is_valid()) {
-            if (is_fetch && trc->tr_handle.is_active()) {
+            if(is_fetch && trc->tr_handle.is_active()) {
                 trc->tr_handle.end_transaction();
             }
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        initiator->b_transport(gp, delay);
+        auto pre_delay = delay;
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
+        dbus->b_transport(gp, delay);
-        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+        if(pre_delay > delay) {
+            quantum_keeper.reset();
+        } else {
+            auto incr = (delay - quantum_keeper.get_local_time()) / curr_clk;
+            if(is_fetch)
+                ibus_inc += incr;
+            else
+                dbus_inc += incr;
+        }
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if (gp.is_dmi_allowed()) {
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
+            if(sckt->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
+                if(dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
     }
 }
 
-bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *const data) {
+bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
-        addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        dbus_inc += lut_entry.get_write_latency() / curr_clk;
         return true;
     } else {
         write_buf.resize(length);
@@ -560,26 +465,30 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         gp.set_data_ptr(write_buf.data());
         gp.set_data_length(length);
         gp.set_streaming_width(length);
-        sc_time delay=quantum_keeper.get_local_time();
+        sc_time delay = quantum_keeper.get_local_time();
-        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+        if(trc->m_db != nullptr && trc->tr_handle.is_valid()) {
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        initiator->b_transport(gp, delay);
+        auto pre_delay = delay;
-        quantum_keeper.set(delay);
+        dbus->b_transport(gp, delay);
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
+        if(pre_delay > delay)
-        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+            quantum_keeper.reset();
+        else
+            dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
+        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
+                   << (length == 4   ? *(uint32_t*)data
+                       : length == 2 ? *(uint16_t*)data
+                                     : (unsigned)*data);
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
-        if (gp.is_dmi_allowed()) {
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
+            if(dbus->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
+                if(dmi_data.is_write_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
@@ -588,34 +497,17 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
     }
 }
 
-bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
+bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
     gp.set_data_ptr(data);
     gp.set_data_length(length);
     gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
+    return dbus->transport_dbg(gp) == length;
-    }
 }
 
-bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
+bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
@@ -624,8 +516,7 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
     gp.set_data_ptr(write_buf.data());
     gp.set_data_length(length);
     gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
+    return dbus->transport_dbg(gp) == length;
-    }
 }
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */

src/sysc/core_complex.h

@@ -33,34 +33,36 @@
 #ifndef _SYSC_CORE_COMPLEX_H_
 #define _SYSC_CORE_COMPLEX_H_
 
-#include <tlm/scc/initiator_mixin.h>
-#include <scc/traceable.h>
 #include <scc/tick2time.h>
+#include <scc/traceable.h>
 #include <scc/utilities.h>
+#include <tlm/scc/initiator_mixin.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
+#define SOCKET_WIDTH 32
 #else
 #include <cci_configuration>
+#define SOCKET_WIDTH scc::LT
 #endif
+#include <memory>
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
-#include <memory>
 
 namespace iss {
-    class vm_plugin;
+class vm_plugin;
 }
 namespace sysc {
 
 class tlm_dmi_ext : public tlm::tlm_dmi {
 public:
-    bool operator==(const tlm_dmi_ext &o) const {
+    bool operator==(const tlm_dmi_ext& o) const {
-        return this->get_granted_access() == o.get_granted_access() &&
+        return this->get_granted_access() == o.get_granted_access() && this->get_start_address() == o.get_start_address() &&
-               this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
+               this->get_end_address() == o.get_end_address();
     }
 
-    bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
+    bool operator!=(const tlm_dmi_ext& o) const { return !operator==(o); }
 };
 
 namespace tgfs {
@@ -69,11 +71,13 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
+
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
+    sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};
 
     sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
 
@@ -84,15 +88,17 @@ public:
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 
     cci::cci_param<bool> enable_disass{"enable_disass", false};
 
+    cci::cci_param<bool> disable_dmi{"disable_dmi", false};
+
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
 
     cci::cci_param<std::string> backend{"backend", "interp"};
 
@@ -115,9 +121,11 @@ public:
 
     scml_property<bool> enable_disass{"enable_disass", false};
 
+    scml_property<bool> disable_dmi{"disable_dmi", false};
+
     scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
 
-    scml_property<std::string> core_type{"core_type", "tgc_c"};
+    scml_property<std::string> core_type{"core_type", "tgc5c"};
 
     scml_property<std::string> backend{"backend", "interp"};
 
@@ -135,14 +143,15 @@ public:
     , elf_file{"elf_file", ""}
     , enable_disass{"enable_disass", false}
     , reset_address{"reset_address", 0ULL}
-    , core_type{"core_type", "tgc_c"}
+    , core_type{"core_type", "tgc5c"}
     , backend{"backend", "interp"}
     , gdb_server_port{"gdb_server_port", 0}
     , dump_ir{"dump_ir", false}
     , mhartid{"mhartid", 0}
+    , plugins{"plugins", ""}
+    , fetch_lut(tlm_dmi_ext())
     , read_lut(tlm_dmi_ext())
-    , write_lut(tlm_dmi_ext())
+    , write_lut(tlm_dmi_ext()) {
-    {
         init();
     }
 
@@ -150,29 +159,36 @@ public:
 
     ~core_complex();
 
+    inline unsigned get_last_bus_cycles() {
+        auto mem_incr = std::max(ibus_inc, dbus_inc);
+        ibus_inc = dbus_inc = 0;
+        return mem_incr > 1 ? mem_incr : 1;
+    }
+
     inline void sync(uint64_t cycle) {
-        auto time = curr_clk * (cycle - last_sync_cycle);
+        auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(time);
+        quantum_keeper.inc(core_inc);
-        if (quantum_keeper.need_sync()) {
+        if(quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
         last_sync_cycle = cycle;
     }
 
-    bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
+    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch);
 
-    bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
+    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data);
 
-    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
+    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data);
 
-    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
+    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data);
 
-    void trace(sc_core::sc_trace_file *trf) const override;
+    void trace(sc_core::sc_trace_file* trf) const override;
 
     bool disass_output(uint64_t pc, const std::string instr);
 
     void set_clock_period(sc_core::sc_time period);
+
 protected:
     void before_end_of_elaboration() override;
     void start_of_simulation() override;
@@ -181,21 +197,23 @@ protected:
     void rst_cb();
     void sw_irq_cb();
     void timer_irq_cb();
-    void global_irq_cb();
+    void ext_irq_cb();
+    void local_irq_cb();
     uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
+    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    uint64_t ibus_inc{0}, dbus_inc{0};
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
+
 private:
     void init();
-    std::vector<iss::vm_plugin *> plugin_list;
+    std::vector<iss::vm_plugin*> plugin_list;
-
 };
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */
 
 #endif /* _SYSC_CORE_COMPLEX_H_ */

src/sysc/iss_factory.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,75 +28,63 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- * Contributors:
+ *******************************************************************************/
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
 
-#ifndef _ISS_PLUGIN_COV_H_
+#ifndef _ISS_FACTORY_H_
-#define _ISS_PLUGIN_COV_H_
+#define _ISS_FACTORY_H_
 
-#include <iss/vm_plugin.h>
+#include "sc_core_adapter_if.h"
-#include "iss/instrumentation_if.h"
+#include <algorithm>
-#include <json/json.h>
+#include <functional>
+#include <iss/iss.h>
+#include <memory>
 #include <string>
-#include <fstream>
+#include <unordered_map>
+#include <vector>
 
+namespace sysc {
 
-namespace iss {
+using sc_cpu_ptr = std::unique_ptr<sc_core_adapter_if>;
-namespace plugin {
+using vm_ptr = std::unique_ptr<iss::vm_if>;
-class lz4compress_steambuf;
-class cov : public iss::vm_plugin {
-    struct instr_delay {
-        std::string instr_name;
-        size_t size;
-        size_t not_taken_delay;
-        size_t taken_delay;
-    };
-    BEGIN_BF_DECL(instr_desc, uint32_t)
-        BF_FIELD(taken, 24, 8)
-        BF_FIELD(not_taken, 16, 8)
-        BF_FIELD(is_branch, 8, 8)
-        BF_FIELD(size, 0, 8)
-        instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
-            this->size=size;
-            this->taken=taken;
-            this->not_taken=not_taken;
-            this->is_branch=branch;
-        }
-    END_BF_DECL();
 
+class iss_factory {
 public:
+    using base_t = std::tuple<sc_cpu_ptr, vm_ptr>;
+    using create_fn = std::function<base_t(unsigned, void*)>;
+    using registry_t = std::unordered_map<std::string, create_fn>;
 
-    cov(const cov &) = delete;
+    iss_factory() = default;
+    iss_factory(const iss_factory&) = delete;
+    iss_factory& operator=(const iss_factory&) = delete;
 
-    cov(const cov &&) = delete;
+    static iss_factory& instance() {
+        static iss_factory bf;
+        return bf;
+    }
 
-    cov(std::string const &);
+    bool register_creator(const std::string& className, create_fn const& fn) {
+        registry[className] = fn;
+        return true;
+    }
 
-    virtual ~cov();
+    base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const {
+        registry_t::const_iterator regEntry = registry.find(className);
+        if(regEntry != registry.end())
+            return regEntry->second(gdb_port, init_data);
+        return {nullptr, nullptr};
+    }
 
-    cov &operator=(const cov &) = delete;
+    std::vector<std::string> get_names() {
-
+        std::vector<std::string> keys{registry.size()};
-    cov &operator=(const cov &&) = delete;
+        std::transform(std::begin(registry), std::end(registry), std::begin(keys),
-
+                       [](std::pair<std::string, create_fn> const& p) { return p.first; });
-    bool registration(const char *const version, vm_if &arch) override;
+        return keys;
-
+    }
-    sync_type get_sync() override { return POST_SYNC; };
-
-    void callback(instr_info_t, exec_info const&) override;
 
 private:
-    iss::instrumentation_if *instr_if  {nullptr};
+    registry_t registry;
-    std::ofstream output;
-#ifdef WITH_LZ4
-    std::unique_ptr<lz4compress_steambuf> strbuf;
-    std::ostream ostr;
-#endif
-    std::string filename;
-    std::vector<instr_desc> delays;
-    bool jumped{false}, first{true};
 };
-}
-}
 
-#endif /* _ISS_PLUGIN_COV_H_ */
+} // namespace sysc
+
+#endif /* _ISS_FACTORY_H_ */

src/sysc/register_tgc_c.cpp

@@ -0,0 +1,110 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+// clang-format off
+#include "iss_factory.h"
+#include <iss/arch/tgc5c.h>
+#include <iss/arch/riscv_hart_m_p.h>
+#include <iss/arch/riscv_hart_mu_p.h>
+#include "sc_core_adapter.h"
+#include "core_complex.h"
+#include <array>
+// clang-format on
+
+namespace iss {
+namespace interp {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|interp",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace interp
+#if defined(WITH_LLVM)
+namespace llvm {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|llvm",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace llvm
+#endif
+#if defined(WITH_TCC)
+namespace tcc {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|tcc",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace tcc
+#endif
+#if defined(WITH_ASMJIT)
+namespace asmjit {
+using namespace sysc;
+volatile std::array<bool, 2> tgc_init = {
+    iss_factory::instance().register_creator("tgc5c|m_p|asmjit",
+                                             [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+                                                 return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+                                             }),
+    iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+        return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
+    })};
+} // namespace asmjit
+#endif
+} // namespace iss

src/sysc/sc_core_adapter.h

@@ -0,0 +1,187 @@
+/*
+ * sc_core_adapter.h
+ *
+ *  Created on: Jul 5, 2023
+ *      Author: eyck
+ */
+
+#ifndef _SYSC_SC_CORE_ADAPTER_H_
+#define _SYSC_SC_CORE_ADAPTER_H_
+
+#include "sc_core_adapter_if.h"
+#include <iostream>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <scc/report.h>
+#include <util/ities.h>
+
+namespace sysc {
+template <typename PLAT> class sc_core_adapter : public PLAT, public sc_core_adapter_if {
+public:
+    using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
+    using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
+    using heart_state_t = typename PLAT::hart_state_type;
+    sc_core_adapter(sysc::tgfs::core_complex* owner)
+    : owner(owner) {}
+
+    iss::arch_if* get_arch_if() override { return this; }
+
+    void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
+
+    uint32_t get_mode() override { return this->reg.PRIV; }
+
+    void set_interrupt_execution(bool v) override { this->interrupt_sim = v ? 1 : 0; }
+
+    bool get_interrupt_execution() override { return this->interrupt_sim; }
+
+    uint64_t get_state() override { return this->state.mstatus.backing.val; }
+
+    void notify_phase(iss::arch_if::exec_phase p) override {
+        if(p == iss::arch_if::ISTART && !first) {
+            auto cycle_incr = owner->get_last_bus_cycles();
+            if(cycle_incr > 1)
+                this->instr_if.update_last_instr_cycles(cycle_incr);
+            owner->sync(this->instr_if.get_total_cycles());
+        }
+        first = false;
+    }
+
+    iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
+
+    void disass_output(uint64_t pc, const std::string instr) override {
+        static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
+        if(!owner->disass_output(pc, instr)) {
+            std::stringstream s;
+            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
+              << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
+            SCCDEBUG(owner->name()) << "disass: "
+                                    << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
+                                    << std::setfill(' ') << std::left << instr << s.str();
+        }
+    };
+
+    iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data) override {
+        if(addr.access && iss::access_type::DEBUG)
+            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+        else {
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
+        }
+    }
+
+    iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) override {
+        if(addr.access && iss::access_type::DEBUG)
+            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+        else {
+            auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) || (sizeof(reg_t) == 8 && addr.val == this->tohost);
+            auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) || (sizeof(reg_t) == 64 && addr.val == this->tohost);
+            if(tohost_lower || tohost_upper) {
+                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                    switch(hostvar >> 48) {
+                    case 0:
+                        if(hostvar != 0x1) {
+                            SCCINFO(owner->name())
+                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
+                        } else {
+                            SCCINFO(owner->name())
+                                << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
+                        }
+                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
+                        break;
+                    default:
+                        break;
+                    }
+                } else if(tohost_lower)
+                    to_host_wr_cnt++;
+                return iss::Ok;
+            } else {
+                auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
+                // clear MTIP on mtimecmp write
+                if(addr.val == 0x2004000) {
+                    reg_t val;
+                    this->read_csr(iss::arch::mip, val);
+                    if(val & (1ULL << 7))
+                        this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
+                }
+                return res;
+            }
+        }
+    }
+
+    iss::status read_csr(unsigned addr, reg_t& val) override {
+#ifndef CWR_SYSTEMC
+        if((addr == iss::arch::time || addr == iss::arch::timeh) && owner->mtime_o.get_interface(0)) {
+            uint64_t time_val;
+            bool ret = owner->mtime_o->nb_peek(time_val);
+            if(addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if(addr == iss::arch::timeh) {
+                if(sizeof(reg_t) != 4)
+                    return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return ret ? iss::Ok : iss::Err;
+#else
+        if((addr == iss::arch::time || addr == iss::arch::timeh)) {
+            uint64_t time_val = owner->mtime_i.read();
+            if(addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if(addr == iss::arch::timeh) {
+                if(sizeof(reg_t) != 4)
+                    return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return iss::Ok;
+#endif
+        } else {
+            return PLAT::read_csr(addr, val);
+        }
+    }
+
+    void wait_until(uint64_t flags) override {
+        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
+        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
+            sc_core::wait(wfi_evt);
+        }
+        PLAT::wait_until(flags);
+    }
+
+    void local_irq(short id, bool value) override {
+        reg_t mask = 0;
+        switch(id) {
+        case 3: // SW
+            mask = 1 << 3;
+            break;
+        case 7: // timer
+            mask = 1 << 7;
+            break;
+        case 11: // external
+            mask = 1 << 11;
+            break;
+        default:
+            if(id > 15)
+                mask = 1 << id;
+            break;
+        }
+        if(value) {
+            this->csr[iss::arch::mip] |= mask;
+            wfi_evt.notify();
+        } else
+            this->csr[iss::arch::mip] &= ~mask;
+        this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+    }
+
+private:
+    sysc::tgfs::core_complex* const owner;
+    sc_core::sc_event wfi_evt;
+    uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
+    unsigned to_host_wr_cnt = 0;
+    bool first{true};
+};
+} // namespace sysc
+#endif /* _SYSC_SC_CORE_ADAPTER_H_ */

src/sysc/sc_core_adapter_if.h

@@ -0,0 +1,30 @@
+/*
+ * sc_core_adapter.h
+ *
+ *  Created on: Jul 5, 2023
+ *      Author: eyck
+ */
+
+#ifndef _SYSC_SC_CORE_ADAPTER_IF_H_
+#define _SYSC_SC_CORE_ADAPTER_IF_H_
+
+#include "core_complex.h"
+#include <iostream>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <scc/report.h>
+#include <util/ities.h>
+
+namespace sysc {
+struct sc_core_adapter_if {
+    virtual iss::arch_if* get_arch_if() = 0;
+    virtual void set_mhartid(unsigned) = 0;
+    virtual uint32_t get_mode() = 0;
+    virtual uint64_t get_state() = 0;
+    virtual bool get_interrupt_execution() = 0;
+    virtual void set_interrupt_execution(bool v) = 0;
+    virtual void local_irq(short id, bool value) = 0;
+    virtual ~sc_core_adapter_if() = default;
+};
+} // namespace sysc
+#endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */

src/vm/fp_functions.cpp

@@ -35,97 +35,90 @@
 #include "fp_functions.h"
 
 extern "C" {
-#include <softfloat.h>
 #include "internals.h"
 #include "specialize.h"
+#include <softfloat.h>
 }
 
 #include <limits>
 
-using this_t = uint8_t *;
+using this_t = uint8_t*;
 const uint8_t rmm_map[] = {
-        softfloat_round_near_even /*RNE*/,
+    softfloat_round_near_even /*RNE*/,   softfloat_round_minMag /*RTZ*/, softfloat_round_min /*RDN*/, softfloat_round_max /*RUP?*/,
-        softfloat_round_minMag/*RTZ*/,
+    softfloat_round_near_maxMag /*RMM*/, softfloat_round_max /*RTZ*/,    softfloat_round_max /*RTZ*/, softfloat_round_max /*RTZ*/,
-        softfloat_round_min/*RDN*/,
-        softfloat_round_max/*RUP?*/,
-        softfloat_round_near_maxMag /*RMM*/,
-        softfloat_round_max/*RTZ*/,
-        softfloat_round_max/*RTZ*/,
-        softfloat_round_max/*RTZ*/,
 };
 
-const uint32_t quiet_nan32=0x7fC00000;
+const uint32_t quiet_nan32 = 0x7fC00000;
 
 extern "C" {
 
-uint32_t fget_flags(){
+uint32_t fget_flags() { return softfloat_exceptionFlags & 0x1f; }
-    return softfloat_exceptionFlags&0x1f;
-}
 
 uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
-    float32_t v1f{v1},v2f{v2};
+    float32_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t r =f32_add(v1f, v2f);
+    float32_t r = f32_add(v1f, v2f);
     return r.v;
 }
 
 uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) {
-    float32_t v1f{v1},v2f{v2};
+    float32_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t r=f32_sub(v1f, v2f);
+    float32_t r = f32_sub(v1f, v2f);
     return r.v;
 }
 
 uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) {
-    float32_t v1f{v1},v2f{v2};
+    float32_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t r=f32_mul(v1f, v2f);
+    float32_t r = f32_mul(v1f, v2f);
     return r.v;
 }
 
 uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) {
-    float32_t v1f{v1},v2f{v2};
+    float32_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t r=f32_div(v1f, v2f);
+    float32_t r = f32_div(v1f, v2f);
     return r.v;
 }
 
 uint32_t fsqrt_s(uint32_t v1, uint8_t mode) {
     float32_t v1f{v1};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t r=f32_sqrt(v1f);
+    float32_t r = f32_sqrt(v1f);
     return r.v;
 }
 
 uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
-    float32_t v1f{v1},v2f{v2};
+    float32_t v1f{v1}, v2f{v2};
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    bool nan = (v1&defaultNaNF32UI)==quiet_nan32 || (v2&defaultNaNF32UI)==quiet_nan32;
+    bool nan = (v1 & defaultNaNF32UI) == quiet_nan32 || (v2 & defaultNaNF32UI) == quiet_nan32;
     bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2);
-    switch(op){
+    switch(op) {
     case 0:
-        if(nan | snan){
+        if(nan | snan) {
-            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
+            if(snan)
+                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f32_eq(v1f,v2f )?1:0;
+            return f32_eq(v1f, v2f) ? 1 : 0;
     case 1:
-        if(nan | snan){
+        if(nan | snan) {
             softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f32_le(v1f,v2f )?1:0;
+            return f32_le(v1f, v2f) ? 1 : 0;
     case 2:
-        if(nan | snan){
+        if(nan | snan) {
             softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f32_lt(v1f,v2f )?1:0;
+            return f32_lt(v1f, v2f) ? 1 : 0;
     default:
         break;
     }
@@ -134,22 +127,22 @@ uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
 
 uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
     float32_t v1f{v1};
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
     float32_t r;
-    switch(op){
+    switch(op) {
-    case 0:{ //w->s, fp to int32
+    case 0: { // w->s, fp to int32
-        uint_fast32_t res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
+        uint_fast32_t res = f32_to_i32(v1f, rmm_map[mode & 0x7], true);
         return (uint32_t)res;
     }
-    case 1:{ //wu->s
+    case 1: { // wu->s
-        uint_fast32_t res = f32_to_ui32(v1f,rmm_map[mode&0x7],true);
+        uint_fast32_t res = f32_to_ui32(v1f, rmm_map[mode & 0x7], true);
         return (uint32_t)res;
     }
-    case 2: //s->w
+    case 2: // s->w
-        r=i32_to_f32(v1);
+        r = i32_to_f32(v1);
         return r.v;
-    case 3: //s->wu
+    case 3: // s->wu
-        r=ui32_to_f32(v1);
+        r = ui32_to_f32(v1);
         return r.v;
     }
     return 0;
@@ -157,10 +150,11 @@ uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
 
 uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) {
     // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
+    float32_t res = softfloat_mulAddF32(v1, v2, v3, op & 0x1);
-    if(op>1) res.v ^= 1ULL<<31;
+    if(op > 1)
+        res.v ^= 1ULL << 31;
     return res.v;
 }
 
@@ -170,23 +164,23 @@ uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
     bool v1_snan = softfloat_isSigNaNF32UI(v1);
     bool v2_snan = softfloat_isSigNaNF32UI(v2);
-    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_snan || v2_snan)
-    if (v1_nan || v1_snan)
+        softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
-    else
+    else if(v2_nan || v2_snan)
-        if (v2_nan || v2_snan)
         return v1;
     else {
-            if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
+        if((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
             return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1);
         } else {
-                float32_t v1f{ v1 }, v2f{ v2 };
+            float32_t v1f{v1}, v2f{v2};
             return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1);
         }
     }
 }
 
-uint32_t fclass_s( uint32_t v1 ){
+uint32_t fclass_s(uint32_t v1) {
 
     float32_t a{v1};
     union ui32_f32 uA;
@@ -195,30 +189,23 @@ uint32_t fclass_s( uint32_t v1 ){
     uA.f = a;
     uiA = uA.ui;
 
-    uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
+    uint_fast16_t infOrNaN = expF32UI(uiA) == 0xFF;
-    uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
+    uint_fast16_t subnormalOrZero = expF32UI(uiA) == 0;
-    bool sign = signF32UI( uiA );
+    bool sign = signF32UI(uiA);
-    bool fracZero = fracF32UI( uiA ) == 0;
+    bool fracZero = fracF32UI(uiA) == 0;
-    bool isNaN = isNaNF32UI( uiA );
+    bool isNaN = isNaNF32UI(uiA);
-    bool isSNaN = softfloat_isSigNaNF32UI( uiA );
+    bool isSNaN = softfloat_isSigNaNF32UI(uiA);
 
-    return
+    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
-        (  sign && infOrNaN && fracZero )          << 0 |
+           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
-        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
+           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
-        (  sign && subnormalOrZero && !fracZero )  << 2 |
+           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
-        (  sign && subnormalOrZero && fracZero )   << 3 |
-        ( !sign && infOrNaN && fracZero )          << 7 |
-        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
-        ( !sign && subnormalOrZero && !fracZero )  << 5 |
-        ( !sign && subnormalOrZero && fracZero )   << 4 |
-        ( isNaN &&  isSNaN )                       << 8 |
-        ( isNaN && !isSNaN )                       << 9;
 }
 
-uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
+uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    bool nan = (v1 & defaultNaNF64UI)==defaultNaNF64UI;
+    bool nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
-    if(nan){
+    if(nan) {
         return defaultNaNF32UI;
     } else {
         float32_t res = f64_to_f32(float64_t{v1});
@@ -226,83 +213,84 @@ uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
     }
 }
 
-uint64_t fconv_f2d(uint32_t v1, uint8_t mode){
+uint64_t fconv_f2d(uint32_t v1, uint8_t mode) {
-    bool nan = (v1 & defaultNaNF32UI)==defaultNaNF32UI;
+    bool nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
-    if(nan){
+    if(nan) {
         return defaultNaNF64UI;
     } else {
-        softfloat_roundingMode=rmm_map[mode&0x7];
+        softfloat_roundingMode = rmm_map[mode & 0x7];
         float64_t res = f32_to_f64(float32_t{v1});
         return res.v;
     }
 }
 
 uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode) {
-    bool nan = (v1&defaultNaNF32UI)==quiet_nan32;
+    bool nan = (v1 & defaultNaNF32UI) == quiet_nan32;
     bool snan = softfloat_isSigNaNF32UI(v1);
-   float64_t v1f{v1},v2f{v2};
+    float64_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t r =f64_add(v1f, v2f);
+    float64_t r = f64_add(v1f, v2f);
     return r.v;
 }
 
 uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode) {
-    float64_t v1f{v1},v2f{v2};
+    float64_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t r=f64_sub(v1f, v2f);
+    float64_t r = f64_sub(v1f, v2f);
     return r.v;
 }
 
 uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode) {
-    float64_t v1f{v1},v2f{v2};
+    float64_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t r=f64_mul(v1f, v2f);
+    float64_t r = f64_mul(v1f, v2f);
     return r.v;
 }
 
 uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode) {
-    float64_t v1f{v1},v2f{v2};
+    float64_t v1f{v1}, v2f{v2};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t r=f64_div(v1f, v2f);
+    float64_t r = f64_div(v1f, v2f);
     return r.v;
 }
 
 uint64_t fsqrt_d(uint64_t v1, uint8_t mode) {
     float64_t v1f{v1};
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t r=f64_sqrt(v1f);
+    float64_t r = f64_sqrt(v1f);
     return r.v;
 }
 
 uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
-    float64_t v1f{v1},v2f{v2};
+    float64_t v1f{v1}, v2f{v2};
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    bool nan = (v1&defaultNaNF64UI)==quiet_nan32 || (v2&defaultNaNF64UI)==quiet_nan32;
+    bool nan = (v1 & defaultNaNF64UI) == quiet_nan32 || (v2 & defaultNaNF64UI) == quiet_nan32;
     bool snan = softfloat_isSigNaNF64UI(v1) || softfloat_isSigNaNF64UI(v2);
-    switch(op){
+    switch(op) {
     case 0:
-        if(nan | snan){
+        if(nan | snan) {
-            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
+            if(snan)
+                softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f64_eq(v1f,v2f )?1:0;
+            return f64_eq(v1f, v2f) ? 1 : 0;
     case 1:
-        if(nan | snan){
+        if(nan | snan) {
             softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f64_le(v1f,v2f )?1:0;
+            return f64_le(v1f, v2f) ? 1 : 0;
     case 2:
-        if(nan | snan){
+        if(nan | snan) {
             softfloat_raiseFlags(softfloat_flag_invalid);
             return 0;
         } else
-            return f64_lt(v1f,v2f )?1:0;
+            return f64_lt(v1f, v2f) ? 1 : 0;
     default:
         break;
     }
@@ -311,22 +299,22 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
 
 uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
     float64_t v1f{v1};
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
     float64_t r;
-    switch(op){
+    switch(op) {
-    case 0:{ //l->d, fp to int32
+    case 0: { // l->d, fp to int32
-        int64_t res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
+        int64_t res = f64_to_i64(v1f, rmm_map[mode & 0x7], true);
         return (uint64_t)res;
     }
-    case 1:{ //lu->s
+    case 1: { // lu->s
-        uint64_t res = f64_to_ui64(v1f,rmm_map[mode&0x7],true);
+        uint64_t res = f64_to_ui64(v1f, rmm_map[mode & 0x7], true);
         return res;
     }
-    case 2: //s->l
+    case 2: // s->l
-        r=i64_to_f64(v1);
+        r = i64_to_f64(v1);
         return r.v;
-    case 3: //s->lu
+    case 3: // s->lu
-        r=ui64_to_f64(v1);
+        r = ui64_to_f64(v1);
         return r.v;
     }
     return 0;
@@ -334,10 +322,11 @@ uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
 
 uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
     // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
-    softfloat_roundingMode=rmm_map[mode&0x7];
+    softfloat_roundingMode = rmm_map[mode & 0x7];
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
-    float64_t res = softfloat_mulAddF64(v1, v2, v3, op&0x1);
+    float64_t res = softfloat_mulAddF64(v1, v2, v3, op & 0x1);
-    if(op>1) res.v ^= 1ULL<<63;
+    if(op > 1)
+        res.v ^= 1ULL << 63;
     return res.v;
 }
 
@@ -347,27 +336,24 @@ uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
     bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
     bool v1_snan = softfloat_isSigNaNF64UI(v1);
     bool v2_snan = softfloat_isSigNaNF64UI(v2);
-    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_snan || v2_snan)
-    if (v1_nan || v1_snan)
+        softfloat_raiseFlags(softfloat_flag_invalid);
+    if(v1_nan || v1_snan)
         return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
-    else
+    else if(v2_nan || v2_snan)
-        if (v2_nan || v2_snan)
         return v1;
     else {
-            if ((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
+        if((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
-                return op == 0 ?
+            return op == 0 ? ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2)
-                        ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
+                           : ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
-                        ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
         } else {
-                float64_t v1f{ v1 }, v2f{ v2 };
+            float64_t v1f{v1}, v2f{v2};
-                return op == 0 ?
+            return op == 0 ? (f64_lt(v1f, v2f) ? v1 : v2) : (f64_lt(v1f, v2f) ? v2 : v1);
-                        (f64_lt(v1f, v2f) ? v1 : v2) :
-                        (f64_lt(v1f, v2f) ? v2 : v1);
         }
     }
 }
 
-uint64_t fclass_d(uint64_t v1  ){
+uint64_t fclass_d(uint64_t v1) {
 
     float64_t a{v1};
     union ui64_f64 uA;
@@ -376,68 +362,61 @@ uint64_t fclass_d(uint64_t v1  ){
     uA.f = a;
     uiA = uA.ui;
 
-    uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
+    uint_fast16_t infOrNaN = expF64UI(uiA) == 0x7FF;
-    uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
+    uint_fast16_t subnormalOrZero = expF64UI(uiA) == 0;
-    bool sign = signF64UI( uiA );
+    bool sign = signF64UI(uiA);
-    bool fracZero = fracF64UI( uiA ) == 0;
+    bool fracZero = fracF64UI(uiA) == 0;
-    bool isNaN = isNaNF64UI( uiA );
+    bool isNaN = isNaNF64UI(uiA);
-    bool isSNaN = softfloat_isSigNaNF64UI( uiA );
+    bool isSNaN = softfloat_isSigNaNF64UI(uiA);
 
-    return
+    return (sign && infOrNaN && fracZero) << 0 | (sign && !infOrNaN && !subnormalOrZero) << 1 |
-        (  sign && infOrNaN && fracZero )          << 0 |
+           (sign && subnormalOrZero && !fracZero) << 2 | (sign && subnormalOrZero && fracZero) << 3 | (!sign && infOrNaN && fracZero) << 7 |
-        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
+           (!sign && !infOrNaN && !subnormalOrZero) << 6 | (!sign && subnormalOrZero && !fracZero) << 5 |
-        (  sign && subnormalOrZero && !fracZero )  << 2 |
+           (!sign && subnormalOrZero && fracZero) << 4 | (isNaN && isSNaN) << 8 | (isNaN && !isSNaN) << 9;
-        (  sign && subnormalOrZero && fracZero )   << 3 |
-        ( !sign && infOrNaN && fracZero )          << 7 |
-        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
-        ( !sign && subnormalOrZero && !fracZero )  << 5 |
-        ( !sign && subnormalOrZero && fracZero )   << 4 |
-        ( isNaN &&  isSNaN )                       << 8 |
-        ( isNaN && !isSNaN )                       << 9;
 }
 
 uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
     float32_t v1f{v1};
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
     float64_t r;
-    switch(op){
+    switch(op) {
-    case 0: //l->s, fp to int32
+    case 0: // l->s, fp to int32
-        return f32_to_i64(v1f,rmm_map[mode&0x7],true);
+        return f32_to_i64(v1f, rmm_map[mode & 0x7], true);
-    case 1: //wu->s
+    case 1: // wu->s
-        return f32_to_ui64(v1f,rmm_map[mode&0x7],true);
+        return f32_to_ui64(v1f, rmm_map[mode & 0x7], true);
-    case 2: //s->w
+    case 2: // s->w
-        r=i32_to_f64(v1);
+        r = i32_to_f64(v1);
         return r.v;
-    case 3: //s->wu
+    case 3: // s->wu
-        r=ui32_to_f64(v1);
+        r = ui32_to_f64(v1);
         return r.v;
     }
     return 0;
 }
 
 uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode) {
-    softfloat_exceptionFlags=0;
+    softfloat_exceptionFlags = 0;
     float32_t r;
-    switch(op){
+    switch(op) {
-    case 0:{ //wu->s
+    case 0: { // wu->s
-        int32_t r=f64_to_i32(float64_t{v1}, rmm_map[mode&0x7],true);
+        int32_t r = f64_to_i32(float64_t{v1}, rmm_map[mode & 0x7], true);
         return r;
     }
-    case 1:{ //wu->s
+    case 1: { // wu->s
-        uint32_t r=f64_to_ui32(float64_t{v1}, rmm_map[mode&0x7],true);
+        uint32_t r = f64_to_ui32(float64_t{v1}, rmm_map[mode & 0x7], true);
         return r;
     }
-    case 2: //l->s, fp to int32
+    case 2: // l->s, fp to int32
-        r=i64_to_f32(v1);
+        r = i64_to_f32(v1);
         return r.v;
-    case 3: //wu->s
+    case 3: // wu->s
-        r=ui64_to_f32(v1);
+        r = ui64_to_f32(v1);
         return r.v;
     }
     return 0;
 }
 
-uint32_t unbox_s(uint64_t v){
+uint32_t unbox_s(uint64_t v) {
     constexpr uint64_t mask = std::numeric_limits<uint64_t>::max() & ~((uint64_t)std::numeric_limits<uint32_t>::max());
     if((v & mask) != mask)
         return 0x7fc00000;
@@ -445,4 +424,3 @@ uint32_t unbox_s(uint64_t v){
         return v & std::numeric_limits<uint32_t>::max();
 }
 }
-

src/vm/fp_functions.h

@@ -44,11 +44,11 @@ uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode);
 uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode);
 uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode);
 uint32_t fsqrt_s(uint32_t v1, uint8_t mode);
-uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) ;
+uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op);
 uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode);
 uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode);
 uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op);
-uint32_t fclass_s( uint32_t v1 );
+uint32_t fclass_s(uint32_t v1);
 uint32_t fconv_d2f(uint64_t v1, uint8_t mode);
 uint64_t fconv_f2d(uint32_t v1, uint8_t mode);
 uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode);
@@ -59,8 +59,8 @@ uint64_t fsqrt_d(uint64_t v1, uint8_t mode);
 uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op);
 uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode);
 uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode);
-uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) ;
+uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op);
-uint64_t fclass_d(uint64_t v1  );
+uint64_t fclass_d(uint64_t v1);
 uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode);
 uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode);
 uint32_t unbox_s(uint64_t v);

src/vm/instruction_decoder.cpp

@@ -0,0 +1,103 @@
+/*******************************************************************************
+ * Copyright (C) 2024 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       alex@minres.com - initial implementation
+ ******************************************************************************/
+
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <limits>
+#include <numeric>
+#include <vector>
+#include <vm/instruction_decoder.h>
+
+decoder::decoder(std::vector<generic_instruction_descriptor> instr_list) {
+    for(auto instr : instr_list) {
+        root.instrs.push_back(instr);
+    }
+    populate_decoding_tree(root);
+}
+
+void decoder::populate_decoding_tree(decoding_tree_node& parent) {
+    // create submask
+    parent.submask =
+        std::accumulate(parent.instrs.begin(), parent.instrs.end(), std::numeric_limits<uint32_t>::max(),
+                        [](int current_submask, const generic_instruction_descriptor& instr) { return current_submask & instr.mask; });
+    //  put each instr according to submask&encoding into children
+    for(auto instr : parent.instrs) {
+        bool foundMatch = false;
+        for(auto& child : parent.children) {
+            // use value as identifying trait
+            if(child.value == (instr.value & parent.submask)) {
+                child.instrs.push_back(instr);
+                foundMatch = true;
+            }
+        }
+        if(!foundMatch) {
+            decoding_tree_node child = decoding_tree_node(instr.value & parent.submask);
+            child.instrs.push_back(instr);
+            parent.children.push_back(child);
+        }
+    }
+    parent.instrs.clear();
+    // call populate_decoding_tree for all children
+    if(parent.children.size() > 1)
+        for(auto& child : parent.children) {
+            populate_decoding_tree(child);
+        }
+    else {
+        // sort instrs by value of the mask, so we have the least restrictive mask last
+        std::sort(parent.children[0].instrs.begin(), parent.children[0].instrs.end(),
+                  [](const generic_instruction_descriptor& instr1, const generic_instruction_descriptor& instr2) {
+                      return instr1.mask > instr2.mask;
+                  });
+    }
+}
+uint32_t decoder::decode_instr(uint32_t word) { return _decode_instr(this->root, word); }
+uint32_t decoder::_decode_instr(decoding_tree_node const& node, uint32_t word) {
+    if(!node.children.size()) {
+        if(node.instrs.size() == 1)
+            return node.instrs[0].index;
+        for(auto instr : node.instrs) {
+            if((instr.mask & word) == instr.value)
+                return instr.index;
+        }
+    } else {
+        for(auto child : node.children) {
+            if(child.value == (node.submask & word)) {
+                return _decode_instr(child, word);
+            }
+        }
+    }
+    return std::numeric_limits<uint32_t>::max();
+}

src/vm/instruction_decoder.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2024 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,35 +28,36 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- *******************************************************************************/
+ * Contributors:
+ *       alex@minres.com - initial implementation
+ ******************************************************************************/
 
-#ifndef _ISS_FACTORY_H_
+#include <cstddef>
-#define _ISS_FACTORY_H_
+#include <cstdint>
+#include <limits>
+#include <vector>
 
-#include <iss/iss.h>
+struct generic_instruction_descriptor {
+    uint32_t value;
+    uint32_t mask;
+    uint32_t index;
+};
 
-namespace iss {
+struct decoding_tree_node {
+    std::vector<generic_instruction_descriptor> instrs;
+    std::vector<decoding_tree_node> children;
+    uint32_t submask = std::numeric_limits<uint32_t>::max();
+    uint32_t value;
+    decoding_tree_node(uint32_t value)
+    : value(value) {}
+};
+class decoder {
+public:
+    decoder(std::vector<generic_instruction_descriptor> instr_list);
+    uint32_t decode_instr(uint32_t word);
 
-using cpu_ptr = std::unique_ptr<iss::arch_if>;
+private:
-using vm_ptr= std::unique_ptr<iss::vm_if>;
+    decoding_tree_node root{decoding_tree_node(std::numeric_limits<uint32_t>::max())};
-
+    void populate_decoding_tree(decoding_tree_node& root);
-template<typename PLAT>
+    uint32_t _decode_instr(decoding_tree_node const& node, uint32_t word);
-std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
+};
-    using core_type = typename PLAT::core;
-    core_type* lcpu = new PLAT();
-    if(backend == "interp")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-#ifdef WITH_LLVM
-    if(backend == "llvm")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-#ifdef WITH_LLVM
-    if(backend == "tcc")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-#endif
-    return {nullptr, nullptr};
-}
-
-}
-
-#endif /* _ISS_FACTORY_H_ */

src/vm/interp/.gitignore

@@ -1 +0,0 @@
-/vm_tgc_*.cpp

src/vm/llvm/fp_impl.cpp

@@ -36,9 +36,9 @@
 #include <iss/llvm/vm_base.h>
 
 extern "C" {
-#include <softfloat.h>
 #include "internals.h"
 #include "specialize.h"
+#include <softfloat.h>
 }
 
 #include <limits>
@@ -56,22 +56,21 @@ using namespace ::llvm;
 #define VOID_TYPE Type::getVoidTy(mod->getContext())
 #define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
 #define FDECLL(NAME, RET, ...)                                                                                                             \
-    Function *NAME##_func = CurrentModule->getFunction(#NAME);                                                         \
+    Function* NAME##_func = CurrentModule->getFunction(#NAME);                                                                             \
-    if (!NAME##_func) {                                                                                                \
+    if(!NAME##_func) {                                                                                                                     \
-        std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                  \
+        std::vector<Type*> NAME##_args{__VA_ARGS__};                                                                                       \
-        FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                        \
+        FunctionType* NAME##_type = FunctionType::get(RET, NAME##_args, false);                                                            \
         NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule);                                   \
         NAME##_func->setCallingConv(CallingConv::C);                                                                                       \
     }
 
 #define FDECL(NAME, RET, ...)                                                                                                              \
-    std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                      \
+    std::vector<Type*> NAME##_args{__VA_ARGS__};                                                                                           \
-    FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                      \
+    FunctionType* NAME##_type = FunctionType::get(RET, NAME##_args, false);                                                                \
     mod->getOrInsertFunction(#NAME, NAME##_type);
 
-
+void add_fp_functions_2_module(Module* mod, uint32_t flen, uint32_t xlen) {
-void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
+    if(flen) {
-    if(flen){
         FDECL(fget_flags, INT_TYPE(32));
         FDECL(fadd_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fsub_s, INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
@@ -85,7 +84,7 @@ void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
         FDECL(fclass_s, INT_TYPE(32), INT_TYPE(32));
         FDECL(fcvt_32_64, INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
         FDECL(fcvt_64_32, INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
-        if(flen>32){
+        if(flen > 32) {
             FDECL(fconv_d2f, INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
             FDECL(fconv_f2d, INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
             FDECL(fadd_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
@@ -99,11 +98,10 @@ void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
             FDECL(fsel_d, INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
             FDECL(fclass_d, INT_TYPE(64), INT_TYPE(64));
             FDECL(unbox_s, INT_TYPE(32), INT_TYPE(64));
-
         }
     }
 }
 
-}
+} // namespace fp_impl
-}
+} // namespace llvm
-}
+} // namespace iss