adds support for compressed instructions

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output

.gitignore

@@ -31,3 +31,5 @@ language.settings.xml
 /*.out
 /dump.json
 /src-gen/
+/*.yaml
+/*.json

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
-	path = gen_input/CoreDSL-Instruction-Set-Description
-	url = ../CoreDSL-Instruction-Set-Description.git

CMakeLists.txt

@@ -1,20 +1,22 @@
 cmake_minimum_required(VERSION 3.12)
-
-project(dbt-core-tgc VERSION 1.0.0)
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
-conan_basic_setup()
+find_package(elfio QUIET)
+find_package(Boost COMPONENTS coroutine)
 
-find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
 if(WITH_LLVM)
-	if(DEFINED ENV{LLVM_HOME})
-		find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
-	endif(DEFINED ENV{LLVM_HOME})
-	find_package(LLVM REQUIRED CONFIG)
-	message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
-	message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
-	llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
+    if(DEFINED ENV{LLVM_HOME})
+        find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
+    endif(DEFINED ENV{LLVM_HOME})
+    find_package(LLVM REQUIRED CONFIG)
+    message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
+    message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
+    llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
 endif()
 
 #Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
@@ -27,95 +29,159 @@ endif()
 add_subdirectory(softfloat)
 
 # library files
-FILE(GLOB TGC_SOURCES
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
-)
+FILE(GLOB TGC_SOURCES    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp) 
+FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
+
 set(LIB_SOURCES 
-	src/vm/fp_functions.cpp
+    src/vm/fp_functions.cpp
     src/plugin/instruction_count.cpp
-    src/plugin/cycle_estimate.cpp
+    
     ${TGC_SOURCES}
+    ${TGC_VM_SOURCES}
 )
+if(TARGET RapidJSON)
+    list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
+endif()
 
 if(WITH_LLVM)
-  set(LIB_SOURCES ${LIB_SOURCES}
-	src/vm/llvm/fp_impl.cpp
-    #src/vm/llvm/vm_tgf_b.cpp
-    #src/vm/llvm/vm_tgf_c.cpp
-  )
+	FILE(GLOB TGC_LLVM_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
+	)
+	list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
+endif()
+
+if(WITH_TCC)
+	FILE(GLOB TGC_TCC_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
+	)
+	list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
 endif()
 
 # Define the library
-add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
+add_library(${PROJECT_NAME} ${LIB_SOURCES})
 # list code gen dependencies
 if(TARGET ${CORE_NAME}_cpp)
     add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
 endif()
 
-target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
+elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
+    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
+endif()
 target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-target_link_libraries(${PROJECT_NAME} PUBLIC ${Boost_LIBRARIES} )
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp Boost::coroutine)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
+endif()
+if(TARGET CONAN_PKG::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
+elseif(TARGET elfio::elfio)
+    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
+else()
+    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
+endif()
+if(TARGET lz4::lz4)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
+    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
+endif()
+if(TARGET RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
+endif()
+
+
 set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
   FRAMEWORK FALSE
-  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )
-
-if(SystemC_FOUND)
-	add_library(${PROJECT_NAME}_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SYSTEMC)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_B)
-    endif()
-	if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_C)
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME}_sc PRIVATE CORE_TGC_D)
-    endif()
-	target_include_directories(${PROJECT_NAME}_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
-	
-	if(SCV_FOUND)   
-	    target_compile_definitions(${PROJECT_NAME}_sc PUBLIC WITH_SCV)
-	    target_include_directories(${PROJECT_NAME}_sc PUBLIC ${SCV_INCLUDE_DIRS})
-	endif()
-	target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${PROJECT_NAME} scc)
-	if(WITH_LLVM)
-		target_link_libraries(${PROJECT_NAME}_sc PUBLIC ${llvm_libs})
-	endif()
-	set_target_properties(${PROJECT_NAME}_sc PROPERTIES
-	  VERSION ${PROJECT_VERSION}
-	  FRAMEWORK FALSE
-	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
-	)
-endif()
-
-project(tgc-sim)
-add_executable(${PROJECT_NAME} src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
-target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-if(WITH_LLVM)
-	target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-	target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-endif()
-# Links the target exe against the libraries
-target_link_libraries(${PROJECT_NAME} dbt-core-tgc)
-target_link_libraries(${PROJECT_NAME} jsoncpp)
-target_link_libraries(${PROJECT_NAME} ${Boost_LIBRARIES} )
-if (Tcmalloc_FOUND)
-    target_link_libraries(${PROJECT_NAME} ${Tcmalloc_LIBRARIES})
-endif(Tcmalloc_FOUND)
-
-install(TARGETS dbt-core-tgc tgc-sim
+install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel   # headers for mac (note the different component -> different package)
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
   INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 )
+install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
+        DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
+        FILES_MATCHING # install only matched files
+        PATTERN "*.h" # select header files
+        )
+###############################################################################
+#
+###############################################################################
+project(tgc-sim)
+find_package(Boost COMPONENTS program_options thread REQUIRED)
+
+add_executable(${PROJECT_NAME} src/main.cpp)
+foreach(F IN LISTS TGC_SOURCES)
+    string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+    string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+endforeach()
+
+if(WITH_LLVM)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+endif()
+# Links the target exe against the libraries
+target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
+if(TARGET Boost::program_options)
+    target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
+else()
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
+endif()
+target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
+if (Tcmalloc_FOUND)
+    target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
+endif(Tcmalloc_FOUND)
+
+install(TARGETS tgc-sim
+  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
+  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+)
+###############################################################################
+#
+###############################################################################
+project(dbt-rise-tgc_sc VERSION 1.0.0)
+
+include(SystemCPackage)
+if(SystemC_FOUND)
+    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    foreach(F IN LISTS TGC_SOURCES)
+        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endforeach()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    if(WITH_LLVM)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    endif()
+    
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+    set_target_properties(${PROJECT_NAME} PROPERTIES
+      VERSION ${PROJECT_VERSION}
+      FRAMEWORK FALSE
+      PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+    )
+    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
+	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
+	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
+	  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
+	  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
+	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+	)    
+endif()
+

contrib/build.tcl

@@ -0,0 +1,30 @@
+namespace eval Specification {
+    proc buildproc { args } {
+        global env
+        variable installDir
+        variable compiler
+        variable compiler [::scsh::get_backend_compiler]
+        #  set target $machine
+        set target [::scsh::machine]
+        set linkerOptions ""
+        set preprocessorOptions ""
+        set libversion $compiler
+        switch -exact -- $target {
+            "linux" {
+            	set install_dir $::env(TGFS_INSTALL_ROOT)
+                set incldir "${install_dir}/include"
+                set libdir "${install_dir}/lib64"
+                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
+                # Set the Linker paths.
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+            }
+            default {
+               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
+               return
+            }
+        }
+        ::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
+        ::scsh::cwr_append_ipsimbld_opts linker       "$linkerOptions"
+    }
+    ::scsh::add_build_callback [namespace current]::buildproc
+}

contrib/tgc_import.cc

@@ -0,0 +1,4 @@
+
+#include "sysc/core_complex.h"
+
+void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }

contrib/tgc_import.tcl

@@ -0,0 +1,50 @@
+#############################################################################
+#
+#############################################################################
+proc getScriptDirectory {} {
+    set dispScriptFile [file normalize [info script]]
+    set scriptFolder [file dirname $dispScriptFile]
+    return $scriptFolder
+}
+if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
+    set hardware /HARDWARE/HW/HW
+} else {
+    set hardware /HARDWARE
+}
+
+set scriptDir [getScriptDirectory]
+set top_design_name core_complex
+set clocks clk_i
+set resets rst_i
+set model_prefix "i_"
+set model_postfix ""
+
+::pct::new_project
+::pct::open_library TLM2_PL
+::pct::clear_systemc_defines
+::pct::clear_systemc_include_path
+::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
+::pct::set_import_protocol_generation_flag false
+::pct::set_update_existing_encaps_flag true
+::pct::set_dynamic_port_arrays_flag true
+::pct::set_import_scml_properties_flag true
+::pct::load_modules --set-category modules tgc_import.cc
+
+# Set Port Protocols correctly
+set block ${top_design_name}
+foreach clock ${clocks} {
+	::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
+}
+foreach reset ${resets} {
+    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
+}
+::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+
+# Set compile settings and look
+set block SYSTEM_LIBRARY:${top_design_name}
+::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_background_color_rgb $block 255 255 255 255
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+
+# export the result as component
+::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

gen_input/.gitignore

@@ -1 +1,2 @@
 /src-gen/
+/CoreDSL-Instruction-Set-Description

gen_input/TGC_C.core_desc

@@ -0,0 +1,13 @@
+import "RV32I.core_desc"
+import "RVM.core_desc"
+import "RVC.core_desc"
+
+Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MARCHID_VAL = 0x80000003;
+    }
+}

gen_input/TGFS.core_desc

@@ -1,37 +0,0 @@
-import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
-
-Core TGC_B provides RV32I {
-	architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000000000100000000;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-	}
-}
-
-Core TGC_C provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned PGSIZE = 0x1000; //1 << 12;
-        unsigned PGMASK = 0xfff; //PGSIZE-1
-    }
-}
-
-Core TGC_D provides RV32I, RV32M, RV32IC {
-    architectural_state {
-        unsigned XLEN=32;
-        unsigned PCLEN=32;
-        // definitions for the architecture wrapper
-        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-    }
-}

gen_input/templates/CORENAME.cpp.gtl

@@ -33,7 +33,7 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+	//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
     return regs
 }
 %>
@@ -51,19 +51,19 @@ constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::a
 constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
 constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
 
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
+    trap_state=0;
+    icount=0;
 }
 
 uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {

gen_input/templates/CORENAME.h.gtl

@@ -37,7 +37,7 @@ def nativeTypeSize(int size){
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
+    // regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
     return regs
 }
 def getRegisterOffsets(){
@@ -91,12 +91,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
     constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
     enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -140,16 +135,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
-    inline uint64_t get_icount() { return reg.icount; }
+    inline uint64_t get_icount() { return icount; }
 
     inline bool should_stop() { return interrupt_sim; }
 
@@ -167,21 +154,22 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
-    inline uint32_t get_last_branch() { return reg.last_branch; }
+    inline uint32_t get_last_branch() { return last_branch; }
+
 
-protected:
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%
         registers.each { reg -> if(reg.size>0) {%> 
         uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
         }}%>
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t last_branch;
     } reg;
 #pragma pack(pop)
+    uint32_t trap_state = 0, pending_trap = 0;
+    uint64_t icount = 0;
+    uint64_t cycle = 0;
+    uint64_t instret = 0;
+    uint32_t instruction = 0;
+    uint32_t last_branch = 0;
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -1,9 +1,12 @@
-{ 
+{
 	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"name"  :   "${instr.name}",
+			"size"  :   ${instr.length},
+			"encoding": "${instr.encoding}",
+            "mask":     "${instr.mask}",
+			"branch":   ${instr.modifiesPC},
+			"delay" :   ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -0,0 +1,16 @@
+<% def getInstructionGroups() {
+    def instrGroups = [:]
+    instructions.each {
+        def groupName = it['instruction'].eContainer().name
+        if(!instrGroups.containsKey(groupName)) {
+            instrGroups[groupName]=[]
+        }
+        instrGroups[groupName]+=it;
+    }
+    instrGroups
+}%><%getInstructionGroups().each{name, instrList -> %>
+${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
+  - ${it.instruction.name}:
+    encoding: ${it.encoding}
+    mask: ${it.mask}<%}}%>
+

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -29,7 +29,13 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
+<%
+import com.minres.coredsl.util.BigIntegerWithRadix
 
+def nativeTypeSize(int size){
+    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
+}
+%>
 #include "../fp_functions.h"
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/arch/riscv_hart_m_p.h>
@@ -39,6 +45,8 @@
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
+#include <boost/coroutine2/all.hpp>
+#include <functional>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -53,6 +61,7 @@ namespace interp {
 namespace ${coreDef.name.toLowerCase()} {
 using namespace iss::arch;
 using namespace iss::debugger;
+using namespace std::placeholders;
 
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
@@ -64,7 +73,7 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
-
+    
     vm_impl();
 
     vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
@@ -85,63 +94,34 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
     // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
     enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
     enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+    enum {
+        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
+        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
+    };
 
     std::array<compile_func, LUT_SIZE> lut;
 
     std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
     std::array<compile_func, LUT_SIZE> lut_11;
 
-    std::array<compile_func *, 4> qlut;
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        typename arch::traits<ARCH>::opcode_e id;
+    };
 
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
-    }
+    std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
+        this->core.trap_state = trap_val;
         this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
     }
 
@@ -153,43 +133,47 @@ protected:
         this->core.wait_until(type);
     }
 
+    using yield_t = boost::coroutines2::coroutine<void>::push_type;
+    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
+    std::vector<coro_t> spawn_blocks;
+
     template<typename T>
     T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
     inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
         auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
         return ret;
     }
     inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
         auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
         return ret;
     }
     inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
         auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
         return ret;
     }
     inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
         auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
         return ret;
     }
     inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
         super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
     }
     inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
         super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
     }
     inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
         super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
     }
     inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
         super::write_mem(space, addr, data);
-        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        if(this->core.trap_state) throw 0;
     }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
@@ -197,7 +181,18 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
-
+    
+    inline void process_spawn_blocks() {
+        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
+             if(*it){
+                 (*it)();
+                 ++it;
+             } else
+                 spawn_blocks.erase(it);
+    }
+<%functions.each{ it.eachLine { %>
+    ${it}<%}%>
+<%}%>
 private:
     /****************************************************************************
      * start opcode definitions
@@ -206,76 +201,15 @@ private:
         size_t length;
         uint32_t value;
         uint32_t mask;
-        compile_func op;
+        typename arch::traits<ARCH>::opcode_e op;
     };
 
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *PC=*NEXT_PC;
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */
-            <%instr.disass.eachLine{%>${it}
-            <%}%>
-        }
-        // used registers<%instr.usedVariables.each{ k,v->
-            if(v.isArray) {%>
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-        <%}}%>// calculate next pc value
-        *NEXT_PC = *PC + ${instr.length/8};
-        // execute instruction
-        try {
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>} catch(...){}
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  2);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
-    }
 
-    static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
+    //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
         auto phys_pc = this->core.v2p(pc);
         //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
@@ -296,49 +230,118 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
 
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
+    unsigned id=0;
     for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+        auto quadrant = instr.value & 0x3;
+        qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+    }
+    for(auto& lut: qlut){
+        std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+            return bit_count(a.mask) > bit_count(b.mask);
+        });
     }
 }
 
 inline bool is_count_limit_enabled(finish_cond_e cond){
     return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
 }
+
+inline bool is_jump_to_self_enabled(finish_cond_e cond){
+    return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
+}
+
+template <typename ARCH>
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+    for(auto& e: qlut[instr&0x3]){
+        if(!((instr&e.mask) ^ e.value )) return e.id;
+    }
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+}
+
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
-    // we fetch at max 4 byte, alignment is 2
-    enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
     auto pc=start;
+    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto& trap_state = this->core.trap_state;
+    auto& icount = this->core.icount;
+    auto& cycle = this->core.cycle;
+    auto& instret = this->core.instret;
+    auto& instr = this->core.instruction;
+    // we fetch at max 4 byte, alignment is 2
+    auto *const data = reinterpret_cast<uint8_t*>(&instr);
+
     while(!this->core.should_stop() &&
             !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        auto res = fetch_ins(pc, data);
-        if(res!=iss::Ok){
-            auto new_pc = super::core.enter_trap(TRAP_ID, pc.val, 0);
-            res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
-            if(res!=iss::Ok) throw simulation_stopped(0);
+        if(fetch_ins(pc, data)!=iss::Ok){
+            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+        } else {
+            if (is_jump_to_self_enabled(cond) &&
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto inst_id = decode_inst_id(instr);
+            // pre execution stuff
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
+            case arch::traits<ARCH>::opcode_e::${instr.name}: {
+		        <%instr.fields.eachLine{%>${it}
+		        <%}%>if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            <%instr.disass.eachLine{%>${it}
+		            <%}%>
+		        }
+		        // used registers<%instr.usedVariables.each{ k,v->
+		        if(v.isArray) {%>
+		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+		        <%}}%>// calculate next pc value
+		        *NEXT_PC = *PC + ${instr.length/8};
+		        // execute instruction
+		        <%instr.behavior.eachLine{%>${it}
+		        <%}%>TRAP_${instr.name}:break;
+	    	}// @suppress("No break at end of case")<%}%>
+            default: {
+                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                raise(0,  2);
+            }
+            }
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // trap check
+            if(trap_state!=0){
+                super::core.enter_trap(trap_state, pc.val, instr);
+            } else {
+                icount++;
+                instret++;
+            }
+            cycle++;
+            pc.val=*NEXT_PC;
+            this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.trap_state = this->core.pending_trap;
         }
-        if ((cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF &&
-                (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-        auto lut_val = extract_fields(insn);
-        auto f = qlut[insn & 0x3][lut_val];
-        if (!f)
-            f = &this_class::illegal_intruction;
-        pc = (this->*f)(pc, insn);
     }
     return pc;
 }
 
-} // namespace mnrv32
+}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {

incl/iss/arch/hwl.h

@@ -0,0 +1,100 @@
+/*******************************************************************************
+ * Copyright (C) 2022 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_HWL_H
+#define _RISCV_HART_M_P_HWL_H
+
+#include <iss/vm_types.h>
+
+namespace iss {
+namespace arch {
+
+template <typename BASE> class hwl : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = hwl<BASE>;
+    using reg_t = typename BASE::reg_t;
+
+    hwl();
+    virtual ~hwl() = default;
+
+protected:
+    iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
+    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
+};
+
+
+template<typename BASE>
+inline hwl<BASE>::hwl() {
+    for (unsigned addr = 0x800; addr < 0x803; ++addr){
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+    for (unsigned addr = 0x804; addr < 0x807; ++addr){
+        this->register_custom_csr_rd(addr);
+        this->register_custom_csr_wr(addr);
+    }
+}
+
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
+    switch(addr){
+    case 0x800: val = this->reg.lpstart0; break;
+    case 0x801: val = this->reg.lpend0;   break;
+    case 0x802: val = this->reg.lpcount0; break;
+    case 0x804: val = this->reg.lpstart1; break;
+    case 0x805: val = this->reg.lpend1;   break;
+    case 0x806: val = this->reg.lpcount1; break;
+    }
+    return iss::Ok;
+}
+
+template<typename BASE>
+inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
+    switch(addr){
+    case 0x800: this->reg.lpstart0 = val; break;
+    case 0x801: this->reg.lpend0   = val; break;
+    case 0x802: this->reg.lpcount0 = val; break;
+    case 0x804: this->reg.lpstart1 = val; break;
+    case 0x805: this->reg.lpend1   = val; break;
+    case 0x806: this->reg.lpcount1 = val; break;
+    }
+    return iss::Ok;
+}
+
+} // namespace arch
+} // namespace iss
+
+
+#endif /* _RISCV_HART_M_P_H */

incl/iss/arch/riscv_hart_common.h

@@ -43,6 +43,8 @@ namespace arch {
 
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
 
+enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
+
 enum riscv_csr {
     /* user-level CSR */
     // User Trap Setup
@@ -104,12 +106,19 @@ enum riscv_csr {
     mie = 0x304,
     mtvec = 0x305,
     mcounteren = 0x306,
+    mtvt = 0x307, //CLIC
     // Machine Trap Handling
     mscratch = 0x340,
     mepc = 0x341,
     mcause = 0x342,
     mtval = 0x343,
     mip = 0x344,
+    mxnti = 0x345, //CLIC
+    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
+    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
@@ -157,7 +166,8 @@ enum riscv_csr {
     // Debug Mode Registers
     dcsr = 0x7B0,
     dpc = 0x7B1,
-    dscratch = 0x7B2
+    dscratch0 = 0x7B2,
+    dscratch1 = 0x7B3
 };
 
 
@@ -178,7 +188,7 @@ enum {
 
 template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
 
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
 
 enum {
     ISA_A = 1,
@@ -204,6 +214,14 @@ struct vm_info {
     bool is_active() { return levels; }
 };
 
+struct feature_config {
+    uint64_t clic_base{0xc0000000};
+    unsigned clic_num_irq{16};
+    unsigned clic_num_trigger{0};
+    uint64_t tcm_base{0x10000000};
+    uint64_t tcm_size{0x8000};
+};
+
 class trap_load_access_fault : public trap_access {
 public:
     trap_load_access_fault(uint64_t badaddr)
@@ -229,6 +247,49 @@ public:
     trap_store_page_fault(uint64_t badaddr)
     : trap_access(15 << 16, badaddr) {}
 };
+
+inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 1 + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(data + i) = *(reg_ptr + 2 + i);
+    break;
+    case 3:
+        *data = *(reg_ptr + 3);
+    break;
+    }
+}
+
+inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
+    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
+    switch (offs & 0x3) {
+    case 0:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + i) = *(data + i);
+    break;
+    case 1:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 1 + i) = *(data + i);
+    break;
+    case 2:
+        for (auto i = 0U; i < length; ++i)
+            *(reg_ptr + 2 + i) = *(data + i);
+    break;
+    case 3:
+        *(reg_ptr + 3) = *data ;
+    break;
+    }
+}
+
 }
 }
 

incl/iss/arch/riscv_hart_m_p.h

@@ -66,7 +66,7 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE> class riscv_hart_m_p : public BASE {
+template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_m_p : public BASE {
 protected:
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char *, 16> trap_str = {{""
@@ -92,13 +92,15 @@ protected:
          "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
 public:
     using core = BASE;
-    using this_class = riscv_hart_m_p<BASE>;
+    using this_class = riscv_hart_m_p<BASE, FEAT>;
     using phys_addr_t = typename core::phys_addr_t;
     using reg_t = typename core::reg_t;
     using addr_t = typename core::addr_t;
 
-    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
-    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
+    using rd_csr_f    = iss::status (this_class::*)(unsigned addr, reg_t &);
+    using wr_csr_f    = iss::status (this_class::*)(unsigned addr, reg_t);
+    using mem_read_f  = iss::status(phys_addr_t addr, unsigned, uint8_t *const);
+    using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const);
 
     // primary template
     template <class T, class Enable = void> struct hart_state {};
@@ -144,24 +146,40 @@ public:
 
         mstatus_t mstatus;
 
-        static const reg_t mstatus_reset_val = 0;
+        static const reg_t mstatus_reset_val = 0x1800;
 
         void write_mstatus(T val) {
-            auto mask = get_mask();
+            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
             auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
             mstatus = new_val;
         }
 
-        T satp;
-
         static constexpr uint32_t get_mask() {
-            return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
+            //return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
+            //       +-SD
+            //       |        +-TSR
+            //       |        |+-TW
+            //       |        ||+-TVM
+            //       |        |||+-MXR
+            //       |        ||||+-SUM
+            //       |        |||||+-MPRV
+            //       |        |||||| +-XS
+            //       |        |||||| | +-FS
+            //       |        |||||| | | +-MPP
+            //       |        |||||| | | |  +-SPP
+            //       |        |||||| | | |  |+-MPIE
+            //       |        ||||||/|/|/|  ||   +-MIE
+            return 0b00000000000000000001100010001000;
         }
     };
     using hart_state_type = hart_state<reg_t>;
 
     constexpr reg_t get_irq_mask() {
-        return 0b101110111011; // only machine mode is supported
+        return 0b100010001000; // only machine mode is supported
+    }
+
+    constexpr reg_t get_pc_mask() {
+        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
     }
 
     riscv_hart_m_p();
@@ -185,7 +203,7 @@ public:
 
     void disass_output(uint64_t pc, const std::string instr) override {
         CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->reg.icount);
+                pc, instr, (reg_t)state.mstatus, this->icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@@ -202,10 +220,13 @@ public:
         csr[addr & csr.page_addr_mask] = val;
     }
 
+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
-        riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
+        riscv_instrumentation_if(riscv_hart_m_p<BASE, FEAT> &arch)
         : arch(arch) {}
         /**
          * get the name of this architecture
@@ -214,22 +235,31 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        uint64_t get_instr_word() override { return arch.instruction; }
 
-        riscv_hart_m_p<BASE> &arch;
+        uint64_t get_instr_count() override { return arch.icount; }
+
+        uint64_t get_pendig_traps() override { return arch.trap_state; }
+
+        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
+
+        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        riscv_hart_m_p<BASE, FEAT> &arch;
     };
 
     friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }
 
     virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
     virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
 
+    iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data);
+    iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data);
+
     virtual iss::status read_csr(unsigned addr, reg_t &val);
     virtual iss::status write_csr(unsigned addr, reg_t val);
 
@@ -254,71 +284,120 @@ protected:
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
+    uint8_t clic_cfg_reg{0};
+    uint32_t clic_info_reg{0};
+    std::array<uint32_t, 32> clic_inttrig_reg;
+    union clic_int_reg_t {
+        struct{
+            uint8_t ip;
+            uint8_t ie;
+            uint8_t attr;
+            uint8_t ctl;
+        };
+        uint32_t raw;
+    };
+    std::vector<clic_int_reg_t> clic_int_reg;
 
-private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
+    std::vector<uint8_t> tcm;
+
+    iss::status read_csr_reg(unsigned addr, reg_t &val);
+    iss::status write_csr_reg(unsigned addr, reg_t val);
     iss::status read_null(unsigned addr, reg_t &val);
     iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
     iss::status read_cycle(unsigned addr, reg_t &val);
     iss::status write_cycle(unsigned addr, reg_t val);
     iss::status read_instret(unsigned addr, reg_t &val);
     iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_mtvec(unsigned addr, reg_t &val);
+    iss::status read_tvec(unsigned addr, reg_t &val);
     iss::status read_time(unsigned addr, reg_t &val);
     iss::status read_status(unsigned addr, reg_t &val);
     iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
     iss::status read_ie(unsigned addr, reg_t &val);
     iss::status write_ie(unsigned addr, reg_t val);
     iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ip(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
+    iss::status write_epc(unsigned addr, reg_t val);
+    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
+    iss::status read_dcsr_reg(unsigned addr, reg_t &val);
+    iss::status write_dcsr_reg(unsigned addr, reg_t val);
+    iss::status read_dpc_reg(unsigned addr, reg_t &val);
+    iss::status write_dpc_reg(unsigned addr, reg_t val);
+
+    virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
+    virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
+
+    void register_custom_csr_rd(unsigned addr){
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
 
     reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
     std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
-protected:
     void check_interrupt();
+    bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
+    std::vector<std::tuple<uint64_t, uint64_t>> memfn_range;
+    std::vector<std::function<mem_read_f>> memfn_read;
+    std::vector<std::function<mem_write_f>> memfn_write;
+    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
+    uint64_t clic_base_addr{0};
+    unsigned clic_num_irq{0};
+    unsigned clic_num_trigger{0};
+    unsigned mcause_max_irq{16};
+    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
 };
 
-template <typename BASE>
-riscv_hart_m_p<BASE>::riscv_hart_m_p()
+template <typename BASE, features_e FEAT>
+riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
 : state()
 , instr_if(*this) {
+    // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
+    csr[mvendorid] = 0x669;
+    csr[marchid] = traits<BASE>::MARCHID_VAL;
+    csr[mimpid] = 1;
+    csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
+
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
-    for (unsigned addr = cycle; addr <= hpmcounter31; ++addr){
+    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
     }
-    for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){
+    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 7> addrs{{misa, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
+    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
     for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    csr_wr_cb[time] = nullptr;
     csr_rd_cb[timeh] = &this_class::read_time;
-    csr_wr_cb[timeh] = nullptr;
+    csr_rd_cb[cycle] = &this_class::read_cycle;
+    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    csr_rd_cb[instret] = &this_class::read_instret;
+    csr_rd_cb[instreth] = &this_class::read_instret;
+
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
     csr_rd_cb[mcycleh] = &this_class::read_cycle;
@@ -329,18 +408,71 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
     csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
     csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_ip;
+    csr_wr_cb[mip] = &this_class::write_null;
     csr_rd_cb[mie] = &this_class::read_ie;
     csr_wr_cb[mie] = &this_class::write_ie;
     csr_rd_cb[mhartid] = &this_class::read_hartid;
-    csr_rd_cb[mcounteren] = &this_class::read_null;
-    csr_wr_cb[mcounteren] = &this_class::write_null;
-    csr_rd_cb[mtvec] = &this_class::read_mtvec;
     csr_wr_cb[misa] = &this_class::write_null;
+    csr_wr_cb[mvendorid] = &this_class::write_null;
+    csr_wr_cb[marchid] = &this_class::write_null;
+    csr_wr_cb[mimpid] = &this_class::write_null;
+    if(FEAT & FEAT_CLIC) {
+        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
+        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mintstatus] = &this_class::write_null;
+        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
+        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
+        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
+        csr_wr_cb[mclicbase] = &this_class::write_null;
+
+        clic_base_addr=0xC0000000;
+        clic_num_irq=16;
+        clic_int_reg.resize(clic_num_irq);
+        clic_cfg_reg=0x20;
+        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
+        mcause_max_irq=clic_num_irq+16;
+        insert_mem_range(clic_base_addr, 0x5000UL,
+                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
+                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
+    }
+    if(FEAT & FEAT_TCM) {
+        tcm.resize(0x8000);
+        std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
+            auto offset=addr.val-0x10000000;
+            std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
+            return iss::Ok;
+        };
+        std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
+            auto offset=addr.val-0x10000000;
+            std::copy(data, data + length, tcm.data() + offset);
+            return iss::Ok;
+        };
+        insert_mem_range(0x10000000, 0x8000UL, read_clic_cb, write_clic_cb);
+    }
+    if(FEAT & FEAT_DEBUG){
+        csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
+        csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
+        csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
+        csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
+        csr_wr_cb[dpc] = &this_class::write_dpc_reg;
+        csr_rd_cb[dpc] = &this_class::read_dpc_reg;
+        csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
+        csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
+    }
 }
 
-template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
+template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
     FILE *fp = fopen(name.c_str(), "r");
     if (fp) {
         std::array<char, 5> buf;
@@ -358,6 +490,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                 if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
             if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
             if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
@@ -366,26 +499,61 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
                             traits<BASE>::MEM, pseg->get_physical_address(),
                             fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
                                    << pseg->get_physical_address();
                 }
             }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
-            }
 
-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
         }
         throw std::runtime_error("memory load file is not a valid elf file");
     }
     throw std::runtime_error("memory load file not found");
 }
 
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
+template<typename BASE, features_e FEAT>
+inline void riscv_hart_m_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
+        std::function<mem_write_f> wr_fn) {
+    std::tuple<uint64_t, uint64_t> entry{base, size};
+    auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
+            [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
+        return std::get<0>(a)<std::get<0>(b);
+    });
+    auto idx = std::distance(memfn_range.begin(), it);
+    memfn_range.insert(it, entry);
+    memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
+    memfn_write.insert(std::begin(memfn_write)+idx, wr_fn);
+}
+
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
         const uint64_t addr, const unsigned length, uint8_t *const data) {
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
@@ -399,20 +567,41 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
     try {
         switch (space) {
         case traits<BASE>::MEM: {
-            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
+            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
+                if (is_debug(access)) throw trap_access(0, addr);
+                this->trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
-                auto res = type==iss::address_type::PHYSICAL?
-                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                if(!is_debug(access) && (addr&(alignment-1))){
+                    this->trap_state = 1<<31 | 4<<16;
+                    fault_data=addr;
+                    return iss::Err;
+                }
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = iss::Err;
+                if(!is_fetch(access) && memfn_range.size()){
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
+                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
+                    });
+                    if(it!=std::end(memfn_range)) {
+                        auto idx = std::distance(std::begin(memfn_range), it);
+                        res = memfn_read[idx](phys_addr, length, data);
+                    } else
+                        res = read_mem( phys_addr, length, data);
+                } else {
+                    res = read_mem( phys_addr, length, data);
+                }
+                if (unlikely(res != iss::Ok)){
+                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    fault_data=addr;
+                }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                 return iss::Err;
             }
         } break;
@@ -437,13 +626,14 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
         return iss::Err;
     }
 }
 
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
         const uint64_t addr, const unsigned length, const uint8_t *const data) {
 #ifndef NDEBUG
     const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
@@ -474,18 +664,37 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
-                auto res = type==iss::address_type::PHYSICAL?
-                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok))
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
+                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
+                    this->trap_state = 1<<31 | 6<<16;
+                    fault_data=addr;
+                    return iss::Err;
+                }
+                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = iss::Err;
+                if(access != access_type::FETCH && memfn_range.size()){
+                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
+                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
+                    });
+                    if(it!=std::end(memfn_range)) {
+                        auto idx = std::distance(std::begin(memfn_range), it);
+                        res = memfn_write[idx]( phys_addr, length, data);
+                    } else
+                        res = write_mem( phys_addr, length, data);
+                } else {
+                    res = write_mem( phys_addr, length, data);
+                }
+                if (unlikely(res != iss::Ok)) {
+                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    fault_data=addr;
+                }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                 return iss::Err;
             }
 
@@ -544,12 +753,13 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
         return iss::Err;
     }
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
     if (addr >= csr.size()) return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
@@ -560,7 +770,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned add
     return (this->*(it->second))(addr, val);
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
     if (addr >= csr.size()) return iss::Err;
     auto req_priv_lvl = (addr >> 8) & 0x3;
     if (this->reg.PRIV < req_priv_lvl) // not having required privileges
@@ -573,23 +783,23 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned ad
     return (this->*(it->second))(addr, val);
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr_reg(unsigned addr, reg_t &val) {
     val = csr[addr];
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_null(unsigned addr, reg_t &val) {
     val = 0;
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr_reg(unsigned addr, reg_t val) {
     csr[addr] = val;
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
+    auto cycle_val = this->icount + cycle_offset;
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
@@ -599,7 +809,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
         if (addr == mcycleh)
             return iss::Err;
@@ -611,38 +821,38 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
             mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
         }
     }
-    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
-    if (addr == minstret) {
-        val = static_cast<reg_t>(this->reg.instret);
-    } else if (addr == minstreth) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
+    if ((addr&0xff) == (minstret&0xff)) {
+        val = static_cast<reg_t>(this->instret);
+    } else if ((addr&0xff) == (minstreth&0xff)) {
         if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(this->reg.instret >> 32);
+        val = static_cast<reg_t>(this->instret >> 32);
     }
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == minstreth)
+        if ((addr&0xff) == (minstreth&0xff))
             return iss::Err;
-        this->reg.instret = static_cast<uint64_t>(val);
+        this->instret = static_cast<uint64_t>(val);
     } else {
-        if (addr == minstret) {
-            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
+        if ((addr&0xff) == (minstret&0xff)) {
+            this->instret = (this->instret & 0xffffffff00000000) + val;
         } else  {
-            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
+            this->instret = (static_cast<uint64_t>(val)<<32) + (this->instret & 0xffffffff);
         }
     }
-    this->reg.instret--;
+    this->instret--;
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
+    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
@@ -652,56 +862,103 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_mtvec(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
     val = csr[mtvec] & ~2;
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
     val = state.mstatus & hart_state_type::get_mask();
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
     state.write_mstatus(val);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
-    val = csr[mie];
-    val &= csr[mideleg];
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
+    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
     val = mhartid_reg;
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
+    auto mask = get_irq_mask();
+    val = csr[mie] & mask;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     auto mask = get_irq_mask();
     csr[mie] = (csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
-    val = csr[mip];
-    val &= csr[mideleg];
-    return iss::Ok;
-}
-
-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
     auto mask = get_irq_mask();
-    mask &= ~(1 << 7); // MTIP is read only
-    csr[mip] = (csr[mip] & ~mask) | (val & mask);
-    check_interrupt();
+    val = csr[mip] & mask;
     return iss::Ok;
 }
 
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
+    csr[addr] = val & get_pc_mask();
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    //                  +-------------- ebreakm
+    //                  |   +---------- stepi
+    //                  |   |  +++----- cause
+    //                  |   |  |||   +- step
+    csr[addr] = val & 0b1000100111000100U;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    val = csr[addr];
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    csr[addr] = val;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    val = this->reg.DPC;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
+    if(!debug_mode_active())
+        throw illegal_instruction_fault(this->fault_data);
+    this->reg.DPC = val;
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
+    csr[addr]= val &0xff;
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x0200BFF8: { // CLINT base, mtime reg
@@ -714,7 +971,7 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
         const mem_type::page_type &p = mem(paddr.val / mem.page_size);
         uint64_t offs = paddr.val & mem.page_addr_mask;
         std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->reg.icount > 30000) data[3] |= 0x80;
+        if (this->icount > 30000) data[3] |= 0x80;
     } break;
     default: {
         for(auto offs=0U; offs<length; ++offs) {
@@ -725,9 +982,8 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
     return iss::Ok;
 }
 
-template <typename BASE>
-iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
     if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
@@ -759,9 +1015,10 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
         // tohost handling in case of riscv-test
         if (paddr.access && iss::access_type::FUNC) {
-            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4));
+            auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
+                                (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             auto tohost_lower =
-                (traits<BASE>::XLEN == 32 && paddr.val == tohost);
+                (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if (tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
                 if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
@@ -774,7 +1031,7 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
                             LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                       << "), stopping simulation";
                         }
-                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
+                        this->trap_state=std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim=hostvar;
                         break;
                         //throw(iss::simulation_stopped(hostvar));
@@ -792,7 +1049,8 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
                     }
                 } else if (tohost_lower)
                     to_host_wr_cnt++;
-            } else if (traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) {
+            } else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
+                       (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
@@ -802,13 +1060,49 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
     return iss::Ok;
 }
 
-template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
+    if(addr==clic_base_addr) { // cliccfg
+        *data=clic_cfg_reg;
+        for(auto i=1; i<length; ++i) *(data+i)=0;
+    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
+        read_reg_uint32(addr, clic_info_reg, data, length);
+    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
+        auto offset = ((addr&0x7fff)-0x40)/4;
+        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
+    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+        auto offset = ((addr&0x7fff)-0x1000)/4;
+        read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+    } else {
+        for(auto i = 0U; i<length; ++i) *(data+i)=0;
+    }
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
+    if(addr==clic_base_addr) { // cliccfg
+        clic_cfg_reg = *data;
+        clic_cfg_reg&= 0x7e;
+//    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
+//        write_uint32(addr, clic_info_reg, data, length);
+    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
+        auto offset = ((addr&0x7fff)-0x40)/4;
+        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
+    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+        auto offset = ((addr&0x7fff)-0x1000)/4;
+        write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+    }
+    return iss::Ok;
+}
+
+template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
     state.mstatus = hart_state_type::mstatus_reset_val;
 }
 
-template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
-    auto ideleg = csr[mideleg];
+template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
+    //auto ideleg = csr[mideleg];
     // Multiple simultaneous interrupts and traps at the same privilege level are
     // handled in the following decreasing priority order:
     // external interrupts, software interrupts, timer interrupts, then finally
@@ -817,7 +1111,7 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
 
     bool mie = state.mstatus.MIE;
     auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
-    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
+    auto enabled_interrupts = m_enabled ? ena_irq : 0;
 
     if (enabled_interrupts != 0) {
         int res = 0;
@@ -825,27 +1119,57 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
         	enabled_interrupts >>= 1;
         	res++;
         }
-        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+        this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
 
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
     auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
-    if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
     // calculate effective privilege level
+    unsigned new_priv = PRIV_M;
     if (trap_id == 0) { // exception
+        if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
         // store ret addr in xepc register
-        csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
-        csr[mtval] = cause==2?instr:fault_data;
+        csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
+        /*
+         * write mtval if new_priv=M_MODE, spec says:
+         * When a hardware breakpoint is triggered, or an instruction-fetch, load,
+         * or store address-misaligned,
+         * access, or page-fault exception occurs, mtval is written with the
+         * faulting effective address.
+         */
+        switch(cause){
+        case 0:
+            csr[mtval] = static_cast<reg_t>(addr);
+            break;
+        case 2:
+            csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
+            break;
+        case 3:
+            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
+                this->reg.DPC = addr;
+                csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
+                new_priv = this->reg.PRIV | PRIV_D;
+            } else {
+                csr[mtval] = addr;
+            }
+            break;
+        case 4:
+        case 6:
+            csr[mtval] = fault_data;
+            break;
+        default:
+            csr[mtval] = 0;
+        }
         fault_data = 0;
     } else {
-        csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
-        this->reg.pending_trap = 0;
+        csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
+        this->pending_trap = 0;
     }
-    csr[mcause] = (trap_id << 31) + cause;
+    csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
     // update mstatus
     // xPP field of mstatus is written with the active privilege mode at the time
     // of the trap; the x PIE field of mstatus
@@ -864,10 +1188,14 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
     this->reg.NEXT_PC = ivec & ~0x3UL;
     if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
     // reset trap state
-    this->reg.PRIV = PRIV_M;
-    this->reg.trap_state = 0;
+    this->reg.PRIV = new_priv;
+    this->trap_state = 0;
     std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+    sprintf(buffer.data(), "0x%016llx", addr);
+#else
     sprintf(buffer.data(), "0x%016lx", addr);
+#endif
     if((flags&0xffffffff) != 0xffffffff)
     CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
                        << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
@@ -875,11 +1203,13 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::leave_trap(uint64_t flags) {
     state.mstatus.MIE = state.mstatus.MPIE;
+    state.mstatus.MPIE = 1;
     // sets the pc to the value stored in the x epc register.
-    this->reg.NEXT_PC = csr[mepc];
+    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
     CLOG(INFO, disass) << "Executing xRET";
+    check_interrupt();
     return this->reg.NEXT_PC;
 }
 

incl/iss/arch/riscv_hart_msu_vp.h

@@ -145,7 +145,7 @@ public:
 
         mstatus_t mstatus;
 
-        static const reg_t mstatus_reset_val = 0;
+        static const reg_t mstatus_reset_val = 0x1800;
 
         void write_mstatus(T val, unsigned priv_lvl) {
             auto mask = get_mask(priv_lvl);
@@ -293,21 +293,21 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
+    phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
     iss::status read(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, uint8_t *const data) override;
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {
         CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.ccount);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->icount + cycle_offset);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@@ -340,6 +340,14 @@ protected:
 
         virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
 
+        uint64_t get_instr_word() override { return arch.instruction; }
+
+        uint64_t get_instr_count() { return arch.icount; }
+
+        uint64_t get_pendig_traps() override { return arch.trap_state; }
+
+        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
+
         virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_msu_vp<BASE> &arch;
@@ -356,7 +364,10 @@ protected:
     virtual iss::status write_csr(unsigned addr, reg_t val);
 
     hart_state_type state;
-    uint64_t cycle_offset;
+    int64_t cycle_offset{0};
+    uint64_t mcycle_csr{0};
+    int64_t instret_offset{0};
+    uint64_t minstret_csr{0};
     reg_t fault_data;
     std::array<vm_info, 2> vm;
     uint64_t tohost = tohost_dflt;
@@ -377,23 +388,39 @@ protected:
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
 
 private:
-    iss::status read_null(unsigned addr, reg_t &val);
     iss::status read_reg(unsigned addr, reg_t &val);
     iss::status write_reg(unsigned addr, reg_t val);
+    iss::status read_null(unsigned addr, reg_t &val);
+    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
     iss::status read_cycle(unsigned addr, reg_t &val);
+    iss::status write_cycle(unsigned addr, reg_t val);
+    iss::status read_instret(unsigned addr, reg_t &val);
+    iss::status write_instret(unsigned addr, reg_t val);
+    iss::status read_mtvec(unsigned addr, reg_t &val);
     iss::status read_time(unsigned addr, reg_t &val);
     iss::status read_status(unsigned addr, reg_t &val);
     iss::status write_status(unsigned addr, reg_t val);
+    iss::status write_cause(unsigned addr, reg_t val);
     iss::status read_ie(unsigned addr, reg_t &val);
     iss::status write_ie(unsigned addr, reg_t val);
     iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ip(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
+    iss::status write_epc(unsigned addr, reg_t val);
     iss::status read_satp(unsigned addr, reg_t &val);
     iss::status write_satp(unsigned addr, reg_t val);
     iss::status read_fcsr(unsigned addr, reg_t &val);
     iss::status write_fcsr(unsigned addr, reg_t val);
 
+    virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
+    virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
+
+    void register_custom_csr_rd(unsigned addr){
+        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
+    }
+    void register_custom_csr_wr(unsigned addr){
+        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
+    }
+
     reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
     std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
@@ -405,15 +432,19 @@ protected:
 template <typename BASE>
 riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
 : state()
-, cycle_offset(0)
 , instr_if(*this) {
-    csr[misa] = hart_state_type::get_misa();
+    // reset values
+    csr[misa] = traits<BASE>::MISA_VAL;
+    csr[mvendorid] = 0x669;
+    csr[marchid] = traits<BASE>::MARCHID_VAL;
+    csr[mimpid] = 1;
+
     uart_buf.str("");
-    for (unsigned addr = mcycle; addr <= mhpmcounter31; ++addr){
+    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_reg;
     }
-    for (unsigned addr = mcycleh; addr <= mhpmcounter31h; ++addr){
+    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_reg;
     }
@@ -421,35 +452,61 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_reg;
     }
-    for (unsigned addr = cycle; addr <= hpmcounter31; ++addr){
+    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
     }
     for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
+        //csr_wr_cb[addr] = &this_class::write_reg;
+    }
+    // common regs
+    const std::array<unsigned, 22> addrs{{
+        misa, mvendorid, marchid, mimpid,
+        mepc, mtvec, mscratch, mcause, mtval, mscratch,
+        sepc, stvec, sscratch, scause, stval, sscratch,
+        uepc, utvec, uscratch, ucause, utval, uscratch
+    }};
+    for(auto addr: addrs) {
+        csr_rd_cb[addr] = &this_class::read_reg;
         csr_wr_cb[addr] = &this_class::write_reg;
     }
-    // special handling
+    // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    csr_wr_cb[time] = nullptr;
     csr_rd_cb[timeh] = &this_class::read_time;
-    csr_wr_cb[timeh] = nullptr;
+    csr_rd_cb[cycle] = &this_class::read_cycle;
+    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    csr_rd_cb[instret] = &this_class::read_instret;
+    csr_rd_cb[instreth] = &this_class::read_instret;
+
     csr_rd_cb[mcycle] = &this_class::read_cycle;
+    csr_wr_cb[mcycle] = &this_class::write_cycle;
     csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_rd_cb[minstret] = &this_class::read_cycle;
-    csr_rd_cb[minstreth] = &this_class::read_cycle;
+    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    csr_rd_cb[minstret] = &this_class::read_instret;
+    csr_wr_cb[minstret] = &this_class::write_instret;
+    csr_rd_cb[minstreth] = &this_class::read_instret;
+    csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_wr_cb[mcause] = &this_class::write_cause;
     csr_rd_cb[sstatus] = &this_class::read_status;
     csr_wr_cb[sstatus] = &this_class::write_status;
+    csr_wr_cb[scause] = &this_class::write_cause;
     csr_rd_cb[ustatus] = &this_class::read_status;
     csr_wr_cb[ustatus] = &this_class::write_status;
+    csr_wr_cb[ucause] = &this_class::write_cause;
+    csr_rd_cb[mtvec] = &this_class::read_tvec;
+    csr_rd_cb[stvec] = &this_class::read_tvec;
+    csr_rd_cb[utvec] = &this_class::read_tvec;
+    csr_wr_cb[mepc] = &this_class::write_epc;
+    csr_wr_cb[sepc] = &this_class::write_epc;
+    csr_wr_cb[uepc] = &this_class::write_epc;
     csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_ip;
+    csr_wr_cb[mip] = &this_class::write_null;
     csr_rd_cb[sip] = &this_class::read_ip;
-    csr_wr_cb[sip] = &this_class::write_ip;
+    csr_wr_cb[sip] = &this_class::write_null;
     csr_rd_cb[uip] = &this_class::read_ip;
-    csr_wr_cb[uip] = &this_class::write_ip;
+    csr_wr_cb[uip] = &this_class::write_null;
     csr_rd_cb[mie] = &this_class::read_ie;
     csr_wr_cb[mie] = &this_class::write_ie;
     csr_rd_cb[sie] = &this_class::read_ie;
@@ -457,16 +514,12 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
     csr_rd_cb[uie] = &this_class::read_ie;
     csr_wr_cb[uie] = &this_class::write_ie;
     csr_rd_cb[mhartid] = &this_class::read_hartid;
-    // common regs
-    const std::array<unsigned, 6> addrs{{mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
-    }
-    // read-only registers
-    csr_rd_cb[misa] = &this_class::read_reg;
-    csr_wr_cb[misa] = nullptr;
-    
+    csr_rd_cb[mcounteren] = &this_class::read_null;
+    csr_wr_cb[mcounteren] = &this_class::write_null;
+    csr_wr_cb[misa] = &this_class::write_null;
+    csr_wr_cb[mvendorid] = &this_class::write_null;
+    csr_wr_cb[marchid] = &this_class::write_null;
+    csr_wr_cb[mimpid] = &this_class::write_null;
     csr_rd_cb[satp] = &this_class::read_satp;
     csr_wr_cb[satp] = &this_class::write_satp;
     csr_rd_cb[fcsr] = &this_class::read_fcsr;
@@ -495,6 +548,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                 if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
             if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
             if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
+            auto entry = reader.get_entry();
             for (const auto pseg : reader.segments) {
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
                 const auto seg_data = pseg->get_data();
@@ -507,14 +561,35 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                                    << pseg->get_physical_address();
                 }
             }
-            for (const auto sec : reader.sections) {
-                if (sec->get_name() == ".tohost") {
+            for(const auto sec : reader.sections) {
+                if(sec->get_name() == ".symtab") {
+                    if ( SHT_SYMTAB == sec->get_type() ||
+                            SHT_DYNSYM == sec->get_type() ) {
+                        ELFIO::symbol_section_accessor symbols( reader, sec );
+                        auto sym_no = symbols.get_symbols_num();
+                        std::string   name;
+                        ELFIO::Elf64_Addr    value   = 0;
+                        ELFIO::Elf_Xword     size    = 0;
+                        unsigned char bind    = 0;
+                        unsigned char type    = 0;
+                        ELFIO::Elf_Half      section = 0;
+                        unsigned char other   = 0;
+                        for ( auto i = 0U; i < sym_no; ++i ) {
+                            symbols.get_symbol( i, name, value, size, bind, type, section, other );
+                            if(name=="tohost") {
+                                tohost = value;
+                            } else if(name=="fromhost") {
+                                fromhost = value;
+                            }
+                        }
+                    }
+                } else if (sec->get_name() == ".tohost") {
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
-            }
 
-            return std::make_pair(reader.get_entry(), true);
+            }
+            return std::make_pair(entry, true);
         }
         throw std::runtime_error("memory load file is not a valid elf file");
     }
@@ -536,13 +611,19 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
     try {
         switch (space) {
         case traits<BASE>::MEM: {
-            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
+            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
+                if(!is_debug(access)  && (addr&(alignment-1))){
+                    this->trap_state = 1<<31 | 4<<16;
+                    fault_data=addr;
+                    return iss::Err;
+                }
                 if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
                     if (vm.levels != 0) { // VM is active
@@ -557,10 +638,14 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                 auto res = type==iss::address_type::PHYSICAL?
                         read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
                         read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                if (unlikely(res != iss::Ok)){
+                	this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    fault_data=addr;
+                }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                 return iss::Err;
             }
         } break;
@@ -575,7 +660,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
             case 3: { // SFENCE:VMA upper
                 auto tvm = state.mstatus.TVM;
                 if (this->reg.PRIV == PRIV_S & tvm != 0) {
-                    this->reg.trap_state = (1 << 31) | (2 << 16);
+                    this->trap_state = (1 << 31) | (2 << 16);
                     this->fault_data = this->reg.PC;
                     return iss::Err;
                 }
@@ -596,7 +681,8 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
         return iss::Err;
     }
 }
@@ -633,7 +719,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
@@ -651,11 +737,14 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 auto res = type==iss::address_type::PHYSICAL?
                         write_mem(phys_addr_t{access, space, addr}, length, data):
                         write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok))
-                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
+                if (unlikely(res != iss::Ok)) {
+                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    fault_data=addr;
+                }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1 << 31) | ta.id;
+                fault_data=ta.addr;
                 return iss::Err;
             }
 
@@ -703,7 +792,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 ptw.clear();
                 auto tvm = state.mstatus.TVM;
                 if (this->reg.PRIV == PRIV_S & tvm != 0) {
-                    this->reg.trap_state = (1 << 31) | (2 << 16);
+                    this->trap_state = (1 << 31) | (2 << 16);
                     this->fault_data = this->reg.PC;
                     return iss::Err;
                 }
@@ -719,7 +808,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1 << 31) | ta.id;
+        fault_data=ta.addr;
         return iss::Err;
     }
 }
@@ -764,7 +854,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
+    auto cycle_val = this->icount + cycle_offset;
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
@@ -774,8 +864,50 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
+    if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if (addr == mcycleh)
+            return iss::Err;
+        mcycle_csr = static_cast<uint64_t>(val);
+    } else {
+        if (addr == mcycle) {
+            mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
+        } else  {
+            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
+        }
+    }
+    cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
+    if ((addr&0xff) == (minstret&0xff)) {
+        val = static_cast<reg_t>(this->reg.instret);
+    } else if ((addr&0xff) == (minstreth&0xff)) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
+        val = static_cast<reg_t>(this->reg.instret >> 32);
+    }
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
+    if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if ((addr&0xff) == (minstreth&0xff))
+            return iss::Err;
+        this->reg.instret = static_cast<uint64_t>(val);
+    } else {
+        if ((addr&0xff) == (minstret&0xff)) {
+            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
+        } else  {
+            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
+        }
+    }
+    this->reg.instret--;
+    return iss::Ok;
+}
+
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
+    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
@@ -785,6 +917,11 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned
     return iss::Ok;
 }
 
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
+    val = csr[addr] & ~2;
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_status(unsigned addr, reg_t &val) {
     auto req_priv_lvl = (addr >> 8) & 0x3;
     val = state.mstatus & hart_state_type::get_mask(req_priv_lvl);
@@ -799,6 +936,11 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsig
     return iss::Ok;
 }
 
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cause(unsigned addr, reg_t val) {
+    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
     val = csr[mie];
     if (addr < mie) val &= csr[mideleg];
@@ -826,19 +968,15 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned a
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    auto mask = get_irq_mask(req_priv_lvl);
-    mask &= ~(1 << 7); // MTIP is read only
-    csr[mip] = (csr[mip] & ~mask) | (val & mask);
-    check_interrupt();
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
+    csr[addr] = val & get_pc_mask();
     return iss::Ok;
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned addr, reg_t &val) {
     reg_t tvm = state.mstatus.TVM;
     if (this->reg.PRIV == PRIV_S & tvm != 0) {
-        this->reg.trap_state = (1 << 31) | (2 << 16);
+        this->trap_state = (1 << 31) | (2 << 16);
         this->fault_data = this->reg.PC;
         return iss::Err;
     }
@@ -849,7 +987,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigned addr, reg_t val) {
     reg_t tvm = state.mstatus.TVM;
     if (this->reg.PRIV == PRIV_S & tvm != 0) {
-        this->reg.trap_state = (1 << 31) | (2 << 16);
+        this->trap_state = (1 << 31) | (2 << 16);
         this->fault_data = this->reg.PC;
         return iss::Err;
     }
@@ -905,7 +1043,7 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
         const mem_type::page_type &p = mem(paddr.val / mem.page_size);
         uint64_t offs = paddr.val & mem.page_addr_mask;
         std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->reg.icount > 30000) data[3] |= 0x80;
+        if (this->icount > 30000) data[3] |= 0x80;
     } break;
     default: {
         for(auto offs=0U; offs<length; ++offs) {
@@ -918,7 +1056,6 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
 
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if ((paddr.val + length) > mem.size()) return iss::Err;
     if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
@@ -966,7 +1103,7 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
                             LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                       << "), stopping simulation";
                         }
-                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
+                        this->trap_state=std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim=hostvar;
                         break;
                         //throw(iss::simulation_stopped(hostvar));
@@ -1035,7 +1172,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
     if (enabled_interrupts != 0) {
         int res = 0;
         while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+        this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
 
@@ -1153,13 +1290,33 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
          * access, or page-fault exception occurs, mtval is written with the
          * faulting effective address.
          */
-        csr[utval | (new_priv << 8)] = cause==2?instr : fault_data;
+        switch(cause){
+        case 0:
+            csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
+            break;
+        case 2:
+            csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
+            break;
+        case 3:
+            //TODO: implement debug mode behavior
+            // csr[dpc] = addr;
+            // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
+            csr[utval | (new_priv << 8)] = addr;
+            break;
+        case 4:
+        case 6:
+        case 7:
+            csr[utval | (new_priv << 8)] = fault_data;
+            break;
+        default:
+            csr[utval | (new_priv << 8)] = 0;
+        }
         fault_data = 0;
     } else {
         if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
             new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S;
         csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
-        this->reg.pending_trap = 0;
+        this->pending_trap = 0;
     }
     size_t adr = ucause | (new_priv << 8);
     csr[adr] = (trap_id << 31) + cause;
@@ -1193,11 +1350,8 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     auto ivec = csr[utvec | (new_priv << 8)];
     // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
     // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x1UL;
+    this->reg.NEXT_PC = ivec & ~0x3UL;
     if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    // reset trap state
-    this->reg.PRIV = new_priv;
-    this->reg.trap_state = 0;
     std::array<char, 32> buffer;
     sprintf(buffer.data(), "0x%016lx", addr);
     if((flags&0xffffffff) != 0xffffffff)
@@ -1205,6 +1359,9 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
                        << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
                        << " at address " << buffer.data() << " occurred, changing privilege level from "
                        << lvl[cur_priv] << " to " << lvl[new_priv];
+    // reset trap state
+    this->reg.PRIV = new_priv;
+    this->trap_state = 0;
     update_vm_info();
     return this->reg.NEXT_PC;
 }
@@ -1216,7 +1373,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
 
     auto tsr = state.mstatus.TSR;
     if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) {
-        this->reg.trap_state = (1 << 31) | (2 << 16);
+        this->trap_state = (1 << 31) | (2 << 16);
         this->fault_data = this->reg.PC;
         return this->reg.PC;
     }
@@ -1228,15 +1385,18 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
         this->reg.PRIV = state.mstatus.MPP;
         state.mstatus.MPP = 0; // clear mpp to U mode
         state.mstatus.MIE = state.mstatus.MPIE;
+        state.mstatus.MPIE = 1;
         break;
     case PRIV_S:
         this->reg.PRIV = state.mstatus.SPP;
         state.mstatus.SPP = 0; // clear spp to U mode
         state.mstatus.SIE = state.mstatus.SPIE;
+        state.mstatus.SPIE = 1;
         break;
     case PRIV_U:
         this->reg.PRIV = 0;
         state.mstatus.UIE = state.mstatus.UPIE;
+        state.mstatus.UPIE = 1;
         break;
     }
     // sets the pc to the value stored in the x epc register.
@@ -1244,6 +1404,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
     CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
                        << lvl[this->reg.PRIV];
     update_vm_info();
+    check_interrupt();
     return this->reg.NEXT_PC;
 }
 
@@ -1251,7 +1412,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
     auto status = state.mstatus;
     auto tw = status.TW;
     if (this->reg.PRIV == PRIV_S && tw != 0) {
-        this->reg.trap_state = (1 << 31) | (2 << 16);
+        this->trap_state = (1 << 31) | (2 << 16);
         this->fault_data = this->reg.PC;
     }
 }

incl/iss/arch/tgc_c.h

@@ -47,23 +47,18 @@ template <> struct traits<tgc_c> {
 
     constexpr static char const* const core_type = "TGC_C";
     
-    static constexpr std::array<const char*, 35> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+    static constexpr std::array<const char*, 36> reg_names{
+        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
  
-    static constexpr std::array<const char*, 35> reg_aliases{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
+    static constexpr std::array<const char*, 36> reg_aliases{
+        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
     enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS,
-        TRAP_STATE=NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS
     };
 
     using reg_t = uint32_t;
@@ -76,11 +71,11 @@ template <> struct traits<tgc_c> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, 40> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}};
+    static constexpr std::array<const uint32_t, 36> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32}};
 
-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}};
+    static constexpr std::array<const uint32_t, 36> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
@@ -133,50 +128,52 @@ template <> struct traits<tgc_c> {
         SRET = 41,
         MRET = 42,
         WFI = 43,
-        CSRRW = 44,
-        CSRRS = 45,
-        CSRRC = 46,
-        CSRRWI = 47,
-        CSRRSI = 48,
-        CSRRCI = 49,
-        MUL = 50,
-        MULH = 51,
-        MULHSU = 52,
-        MULHU = 53,
-        DIV = 54,
-        DIVU = 55,
-        REM = 56,
-        REMU = 57,
-        CADDI4SPN = 58,
-        CLW = 59,
-        CSW = 60,
-        CADDI = 61,
-        CNOP = 62,
-        CJAL = 63,
-        CLI = 64,
-        CLUI = 65,
-        CADDI16SP = 66,
-        __reserved_clui = 67,
-        CSRLI = 68,
-        CSRAI = 69,
-        CANDI = 70,
-        CSUB = 71,
-        CXOR = 72,
-        COR = 73,
-        CAND = 74,
-        CJ = 75,
-        CBEQZ = 76,
-        CBNEZ = 77,
-        CSLLI = 78,
-        CLWSP = 79,
-        CMV = 80,
-        CJR = 81,
-        __reserved_cmv = 82,
-        CADD = 83,
-        CJALR = 84,
-        CEBREAK = 85,
-        CSWSP = 86,
-        DII = 87,
+        DRET = 44,
+        CSRRW = 45,
+        CSRRS = 46,
+        CSRRC = 47,
+        CSRRWI = 48,
+        CSRRSI = 49,
+        CSRRCI = 50,
+        FENCE_I = 51,
+        MUL = 52,
+        MULH = 53,
+        MULHSU = 54,
+        MULHU = 55,
+        DIV = 56,
+        DIVU = 57,
+        REM = 58,
+        REMU = 59,
+        CADDI4SPN = 60,
+        CLW = 61,
+        CSW = 62,
+        CADDI = 63,
+        CNOP = 64,
+        CJAL = 65,
+        CLI = 66,
+        CLUI = 67,
+        CADDI16SP = 68,
+        __reserved_clui = 69,
+        CSRLI = 70,
+        CSRAI = 71,
+        CANDI = 72,
+        CSUB = 73,
+        CXOR = 74,
+        COR = 75,
+        CAND = 76,
+        CJ = 77,
+        CBEQZ = 78,
+        CBNEZ = 79,
+        CSLLI = 80,
+        CLWSP = 81,
+        CMV = 82,
+        CJR = 83,
+        __reserved_cmv = 84,
+        CADD = 85,
+        CJALR = 86,
+        CEBREAK = 87,
+        CSWSP = 88,
+        DII = 89,
         MAX_OPCODE
     };
 };
@@ -194,16 +191,8 @@ struct tgc_c: public arch_if {
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
-    inline uint64_t get_icount() { return reg.icount; }
+    inline uint64_t get_icount() { return icount; }
 
     inline bool should_stop() { return interrupt_sim; }
 
@@ -221,9 +210,9 @@ struct tgc_c: public arch_if {
 
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
 
-    inline uint32_t get_last_branch() { return reg.last_branch; }
+    inline uint32_t get_last_branch() { return last_branch; }
+
 
-protected:
 #pragma pack(push, 1)
     struct TGC_C_regs { 
         uint32_t X0 = 0; 
@@ -260,14 +249,16 @@ protected:
         uint32_t X31 = 0; 
         uint32_t PC = 0; 
         uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0;
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t last_branch;
+        uint8_t PRIV = 0; 
+        uint32_t DPC = 0;
     } reg;
 #pragma pack(pop)
+    uint32_t trap_state = 0, pending_trap = 0;
+    uint64_t icount = 0;
+    uint64_t cycle = 0;
+    uint64_t instret = 0;
+    uint32_t instruction = 0;
+    uint32_t last_branch = 0;
     std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;

incl/iss/arch/tgc_mapper.h

@@ -0,0 +1,43 @@
+#ifndef _ISS_ARCH_TGC_MAPPER_H
+#define _ISS_ARCH_TGC_MAPPER_H
+
+#include "riscv_hart_m_p.h"
+#include "tgc_c.h"
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_B
+#include "riscv_hart_m_p.h"
+#include "tgc_b.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#endif
+#ifdef CORE_TGC_C_XRB_NN
+#include "riscv_hart_m_p.h"
+#include "tgc_c_xrb_nn.h"
+using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
+#endif
+#ifdef CORE_TGC_D
+#include "riscv_hart_mu_p.h"
+#include "tgc_d.h"
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+#include "riscv_hart_mu_p.h"
+#include "tgc_d_xrb_mac.h"
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+#include "riscv_hart_mu_p.h"
+#include "tgc_d_xrb_nn.h"
+using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_E
+#include "riscv_hart_mu_p.h"
+#include "tgc_e.h"
+using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_X
+#include "riscv_hart_mu_p.h"
+#include "tgc_x.h"
+using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+#endif
+
+#endif

incl/iss/debugger/riscv_target_adapter.h

@@ -214,12 +214,26 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg=arch::traits<ARCH>::X0;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
+    bool e_ext = arch::traits<ARCH>::PC<32;
     for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
-        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
-        std::copy(iter, iter + reg_width, reg_base);
-        iter += 4;
-        reg_base += offset;
+        if(e_ext && reg_no>15){
+            if(reg_no==32){
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+                std::copy(iter, iter + reg_width, reg_base);
+            } else {
+                const uint64_t zero_val=0;
+                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+                auto iter = (uint8_t*)&zero_val;
+                std::copy(iter, iter + reg_width, reg_base);
+            }
+        } else {
+            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            std::copy(iter, iter + reg_width, reg_base);
+            iter += 4;
+            reg_base += offset;
+        }
     }
     return Ok;
 }

incl/iss/plugin/cycle_estimate.h

@@ -37,9 +37,9 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
-#include <json/json.h>
 #include <string>
 #include <unordered_map>
+#include <vector>
 
 namespace iss {
 
@@ -49,11 +49,13 @@ class cycle_estimate: public iss::vm_plugin {
 	BEGIN_BF_DECL(instr_desc, uint32_t)
 		BF_FIELD(taken, 24, 8)
 		BF_FIELD(not_taken, 16, 8)
-		BF_FIELD(size, 0, 16)
-		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
+        BF_FIELD(is_branch, 8, 8)
+        BF_FIELD(size, 0, 8)
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
 			this->size=size;
 			this->taken=taken;
 			this->not_taken=not_taken;
+			this->is_branch=branch;
 		}
 	END_BF_DECL();
 
@@ -64,7 +66,7 @@ public:
 
     cycle_estimate(const cycle_estimate &&) = delete;
 
-    cycle_estimate(std::string config_file_name);
+    cycle_estimate(std::string const& config_file_name);
 
     virtual ~cycle_estimate();
 
@@ -79,7 +81,7 @@ public:
     void callback(instr_info_t instr_info, exec_info const&) override;
 
 private:
-    iss::instrumentation_if *arch_instr;
+    iss::instrumentation_if *instr_if;
     std::vector<instr_desc> delays;
     struct pair_hash {
         size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
@@ -88,7 +90,7 @@ private:
         }
     };
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
-    Json::Value root;
+    std::string config_file_name;
 };
 }
 }

incl/iss/plugin/pctrace.h

@@ -0,0 +1,102 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#ifndef _ISS_PLUGIN_COV_H_
+#define _ISS_PLUGIN_COV_H_
+
+#include <iss/vm_plugin.h>
+#include "iss/instrumentation_if.h"
+#include <json/json.h>
+#include <string>
+#include <fstream>
+
+
+namespace iss {
+namespace plugin {
+class lz4compress_steambuf;
+class cov : public iss::vm_plugin {
+    struct instr_delay {
+        std::string instr_name;
+        size_t size;
+        size_t not_taken_delay;
+        size_t taken_delay;
+    };
+    BEGIN_BF_DECL(instr_desc, uint32_t)
+        BF_FIELD(taken, 24, 8)
+        BF_FIELD(not_taken, 16, 8)
+        BF_FIELD(is_branch, 8, 8)
+        BF_FIELD(size, 0, 8)
+        instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
+            this->size=size;
+            this->taken=taken;
+            this->not_taken=not_taken;
+            this->is_branch=branch;
+        }
+    END_BF_DECL();
+
+public:
+
+    cov(const cov &) = delete;
+
+    cov(const cov &&) = delete;
+
+    cov(std::string const &);
+
+    virtual ~cov();
+
+    cov &operator=(const cov &) = delete;
+
+    cov &operator=(const cov &&) = delete;
+
+    bool registration(const char *const version, vm_if &arch) override;
+
+    sync_type get_sync() override { return POST_SYNC; };
+
+    void callback(instr_info_t, exec_info const&) override;
+
+private:
+    iss::instrumentation_if *instr_if  {nullptr};
+    std::ofstream output;
+#ifdef WITH_LZ4
+    std::unique_ptr<lz4compress_steambuf> strbuf;
+    std::ostream ostr;
+#endif
+    std::string filename;
+    std::vector<instr_desc> delays;
+    bool jumped{false}, first{true};
+};
+}
+}
+
+#endif /* _ISS_PLUGIN_COV_H_ */

incl/sysc/core_complex.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017-2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,24 +30,27 @@
  *
  *******************************************************************************/
 
-#ifndef _SYSC_SIFIVE_FE310_H_
-#define _SYSC_SIFIVE_FE310_H_
+#ifndef _SYSC_CORE_COMPLEX_H_
+#define _SYSC_CORE_COMPLEX_H_
 
-#include "tlm/scc/initiator_mixin.h"
-#include "scc/traceable.h"
-#include "scc/utilities.h"
-#include "tlm/scc/scv/tlm_rec_initiator_socket.h"
+#include <tlm/scc/initiator_mixin.h>
+#include <scc/traceable.h>
+#include <scc/tick2time.h>
+#include <scc/utilities.h>
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#ifdef CWR_SYSTEMC
+#include <scmlinc/scml_property.h>
+#else
 #include <cci_configuration>
+#endif
 #include <tlm>
-#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
+#include <memory>
 
-class scv_tr_db;
-class scv_tr_stream;
-struct _scv_tr_generator_default_data;
-template <class T_begin, class T_end> class scv_tr_generator;
-
+namespace iss {
+    class vm_plugin;
+}
 namespace sysc {
 
 class tlm_dmi_ext : public tlm::tlm_dmi {
@@ -62,13 +65,12 @@ public:
 
 namespace tgfs {
 class core_wrapper;
+struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
     tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
 
-    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
-
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
     sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
@@ -79,6 +81,9 @@ public:
 
     sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
 
+#ifndef CWR_SYSTEMC
+	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+
     sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
@@ -97,7 +102,51 @@ public:
 
     cci::cci_param<uint32_t> mhartid{"mhartid", 0};
 
-    core_complex(sc_core::sc_module_name name);
+    cci::cci_param<std::string> plugins{"plugins", ""};
+
+    core_complex(sc_core::sc_module_name const& name);
+
+#else
+	sc_core::sc_in<bool> clk_i{"clk_i"};
+
+	sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
+
+	scml_property<std::string> elf_file{"elf_file", ""};
+
+    scml_property<bool> enable_disass{"enable_disass", false};
+
+    scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
+
+    scml_property<std::string> core_type{"core_type", "tgc_c"};
+
+    scml_property<std::string> backend{"backend", "interp"};
+
+    scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
+
+    scml_property<bool> dump_ir{"dump_ir", false};
+
+    scml_property<uint32_t> mhartid{"mhartid", 0};
+
+    scml_property<std::string> plugins{"plugins", ""};
+
+    core_complex(sc_core::sc_module_name const& name)
+    : sc_module(name)
+    , local_irq_i{"local_irq_i", 16}
+    , elf_file{"elf_file", ""}
+    , enable_disass{"enable_disass", false}
+    , reset_address{"reset_address", 0ULL}
+    , core_type{"core_type", "tgc_c"}
+    , backend{"backend", "interp"}
+    , gdb_server_port{"gdb_server_port", 0}
+    , dump_ir{"dump_ir", false}
+    , mhartid{"mhartid", 0}
+    , read_lut(tlm_dmi_ext())
+    , write_lut(tlm_dmi_ext())
+    {
+    	init();
+    }
+
+#endif
 
     ~core_complex();
 
@@ -121,13 +170,14 @@ public:
 
     void trace(sc_core::sc_trace_file *trf) const override;
 
-    void disass_output(uint64_t pc, const std::string instr);
+    bool disass_output(uint64_t pc, const std::string instr);
 
+    void set_clock_period(sc_core::sc_time period);
 protected:
     void before_end_of_elaboration() override;
     void start_of_simulation() override;
+	void forward();
     void run();
-    void clk_cb();
     void rst_cb();
     void sw_irq_cb();
     void timer_irq_cb();
@@ -136,21 +186,16 @@ protected:
     util::range_lut<tlm_dmi_ext> read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;
     std::vector<uint8_t> write_buf;
-    std::unique_ptr<core_wrapper> cpu;
-    sc_core::sc_time curr_clk;
-#ifdef WITH_SCV
-    //! transaction recording database
-    scv_tr_db *m_db;
-    //! blocking transaction recording stream handle
-    scv_tr_stream *stream_handle;
-    //! transaction generator handle for blocking transactions
-    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
-    scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
-    scv_tr_handle tr_handle;
-#endif
-};
+    core_wrapper* cpu{nullptr};
+    sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    core_trace* trc{nullptr};
+    std::unique_ptr<scc::tick2time> t2t;
+private:
+    void init();
+    std::vector<iss::vm_plugin *> plugin_list;
 
+};
 } /* namespace SiFive */
 } /* namespace sysc */
 
-#endif /* _SYSC_SIFIVE_FE310_H_ */
+#endif /* _SYSC_CORE_COMPLEX_H_ */

softfloat/build/Linux-x86_64-GCC/platform.h

@@ -49,7 +49,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
+#ifdef __GNUC__
 #define SOFTFLOAT_BUILTIN_CLZ 1
 #define SOFTFLOAT_INTRINSIC_INT128 1
+#endif
 #include "opts-GCC.h"
 

src/iss/tgc_c.cpp

@@ -39,24 +39,24 @@
 
 using namespace iss::arch;
 
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 35>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
+constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
-tgc_c::tgc_c() {
-    reg.icount = 0;
-}
+tgc_c::tgc_c()  = default;
 
 tgc_c::~tgc_c() = default;
 
 void tgc_c::reset(uint64_t address) {
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
+    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+        *(base_ptr+i)=0;
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
+    trap_state=0;
+    icount=0;
 }
 
 uint8_t *tgc_c::get_regs_base_ptr() {

src/main.cpp

@@ -35,26 +35,18 @@
 
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
-#include <iss/arch/riscv_hart_m_p.h>
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_B
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_b.h"
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#endif
-#ifdef CORE_TGC_D
-#include "iss/arch/riscv_hart_mu_p.h"
-#include "iss/arch/tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
-#endif
+#include <iss/arch/tgc_mapper.h>
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
 #endif
 #include <iss/log_categories.h>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
+#include <iss/plugin/pctrace.h>
+#include <iss/plugin/loader.h>
+#if defined(HAS_LUA)
+#include <iss/plugin/lua.h>
+#endif
 
 namespace po = boost::program_options;
 
@@ -68,17 +60,17 @@ int main(int argc, char *argv[]) {
     desc.add_options()
         ("help,h", "Print help message")
         ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
-        ("logfile,f", po::value<std::string>(), "Sets default log file.")
+        ("logfile,l", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
         ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
         ("reset,r", po::value<std::string>(), "reset address")
         ("dump-ir", "dump the intermediate representation")
-        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
+        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
         ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
-        ("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
     try {
@@ -123,24 +115,48 @@ int main(int argc, char *argv[]) {
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgf_c") {
+        if (isa_opt == "tgc_c") {
             std::tie(cpu, vm) =
                 iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else
 #ifdef CORE_TGC_B
-        if (isa_opt == "tgf_b") {
+        if (isa_opt == "tgc_b") {
             std::tie(cpu, vm) =
                 iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else
 #endif
+#ifdef CORE_TGC_C_XRB_NN
+        if (isa_opt == "tgc_c_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
 #ifdef CORE_TGC_D
-        if (isa_opt == "tgf_d") {
+        if (isa_opt == "tgc_d") {
             std::tie(cpu, vm) =
                 iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+        if (isa_opt == "tgc_d_xrb_mac") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        if (isa_opt == "tgc_d_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_E
+        if (isa_opt == "tgc_e") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
 #endif
         {
-            LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+            LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
             return 127;
         }
         if (clim.count("plugin")) {
@@ -160,9 +176,21 @@ int main(int argc, char *argv[]) {
                     auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
                     vm->register_plugin(*ce_plugin);
                     plugin_list.push_back(ce_plugin);
-                } else {
-                    LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
-                    return 127;
+                } else if (plugin_name == "pctrace") {
+                    auto *plugin = new iss::plugin::cov(filename);
+                    vm->register_plugin(*plugin);
+                    plugin_list.push_back(plugin);
+               } else {
+                    std::array<char const*, 1> a{{filename.c_str()}};
+                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                    if(plugin){
+                        vm->register_plugin(*plugin);
+                        plugin_list.push_back(plugin);
+                    } else {
+                        LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+                        return 127;
+                    }
                 }
             }
         }
@@ -196,7 +224,7 @@ int main(int argc, char *argv[]) {
         auto cycles = clim["instructions"].as<uint64_t>();
         res = vm->start(cycles, dump);
     } catch (std::exception &e) {
-        LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
+        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
                    << std::endl;
         res = 2;
     }

src/plugin/GCOV.cpp

@@ -1,821 +0,0 @@
-//===- GCOV.cpp - LLVM coverage tool --------------------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// GCOV implements the interface to read and write coverage files that use
-// 'gcov' format.
-//
-//===----------------------------------------------------------------------===//
-
-#include "GCOV.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/FileSystem.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/Path.h"
-#include "llvm/Support/raw_ostream.h"
-#include <algorithm>
-#include <system_error>
-
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// GCOVFile implementation.
-
-/// readGCNO - Read GCNO buffer.
-bool GCOVFile::readGCNO(GCOVBuffer &Buffer) {
-  if (!Buffer.readGCNOFormat())
-    return false;
-  if (!Buffer.readGCOVVersion(Version))
-    return false;
-
-  if (!Buffer.readInt(Checksum))
-    return false;
-  while (true) {
-    if (!Buffer.readFunctionTag())
-      break;
-    auto GFun = make_unique<GCOVFunction>(*this);
-    if (!GFun->readGCNO(Buffer, Version))
-      return false;
-    Functions.push_back(std::move(GFun));
-  }
-
-  GCNOInitialized = true;
-  return true;
-}
-
-/// readGCDA - Read GCDA buffer. It is required that readGCDA() can only be
-/// called after readGCNO().
-bool GCOVFile::readGCDA(GCOVBuffer &Buffer) {
-  assert(GCNOInitialized && "readGCDA() can only be called after readGCNO()");
-  if (!Buffer.readGCDAFormat())
-    return false;
-  GCOV::GCOVVersion GCDAVersion;
-  if (!Buffer.readGCOVVersion(GCDAVersion))
-    return false;
-  if (Version != GCDAVersion) {
-    errs() << "GCOV versions do not match.\n";
-    return false;
-  }
-
-  uint32_t GCDAChecksum;
-  if (!Buffer.readInt(GCDAChecksum))
-    return false;
-  if (Checksum != GCDAChecksum) {
-    errs() << "File checksums do not match: " << Checksum
-           << " != " << GCDAChecksum << ".\n";
-    return false;
-  }
-  for (size_t i = 0, e = Functions.size(); i < e; ++i) {
-    if (!Buffer.readFunctionTag()) {
-      errs() << "Unexpected number of functions.\n";
-      return false;
-    }
-    if (!Functions[i]->readGCDA(Buffer, Version))
-      return false;
-  }
-  if (Buffer.readObjectTag()) {
-    uint32_t Length;
-    uint32_t Dummy;
-    if (!Buffer.readInt(Length))
-      return false;
-    if (!Buffer.readInt(Dummy))
-      return false; // checksum
-    if (!Buffer.readInt(Dummy))
-      return false; // num
-    if (!Buffer.readInt(RunCount))
-      return false;
-    Buffer.advanceCursor(Length - 3);
-  }
-  while (Buffer.readProgramTag()) {
-    uint32_t Length;
-    if (!Buffer.readInt(Length))
-      return false;
-    Buffer.advanceCursor(Length);
-    ++ProgramCount;
-  }
-
-  return true;
-}
-
-void GCOVFile::print(raw_ostream &OS) const {
-  for (const auto &FPtr : Functions)
-    FPtr->print(OS);
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVFile content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVFile::dump() const {
-  print(dbgs());
-}
-#endif
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVFile::collectLineCounts(FileInfo &FI) {
-  for (const auto &FPtr : Functions)
-    FPtr->collectLineCounts(FI);
-  FI.setRunCount(RunCount);
-  FI.setProgramCount(ProgramCount);
-}
-
-//===----------------------------------------------------------------------===//
-// GCOVFunction implementation.
-
-/// readGCNO - Read a function from the GCNO buffer. Return false if an error
-/// occurs.
-bool GCOVFunction::readGCNO(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
-  uint32_t Dummy;
-  if (!Buff.readInt(Dummy))
-    return false; // Function header length
-  if (!Buff.readInt(Ident))
-    return false;
-  if (!Buff.readInt(Checksum))
-    return false;
-  if (Version != GCOV::V402) {
-    uint32_t CfgChecksum;
-    if (!Buff.readInt(CfgChecksum))
-      return false;
-    if (Parent.getChecksum() != CfgChecksum) {
-      errs() << "File checksums do not match: " << Parent.getChecksum()
-             << " != " << CfgChecksum << " in (" << Name << ").\n";
-      return false;
-    }
-  }
-  if (!Buff.readString(Name))
-    return false;
-  if (!Buff.readString(Filename))
-    return false;
-  if (!Buff.readInt(LineNumber))
-    return false;
-
-  // read blocks.
-  if (!Buff.readBlockTag()) {
-    errs() << "Block tag not found.\n";
-    return false;
-  }
-  uint32_t BlockCount;
-  if (!Buff.readInt(BlockCount))
-    return false;
-  for (uint32_t i = 0, e = BlockCount; i != e; ++i) {
-    if (!Buff.readInt(Dummy))
-      return false; // Block flags;
-    Blocks.push_back(make_unique<GCOVBlock>(*this, i));
-  }
-
-  // read edges.
-  while (Buff.readEdgeTag()) {
-    uint32_t EdgeCount;
-    if (!Buff.readInt(EdgeCount))
-      return false;
-    EdgeCount = (EdgeCount - 1) / 2;
-    uint32_t BlockNo;
-    if (!Buff.readInt(BlockNo))
-      return false;
-    if (BlockNo >= BlockCount) {
-      errs() << "Unexpected block number: " << BlockNo << " (in " << Name
-             << ").\n";
-      return false;
-    }
-    for (uint32_t i = 0, e = EdgeCount; i != e; ++i) {
-      uint32_t Dst;
-      if (!Buff.readInt(Dst))
-        return false;
-      Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst]));
-      GCOVEdge *Edge = Edges.back().get();
-      Blocks[BlockNo]->addDstEdge(Edge);
-      Blocks[Dst]->addSrcEdge(Edge);
-      if (!Buff.readInt(Dummy))
-        return false; // Edge flag
-    }
-  }
-
-  // read line table.
-  while (Buff.readLineTag()) {
-    uint32_t LineTableLength;
-    // Read the length of this line table.
-    if (!Buff.readInt(LineTableLength))
-      return false;
-    uint32_t EndPos = Buff.getCursor() + LineTableLength * 4;
-    uint32_t BlockNo;
-    // Read the block number this table is associated with.
-    if (!Buff.readInt(BlockNo))
-      return false;
-    if (BlockNo >= BlockCount) {
-      errs() << "Unexpected block number: " << BlockNo << " (in " << Name
-             << ").\n";
-      return false;
-    }
-    GCOVBlock &Block = *Blocks[BlockNo];
-    // Read the word that pads the beginning of the line table. This may be a
-    // flag of some sort, but seems to always be zero.
-    if (!Buff.readInt(Dummy))
-      return false;
-
-    // Line information starts here and continues up until the last word.
-    if (Buff.getCursor() != (EndPos - sizeof(uint32_t))) {
-      StringRef F;
-      // Read the source file name.
-      if (!Buff.readString(F))
-        return false;
-      if (Filename != F) {
-        errs() << "Multiple sources for a single basic block: " << Filename
-               << " != " << F << " (in " << Name << ").\n";
-        return false;
-      }
-      // Read lines up to, but not including, the null terminator.
-      while (Buff.getCursor() < (EndPos - 2 * sizeof(uint32_t))) {
-        uint32_t Line;
-        if (!Buff.readInt(Line))
-          return false;
-        // Line 0 means this instruction was injected by the compiler. Skip it.
-        if (!Line)
-          continue;
-        Block.addLine(Line);
-      }
-      // Read the null terminator.
-      if (!Buff.readInt(Dummy))
-        return false;
-    }
-    // The last word is either a flag or padding, it isn't clear which. Skip
-    // over it.
-    if (!Buff.readInt(Dummy))
-      return false;
-  }
-  return true;
-}
-
-/// readGCDA - Read a function from the GCDA buffer. Return false if an error
-/// occurs.
-bool GCOVFunction::readGCDA(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
-  uint32_t HeaderLength;
-  if (!Buff.readInt(HeaderLength))
-    return false; // Function header length
-
-  uint64_t EndPos = Buff.getCursor() + HeaderLength * sizeof(uint32_t);
-
-  uint32_t GCDAIdent;
-  if (!Buff.readInt(GCDAIdent))
-    return false;
-  if (Ident != GCDAIdent) {
-    errs() << "Function identifiers do not match: " << Ident
-           << " != " << GCDAIdent << " (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t GCDAChecksum;
-  if (!Buff.readInt(GCDAChecksum))
-    return false;
-  if (Checksum != GCDAChecksum) {
-    errs() << "Function checksums do not match: " << Checksum
-           << " != " << GCDAChecksum << " (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t CfgChecksum;
-  if (Version != GCOV::V402) {
-    if (!Buff.readInt(CfgChecksum))
-      return false;
-    if (Parent.getChecksum() != CfgChecksum) {
-      errs() << "File checksums do not match: " << Parent.getChecksum()
-             << " != " << CfgChecksum << " (in " << Name << ").\n";
-      return false;
-    }
-  }
-
-  if (Buff.getCursor() < EndPos) {
-    StringRef GCDAName;
-    if (!Buff.readString(GCDAName))
-      return false;
-    if (Name != GCDAName) {
-      errs() << "Function names do not match: " << Name << " != " << GCDAName
-             << ".\n";
-      return false;
-    }
-  }
-
-  if (!Buff.readArcTag()) {
-    errs() << "Arc tag not found (in " << Name << ").\n";
-    return false;
-  }
-
-  uint32_t Count;
-  if (!Buff.readInt(Count))
-    return false;
-  Count /= 2;
-
-  // This for loop adds the counts for each block. A second nested loop is
-  // required to combine the edge counts that are contained in the GCDA file.
-  for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) {
-    // The last block is always reserved for exit block
-    if (BlockNo >= Blocks.size()) {
-      errs() << "Unexpected number of edges (in " << Name << ").\n";
-      return false;
-    }
-    if (BlockNo == Blocks.size() - 1)
-      errs() << "(" << Name << ") has arcs from exit block.\n";
-    GCOVBlock &Block = *Blocks[BlockNo];
-    for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End;
-         ++EdgeNo) {
-      if (Count == 0) {
-        errs() << "Unexpected number of edges (in " << Name << ").\n";
-        return false;
-      }
-      uint64_t ArcCount;
-      if (!Buff.readInt64(ArcCount))
-        return false;
-      Block.addCount(EdgeNo, ArcCount);
-      --Count;
-    }
-    Block.sortDstEdges();
-  }
-  return true;
-}
-
-/// getEntryCount - Get the number of times the function was called by
-/// retrieving the entry block's count.
-uint64_t GCOVFunction::getEntryCount() const {
-  return Blocks.front()->getCount();
-}
-
-/// getExitCount - Get the number of times the function returned by retrieving
-/// the exit block's count.
-uint64_t GCOVFunction::getExitCount() const {
-  return Blocks.back()->getCount();
-}
-
-void GCOVFunction::print(raw_ostream &OS) const {
-  OS << "===== " << Name << " (" << Ident << ") @ " << Filename << ":"
-     << LineNumber << "\n";
-  for (const auto &Block : Blocks)
-    Block->print(OS);
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVFunction content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVFunction::dump() const {
-  print(dbgs());
-}
-#endif
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVFunction::collectLineCounts(FileInfo &FI) {
-  // If the line number is zero, this is a function that doesn't actually appear
-  // in the source file, so there isn't anything we can do with it.
-  if (LineNumber == 0)
-    return;
-
-  for (const auto &Block : Blocks)
-    Block->collectLineCounts(FI);
-  FI.addFunctionLine(Filename, LineNumber, this);
-}
-
-//===----------------------------------------------------------------------===//
-// GCOVBlock implementation.
-
-/// ~GCOVBlock - Delete GCOVBlock and its content.
-GCOVBlock::~GCOVBlock() {
-  SrcEdges.clear();
-  DstEdges.clear();
-  Lines.clear();
-}
-
-/// addCount - Add to block counter while storing the edge count. If the
-/// destination has no outgoing edges, also update that block's count too.
-void GCOVBlock::addCount(size_t DstEdgeNo, uint64_t N) {
-  assert(DstEdgeNo < DstEdges.size()); // up to caller to ensure EdgeNo is valid
-  DstEdges[DstEdgeNo]->Count = N;
-  Counter += N;
-  if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges())
-    DstEdges[DstEdgeNo]->Dst.Counter += N;
-}
-
-/// sortDstEdges - Sort destination edges by block number, nop if already
-/// sorted. This is required for printing branch info in the correct order.
-void GCOVBlock::sortDstEdges() {
-  if (!DstEdgesAreSorted) {
-    SortDstEdgesFunctor SortEdges;
-    std::stable_sort(DstEdges.begin(), DstEdges.end(), SortEdges);
-  }
-}
-
-/// collectLineCounts - Collect line counts. This must be used after
-/// reading .gcno and .gcda files.
-void GCOVBlock::collectLineCounts(FileInfo &FI) {
-  for (uint32_t N : Lines)
-    FI.addBlockLine(Parent.getFilename(), N, this);
-}
-
-void GCOVBlock::print(raw_ostream &OS) const {
-  OS << "Block : " << Number << " Counter : " << Counter << "\n";
-  if (!SrcEdges.empty()) {
-    OS << "\tSource Edges : ";
-    for (const GCOVEdge *Edge : SrcEdges)
-      OS << Edge->Src.Number << " (" << Edge->Count << "), ";
-    OS << "\n";
-  }
-  if (!DstEdges.empty()) {
-    OS << "\tDestination Edges : ";
-    for (const GCOVEdge *Edge : DstEdges)
-      OS << Edge->Dst.Number << " (" << Edge->Count << "), ";
-    OS << "\n";
-  }
-  if (!Lines.empty()) {
-    OS << "\tLines : ";
-    for (uint32_t N : Lines)
-      OS << (N) << ",";
-    OS << "\n";
-  }
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-/// dump - Dump GCOVBlock content to dbgs() for debugging purposes.
-LLVM_DUMP_METHOD void GCOVBlock::dump() const {
-  print(dbgs());
-}
-#endif
-
-//===----------------------------------------------------------------------===//
-// FileInfo implementation.
-
-// Safe integer division, returns 0 if numerator is 0.
-static uint32_t safeDiv(uint64_t Numerator, uint64_t Divisor) {
-  if (!Numerator)
-    return 0;
-  return Numerator / Divisor;
-}
-
-// This custom division function mimics gcov's branch ouputs:
-//   - Round to closest whole number
-//   - Only output 0% or 100% if it's exactly that value
-static uint32_t branchDiv(uint64_t Numerator, uint64_t Divisor) {
-  if (!Numerator)
-    return 0;
-  if (Numerator == Divisor)
-    return 100;
-
-  uint8_t Res = (Numerator * 100 + Divisor / 2) / Divisor;
-  if (Res == 0)
-    return 1;
-  if (Res == 100)
-    return 99;
-  return Res;
-}
-
-namespace {
-struct formatBranchInfo {
-  formatBranchInfo(const GCOV::Options &Options, uint64_t Count, uint64_t Total)
-      : Options(Options), Count(Count), Total(Total) {}
-
-  void print(raw_ostream &OS) const {
-    if (!Total)
-      OS << "never executed";
-    else if (Options.BranchCount)
-      OS << "taken " << Count;
-    else
-      OS << "taken " << branchDiv(Count, Total) << "%";
-  }
-
-  const GCOV::Options &Options;
-  uint64_t Count;
-  uint64_t Total;
-};
-
-static raw_ostream &operator<<(raw_ostream &OS, const formatBranchInfo &FBI) {
-  FBI.print(OS);
-  return OS;
-}
-
-class LineConsumer {
-  std::unique_ptr<MemoryBuffer> Buffer;
-  StringRef Remaining;
-
-public:
-  LineConsumer(StringRef Filename) {
-    ErrorOr<std::unique_ptr<MemoryBuffer>> BufferOrErr =
-        MemoryBuffer::getFileOrSTDIN(Filename);
-    if (std::error_code EC = BufferOrErr.getError()) {
-      errs() << Filename << ": " << EC.message() << "\n";
-      Remaining = "";
-    } else {
-      Buffer = std::move(BufferOrErr.get());
-      Remaining = Buffer->getBuffer();
-    }
-  }
-  bool empty() { return Remaining.empty(); }
-  void printNext(raw_ostream &OS, uint32_t LineNum) {
-    StringRef Line;
-    if (empty())
-      Line = "/*EOF*/";
-    else
-      std::tie(Line, Remaining) = Remaining.split("\n");
-    OS << format("%5u:", LineNum) << Line << "\n";
-  }
-};
-} // end anonymous namespace
-
-/// Convert a path to a gcov filename. If PreservePaths is true, this
-/// translates "/" to "#", ".." to "^", and drops ".", to match gcov.
-static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) {
-  if (!PreservePaths)
-    return sys::path::filename(Filename).str();
-
-  // This behaviour is defined by gcov in terms of text replacements, so it's
-  // not likely to do anything useful on filesystems with different textual
-  // conventions.
-  llvm::SmallString<256> Result("");
-  StringRef::iterator I, S, E;
-  for (I = S = Filename.begin(), E = Filename.end(); I != E; ++I) {
-    if (*I != '/')
-      continue;
-
-    if (I - S == 1 && *S == '.') {
-      // ".", the current directory, is skipped.
-    } else if (I - S == 2 && *S == '.' && *(S + 1) == '.') {
-      // "..", the parent directory, is replaced with "^".
-      Result.append("^#");
-    } else {
-      if (S < I)
-        // Leave other components intact,
-        Result.append(S, I);
-      // And separate with "#".
-      Result.push_back('#');
-    }
-    S = I + 1;
-  }
-
-  if (S < I)
-    Result.append(S, I);
-  return Result.str();
-}
-
-std::string FileInfo::getCoveragePath(StringRef Filename,
-                                      StringRef MainFilename) {
-  if (Options.NoOutput)
-    // This is probably a bug in gcov, but when -n is specified, paths aren't
-    // mangled at all, and the -l and -p options are ignored. Here, we do the
-    // same.
-    return Filename;
-
-  std::string CoveragePath;
-  if (Options.LongFileNames && !Filename.equals(MainFilename))
-    CoveragePath =
-        mangleCoveragePath(MainFilename, Options.PreservePaths) + "##";
-  CoveragePath += mangleCoveragePath(Filename, Options.PreservePaths) + ".gcov";
-  return CoveragePath;
-}
-
-std::unique_ptr<raw_ostream>
-FileInfo::openCoveragePath(StringRef CoveragePath) {
-  if (Options.NoOutput)
-    return llvm::make_unique<raw_null_ostream>();
-
-  std::error_code EC;
-  auto OS = llvm::make_unique<raw_fd_ostream>(CoveragePath, EC,
-                                              sys::fs::F_Text);
-  if (EC) {
-    errs() << EC.message() << "\n";
-    return llvm::make_unique<raw_null_ostream>();
-  }
-  return std::move(OS);
-}
-
-/// print -  Print source files with collected line count information.
-void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename,
-                     StringRef GCNOFile, StringRef GCDAFile) {
-  SmallVector<StringRef, 4> Filenames;
-  for (const auto &LI : LineInfo)
-    Filenames.push_back(LI.first());
-  std::sort(Filenames.begin(), Filenames.end());
-
-  for (StringRef Filename : Filenames) {
-    auto AllLines = LineConsumer(Filename);
-
-    std::string CoveragePath = getCoveragePath(Filename, MainFilename);
-    std::unique_ptr<raw_ostream> CovStream = openCoveragePath(CoveragePath);
-    raw_ostream &CovOS = *CovStream;
-
-    CovOS << "        -:    0:Source:" << Filename << "\n";
-    CovOS << "        -:    0:Graph:" << GCNOFile << "\n";
-    CovOS << "        -:    0:Data:" << GCDAFile << "\n";
-    CovOS << "        -:    0:Runs:" << RunCount << "\n";
-    CovOS << "        -:    0:Programs:" << ProgramCount << "\n";
-
-    const LineData &Line = LineInfo[Filename];
-    GCOVCoverage FileCoverage(Filename);
-    for (uint32_t LineIndex = 0; LineIndex < Line.LastLine || !AllLines.empty();
-         ++LineIndex) {
-      if (Options.BranchInfo) {
-        FunctionLines::const_iterator FuncsIt = Line.Functions.find(LineIndex);
-        if (FuncsIt != Line.Functions.end())
-          printFunctionSummary(CovOS, FuncsIt->second);
-      }
-
-      BlockLines::const_iterator BlocksIt = Line.Blocks.find(LineIndex);
-      if (BlocksIt == Line.Blocks.end()) {
-        // No basic blocks are on this line. Not an executable line of code.
-        CovOS << "        -:";
-        AllLines.printNext(CovOS, LineIndex + 1);
-      } else {
-        const BlockVector &Blocks = BlocksIt->second;
-
-        // Add up the block counts to form line counts.
-        DenseMap<const GCOVFunction *, bool> LineExecs;
-        uint64_t LineCount = 0;
-        for (const GCOVBlock *Block : Blocks) {
-          if (Options.AllBlocks) {
-            // Only take the highest block count for that line.
-            uint64_t BlockCount = Block->getCount();
-            LineCount = LineCount > BlockCount ? LineCount : BlockCount;
-          } else {
-            // Sum up all of the block counts.
-            LineCount += Block->getCount();
-          }
-
-          if (Options.FuncCoverage) {
-            // This is a slightly convoluted way to most accurately gather line
-            // statistics for functions. Basically what is happening is that we
-            // don't want to count a single line with multiple blocks more than
-            // once. However, we also don't simply want to give the total line
-            // count to every function that starts on the line. Thus, what is
-            // happening here are two things:
-            // 1) Ensure that the number of logical lines is only incremented
-            //    once per function.
-            // 2) If there are multiple blocks on the same line, ensure that the
-            //    number of lines executed is incremented as long as at least
-            //    one of the blocks are executed.
-            const GCOVFunction *Function = &Block->getParent();
-            if (FuncCoverages.find(Function) == FuncCoverages.end()) {
-              std::pair<const GCOVFunction *, GCOVCoverage> KeyValue(
-                  Function, GCOVCoverage(Function->getName()));
-              FuncCoverages.insert(KeyValue);
-            }
-            GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
-
-            if (LineExecs.find(Function) == LineExecs.end()) {
-              if (Block->getCount()) {
-                ++FuncCoverage.LinesExec;
-                LineExecs[Function] = true;
-              } else {
-                LineExecs[Function] = false;
-              }
-              ++FuncCoverage.LogicalLines;
-            } else if (!LineExecs[Function] && Block->getCount()) {
-              ++FuncCoverage.LinesExec;
-              LineExecs[Function] = true;
-            }
-          }
-        }
-
-        if (LineCount == 0)
-          CovOS << "    #####:";
-        else {
-          CovOS << format("%9" PRIu64 ":", LineCount);
-          ++FileCoverage.LinesExec;
-        }
-        ++FileCoverage.LogicalLines;
-
-        AllLines.printNext(CovOS, LineIndex + 1);
-
-        uint32_t BlockNo = 0;
-        uint32_t EdgeNo = 0;
-        for (const GCOVBlock *Block : Blocks) {
-          // Only print block and branch information at the end of the block.
-          if (Block->getLastLine() != LineIndex + 1)
-            continue;
-          if (Options.AllBlocks)
-            printBlockInfo(CovOS, *Block, LineIndex, BlockNo);
-          if (Options.BranchInfo) {
-            size_t NumEdges = Block->getNumDstEdges();
-            if (NumEdges > 1)
-              printBranchInfo(CovOS, *Block, FileCoverage, EdgeNo);
-            else if (Options.UncondBranch && NumEdges == 1)
-              printUncondBranchInfo(CovOS, EdgeNo,
-                                    (*Block->dst_begin())->Count);
-          }
-        }
-      }
-    }
-    FileCoverages.push_back(std::make_pair(CoveragePath, FileCoverage));
-  }
-
-  // FIXME: There is no way to detect calls given current instrumentation.
-  if (Options.FuncCoverage)
-    printFuncCoverage(InfoOS);
-  printFileCoverage(InfoOS);
-}
-
-/// printFunctionSummary - Print function and block summary.
-void FileInfo::printFunctionSummary(raw_ostream &OS,
-                                    const FunctionVector &Funcs) const {
-  for (const GCOVFunction *Func : Funcs) {
-    uint64_t EntryCount = Func->getEntryCount();
-    uint32_t BlocksExec = 0;
-    for (const GCOVBlock &Block : Func->blocks())
-      if (Block.getNumDstEdges() && Block.getCount())
-        ++BlocksExec;
-
-    OS << "function " << Func->getName() << " called " << EntryCount
-       << " returned " << safeDiv(Func->getExitCount() * 100, EntryCount)
-       << "% blocks executed "
-       << safeDiv(BlocksExec * 100, Func->getNumBlocks() - 1) << "%\n";
-  }
-}
-
-/// printBlockInfo - Output counts for each block.
-void FileInfo::printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
-                              uint32_t LineIndex, uint32_t &BlockNo) const {
-  if (Block.getCount() == 0)
-    OS << "    $$$$$:";
-  else
-    OS << format("%9" PRIu64 ":", Block.getCount());
-  OS << format("%5u-block %2u\n", LineIndex + 1, BlockNo++);
-}
-
-/// printBranchInfo - Print conditional branch probabilities.
-void FileInfo::printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
-                               GCOVCoverage &Coverage, uint32_t &EdgeNo) {
-  SmallVector<uint64_t, 16> BranchCounts;
-  uint64_t TotalCounts = 0;
-  for (const GCOVEdge *Edge : Block.dsts()) {
-    BranchCounts.push_back(Edge->Count);
-    TotalCounts += Edge->Count;
-    if (Block.getCount())
-      ++Coverage.BranchesExec;
-    if (Edge->Count)
-      ++Coverage.BranchesTaken;
-    ++Coverage.Branches;
-
-    if (Options.FuncCoverage) {
-      const GCOVFunction *Function = &Block.getParent();
-      GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
-      if (Block.getCount())
-        ++FuncCoverage.BranchesExec;
-      if (Edge->Count)
-        ++FuncCoverage.BranchesTaken;
-      ++FuncCoverage.Branches;
-    }
-  }
-
-  for (uint64_t N : BranchCounts)
-    OS << format("branch %2u ", EdgeNo++)
-       << formatBranchInfo(Options, N, TotalCounts) << "\n";
-}
-
-/// printUncondBranchInfo - Print unconditional branch probabilities.
-void FileInfo::printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
-                                     uint64_t Count) const {
-  OS << format("unconditional %2u ", EdgeNo++)
-     << formatBranchInfo(Options, Count, Count) << "\n";
-}
-
-// printCoverage - Print generic coverage info used by both printFuncCoverage
-// and printFileCoverage.
-void FileInfo::printCoverage(raw_ostream &OS,
-                             const GCOVCoverage &Coverage) const {
-  OS << format("Lines executed:%.2f%% of %u\n",
-               double(Coverage.LinesExec) * 100 / Coverage.LogicalLines,
-               Coverage.LogicalLines);
-  if (Options.BranchInfo) {
-    if (Coverage.Branches) {
-      OS << format("Branches executed:%.2f%% of %u\n",
-                   double(Coverage.BranchesExec) * 100 / Coverage.Branches,
-                   Coverage.Branches);
-      OS << format("Taken at least once:%.2f%% of %u\n",
-                   double(Coverage.BranchesTaken) * 100 / Coverage.Branches,
-                   Coverage.Branches);
-    } else {
-      OS << "No branches\n";
-    }
-    OS << "No calls\n"; // to be consistent with gcov
-  }
-}
-
-// printFuncCoverage - Print per-function coverage info.
-void FileInfo::printFuncCoverage(raw_ostream &OS) const {
-  for (const auto &FC : FuncCoverages) {
-    const GCOVCoverage &Coverage = FC.second;
-    OS << "Function '" << Coverage.Name << "'\n";
-    printCoverage(OS, Coverage);
-    OS << "\n";
-  }
-}
-
-// printFileCoverage - Print per-file coverage info.
-void FileInfo::printFileCoverage(raw_ostream &OS) const {
-  for (const auto &FC : FileCoverages) {
-    const std::string &Filename = FC.first;
-    const GCOVCoverage &Coverage = FC.second;
-    OS << "File '" << Coverage.Name << "'\n";
-    printCoverage(OS, Coverage);
-    if (!Options.NoOutput)
-      OS << Coverage.Name << ":creating '" << Filename << "'\n";
-    OS << "\n";
-  }
-}

src/plugin/GCOV.h

@@ -1,460 +0,0 @@
-//===- GCOV.h - LLVM coverage tool ------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This header provides the interface to read and write coverage files that
-// use 'gcov' format.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_PROFILEDATA_GCOV_H
-#define LLVM_PROFILEDATA_GCOV_H
-
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/MapVector.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/iterator.h"
-#include "llvm/ADT/iterator_range.h"
-#include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Support/raw_ostream.h"
-#include <cassert>
-#include <cstddef>
-#include <cstdint>
-#include <memory>
-#include <string>
-#include <utility>
-
-namespace llvm {
-
-class GCOVFunction;
-class GCOVBlock;
-class FileInfo;
-
-namespace GCOV {
-
-enum GCOVVersion { V402, V404, V704 };
-
-/// \brief A struct for passing gcov options between functions.
-struct Options {
-  Options(bool A, bool B, bool C, bool F, bool P, bool U, bool L, bool N)
-      : AllBlocks(A), BranchInfo(B), BranchCount(C), FuncCoverage(F),
-        PreservePaths(P), UncondBranch(U), LongFileNames(L), NoOutput(N) {}
-
-  bool AllBlocks;
-  bool BranchInfo;
-  bool BranchCount;
-  bool FuncCoverage;
-  bool PreservePaths;
-  bool UncondBranch;
-  bool LongFileNames;
-  bool NoOutput;
-};
-
-} // end namespace GCOV
-
-/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific
-/// read operations.
-class GCOVBuffer {
-public:
-  GCOVBuffer(MemoryBuffer *B) : Buffer(B) {}
-
-  /// readGCNOFormat - Check GCNO signature is valid at the beginning of buffer.
-  bool readGCNOFormat() {
-    StringRef File = Buffer->getBuffer().slice(0, 4);
-    if (File != "oncg") {
-      errs() << "Unexpected file type: " << File << ".\n";
-      return false;
-    }
-    Cursor = 4;
-    return true;
-  }
-
-  /// readGCDAFormat - Check GCDA signature is valid at the beginning of buffer.
-  bool readGCDAFormat() {
-    StringRef File = Buffer->getBuffer().slice(0, 4);
-    if (File != "adcg") {
-      errs() << "Unexpected file type: " << File << ".\n";
-      return false;
-    }
-    Cursor = 4;
-    return true;
-  }
-
-  /// readGCOVVersion - Read GCOV version.
-  bool readGCOVVersion(GCOV::GCOVVersion &Version) {
-    StringRef VersionStr = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (VersionStr == "*204") {
-      Cursor += 4;
-      Version = GCOV::V402;
-      return true;
-    }
-    if (VersionStr == "*404") {
-      Cursor += 4;
-      Version = GCOV::V404;
-      return true;
-    }
-    if (VersionStr == "*704") {
-      Cursor += 4;
-      Version = GCOV::V704;
-      return true;
-    }
-    errs() << "Unexpected version: " << VersionStr << ".\n";
-    return false;
-  }
-
-  /// readFunctionTag - If cursor points to a function tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readFunctionTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readBlockTag - If cursor points to a block tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readBlockTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x41' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readEdgeTag - If cursor points to an edge tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readEdgeTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x43' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readLineTag - If cursor points to a line tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readLineTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x45' ||
-        Tag[3] != '\x01') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readArcTag - If cursor points to an gcda arc tag then increment the
-  /// cursor and return true otherwise return false.
-  bool readArcTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\xa1' ||
-        Tag[3] != '\1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readObjectTag - If cursor points to an object summary tag then increment
-  /// the cursor and return true otherwise return false.
-  bool readObjectTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\xa1') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  /// readProgramTag - If cursor points to a program summary tag then increment
-  /// the cursor and return true otherwise return false.
-  bool readProgramTag() {
-    StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
-        Tag[3] != '\xa3') {
-      return false;
-    }
-    Cursor += 4;
-    return true;
-  }
-
-  bool readInt(uint32_t &Val) {
-    if (Buffer->getBuffer().size() < Cursor + 4) {
-      errs() << "Unexpected end of memory buffer: " << Cursor + 4 << ".\n";
-      return false;
-    }
-    StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor + 4);
-    Cursor += 4;
-    Val = *(const uint32_t *)(Str.data());
-    return true;
-  }
-
-  bool readInt64(uint64_t &Val) {
-    uint32_t Lo, Hi;
-    if (!readInt(Lo) || !readInt(Hi))
-      return false;
-    Val = ((uint64_t)Hi << 32) | Lo;
-    return true;
-  }
-
-  bool readString(StringRef &Str) {
-    uint32_t Len = 0;
-    // Keep reading until we find a non-zero length. This emulates gcov's
-    // behaviour, which appears to do the same.
-    while (Len == 0)
-      if (!readInt(Len))
-        return false;
-    Len *= 4;
-    if (Buffer->getBuffer().size() < Cursor + Len) {
-      errs() << "Unexpected end of memory buffer: " << Cursor + Len << ".\n";
-      return false;
-    }
-    Str = Buffer->getBuffer().slice(Cursor, Cursor + Len).split('\0').first;
-    Cursor += Len;
-    return true;
-  }
-
-  uint64_t getCursor() const { return Cursor; }
-  void advanceCursor(uint32_t n) { Cursor += n * 4; }
-
-private:
-  MemoryBuffer *Buffer;
-  uint64_t Cursor = 0;
-};
-
-/// GCOVFile - Collects coverage information for one pair of coverage file
-/// (.gcno and .gcda).
-class GCOVFile {
-public:
-  GCOVFile() = default;
-
-  bool readGCNO(GCOVBuffer &Buffer);
-  bool readGCDA(GCOVBuffer &Buffer);
-  uint32_t getChecksum() const { return Checksum; }
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  bool GCNOInitialized = false;
-  GCOV::GCOVVersion Version;
-  uint32_t Checksum = 0;
-  SmallVector<std::unique_ptr<GCOVFunction>, 16> Functions;
-  uint32_t RunCount = 0;
-  uint32_t ProgramCount = 0;
-};
-
-/// GCOVEdge - Collects edge information.
-struct GCOVEdge {
-  GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D) {}
-
-  GCOVBlock &Src;
-  GCOVBlock &Dst;
-  uint64_t Count = 0;
-};
-
-/// GCOVFunction - Collects function information.
-class GCOVFunction {
-public:
-  using BlockIterator = pointee_iterator<SmallVectorImpl<
-      std::unique_ptr<GCOVBlock>>::const_iterator>;
-
-  GCOVFunction(GCOVFile &P) : Parent(P) {}
-
-  bool readGCNO(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
-  bool readGCDA(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
-  StringRef getName() const { return Name; }
-  StringRef getFilename() const { return Filename; }
-  size_t getNumBlocks() const { return Blocks.size(); }
-  uint64_t getEntryCount() const;
-  uint64_t getExitCount() const;
-
-  BlockIterator block_begin() const { return Blocks.begin(); }
-  BlockIterator block_end() const { return Blocks.end(); }
-  iterator_range<BlockIterator> blocks() const {
-    return make_range(block_begin(), block_end());
-  }
-
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  GCOVFile &Parent;
-  uint32_t Ident = 0;
-  uint32_t Checksum;
-  uint32_t LineNumber = 0;
-  StringRef Name;
-  StringRef Filename;
-  SmallVector<std::unique_ptr<GCOVBlock>, 16> Blocks;
-  SmallVector<std::unique_ptr<GCOVEdge>, 16> Edges;
-};
-
-/// GCOVBlock - Collects block information.
-class GCOVBlock {
-  struct EdgeWeight {
-    EdgeWeight(GCOVBlock *D) : Dst(D) {}
-
-    GCOVBlock *Dst;
-    uint64_t Count = 0;
-  };
-
-  struct SortDstEdgesFunctor {
-    bool operator()(const GCOVEdge *E1, const GCOVEdge *E2) {
-      return E1->Dst.Number < E2->Dst.Number;
-    }
-  };
-
-public:
-  using EdgeIterator = SmallVectorImpl<GCOVEdge *>::const_iterator;
-
-  GCOVBlock(GCOVFunction &P, uint32_t N) : Parent(P), Number(N) {}
-  ~GCOVBlock();
-
-  const GCOVFunction &getParent() const { return Parent; }
-  void addLine(uint32_t N) { Lines.push_back(N); }
-  uint32_t getLastLine() const { return Lines.back(); }
-  void addCount(size_t DstEdgeNo, uint64_t N);
-  uint64_t getCount() const { return Counter; }
-
-  void addSrcEdge(GCOVEdge *Edge) {
-    assert(&Edge->Dst == this); // up to caller to ensure edge is valid
-    SrcEdges.push_back(Edge);
-  }
-
-  void addDstEdge(GCOVEdge *Edge) {
-    assert(&Edge->Src == this); // up to caller to ensure edge is valid
-    // Check if adding this edge causes list to become unsorted.
-    if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
-      DstEdgesAreSorted = false;
-    DstEdges.push_back(Edge);
-  }
-
-  size_t getNumSrcEdges() const { return SrcEdges.size(); }
-  size_t getNumDstEdges() const { return DstEdges.size(); }
-  void sortDstEdges();
-
-  EdgeIterator src_begin() const { return SrcEdges.begin(); }
-  EdgeIterator src_end() const { return SrcEdges.end(); }
-  iterator_range<EdgeIterator> srcs() const {
-    return make_range(src_begin(), src_end());
-  }
-
-  EdgeIterator dst_begin() const { return DstEdges.begin(); }
-  EdgeIterator dst_end() const { return DstEdges.end(); }
-  iterator_range<EdgeIterator> dsts() const {
-    return make_range(dst_begin(), dst_end());
-  }
-
-  void print(raw_ostream &OS) const;
-  void dump() const;
-  void collectLineCounts(FileInfo &FI);
-
-private:
-  GCOVFunction &Parent;
-  uint32_t Number;
-  uint64_t Counter = 0;
-  bool DstEdgesAreSorted = true;
-  SmallVector<GCOVEdge *, 16> SrcEdges;
-  SmallVector<GCOVEdge *, 16> DstEdges;
-  SmallVector<uint32_t, 16> Lines;
-};
-
-class FileInfo {
-  // It is unlikely--but possible--for multiple functions to be on the same
-  // line.
-  // Therefore this typedef allows LineData.Functions to store multiple
-  // functions
-  // per instance. This is rare, however, so optimize for the common case.
-  using FunctionVector = SmallVector<const GCOVFunction *, 1>;
-  using FunctionLines = DenseMap<uint32_t, FunctionVector>;
-  using BlockVector = SmallVector<const GCOVBlock *, 4>;
-  using BlockLines = DenseMap<uint32_t, BlockVector>;
-
-  struct LineData {
-    LineData() = default;
-
-    BlockLines Blocks;
-    FunctionLines Functions;
-    uint32_t LastLine = 0;
-  };
-
-  struct GCOVCoverage {
-    GCOVCoverage(StringRef Name) : Name(Name) {}
-
-    StringRef Name;
-
-    uint32_t LogicalLines = 0;
-    uint32_t LinesExec = 0;
-
-    uint32_t Branches = 0;
-    uint32_t BranchesExec = 0;
-    uint32_t BranchesTaken = 0;
-  };
-
-public:
-  FileInfo(const GCOV::Options &Options) : Options(Options) {}
-
-  void addBlockLine(StringRef Filename, uint32_t Line, const GCOVBlock *Block) {
-    if (Line > LineInfo[Filename].LastLine)
-      LineInfo[Filename].LastLine = Line;
-    LineInfo[Filename].Blocks[Line - 1].push_back(Block);
-  }
-
-  void addFunctionLine(StringRef Filename, uint32_t Line,
-                       const GCOVFunction *Function) {
-    if (Line > LineInfo[Filename].LastLine)
-      LineInfo[Filename].LastLine = Line;
-    LineInfo[Filename].Functions[Line - 1].push_back(Function);
-  }
-
-  void setRunCount(uint32_t Runs) { RunCount = Runs; }
-  void setProgramCount(uint32_t Programs) { ProgramCount = Programs; }
-  void print(raw_ostream &OS, StringRef MainFilename, StringRef GCNOFile,
-             StringRef GCDAFile);
-
-private:
-  std::string getCoveragePath(StringRef Filename, StringRef MainFilename);
-  std::unique_ptr<raw_ostream> openCoveragePath(StringRef CoveragePath);
-  void printFunctionSummary(raw_ostream &OS, const FunctionVector &Funcs) const;
-  void printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
-                      uint32_t LineIndex, uint32_t &BlockNo) const;
-  void printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
-                       GCOVCoverage &Coverage, uint32_t &EdgeNo);
-  void printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
-                             uint64_t Count) const;
-
-  void printCoverage(raw_ostream &OS, const GCOVCoverage &Coverage) const;
-  void printFuncCoverage(raw_ostream &OS) const;
-  void printFileCoverage(raw_ostream &OS) const;
-
-  const GCOV::Options &Options;
-  StringMap<LineData> LineInfo;
-  uint32_t RunCount = 0;
-  uint32_t ProgramCount = 0;
-
-  using FileCoverageList = SmallVector<std::pair<std::string, GCOVCoverage>, 4>;
-  using FuncCoverageMap = MapVector<const GCOVFunction *, GCOVCoverage>;
-
-  FileCoverageList FileCoverages;
-  FuncCoverageMap FuncCoverages;
-};
-
-} // end namespace llvm
-
-#endif // LLVM_SUPPORT_GCOV_H

src/plugin/cycle_estimate.cpp

@@ -36,57 +36,83 @@
 
 #include <iss/arch_if.h>
 #include <util/logging.h>
+#include <rapidjson/document.h>
+#include <rapidjson/istreamwrapper.h>
+#include "rapidjson/writer.h"
+#include "rapidjson/stringbuffer.h"
+#include <rapidjson/ostreamwrapper.h>
+#include <rapidjson/error/en.h>
 #include <fstream>
 
-iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
-: arch_instr(nullptr)
+using namespace rapidjson;
+using namespace std;
+
+iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
+: instr_if(nullptr)
+, config_file_name(config_file_name)
 {
-    if (config_file_name.length() > 0) {
-        std::ifstream is(config_file_name);
-        if (is.is_open()) {
-            try {
-                is >> root;
-            } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
-            }
-        } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
-        }
-    }
 }
 
 iss::plugin::cycle_estimate::~cycle_estimate() {
 }
 
 bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
-	arch_instr = vm.get_arch()->get_instrumentation_if();
-	if(!arch_instr) return false;
-	const std::string  core_name = arch_instr->core_type_name();
-    Json::Value &val = root[core_name];
-    if(!val.isNull() && val.isArray()){
-    	delays.reserve(val.size());
-    	for(auto it:val){
-    		auto name = it["name"];
-    		auto size = it["size"];
-    		auto delay = it["delay"];
-    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
-    		if(delay.isUInt()){
-				delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
-    		} else {
-				delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
-    		}
-    	}
-    } else {
-        LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    if(!instr_if) return false;
+    const string  core_name = instr_if->core_type_name();
+    if (config_file_name.length() > 0) {
+        ifstream is(config_file_name);
+        if (is.is_open()) {
+            try {
+                IStreamWrapper isw(is);
+                Document d;
+                ParseResult ok = d.ParseStream(isw);
+                if(ok) {
+                    Value& val = d[core_name.c_str()];
+                    if(val.IsArray()){
+                        delays.reserve(val.Size());
+                        for (auto it = val.Begin(); it != val.End(); ++it) {
+                            auto& name = (*it)["name"];
+                            auto& size = (*it)["size"];
+                            auto& delay = (*it)["delay"];
+                            auto& branch = (*it)["branch"];
+                            if(delay.IsArray()) {
+                                auto dt = delay[0].Get<unsigned>();
+                                auto dnt = delay[1].Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
+                            } else if(delay.Is<unsigned>()) {
+                                auto d = delay.Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
+                            } else
+                                throw runtime_error("JSON parse error");
+                       }
+                    } else {
+                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
+                        return false;
+                   }
+                } else {
+                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
+                    return false;
+               }
+            } catch (runtime_error &e) {
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            LOG(ERR) << "Could not open input file " << config_file_name;
+            return false;
+        }
     }
-	return true;
+    return true;
 
 }
 
-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
-    assert(arch_instr && "No instrumentation interface available but callback executed");
-	auto entry = delays[instr_info.instr_id];
-	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
-    uint32_t delay = taken ? entry.taken : entry.not_taken;
-    if(delay>1) arch_instr->set_curr_instr_cycles(delay);
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
+    assert(instr_if && "No instrumentation interface available but callback executed");
+    auto entry = delays[instr_info.instr_id];
+    bool taken = exc_info.branch_taken;
+    if (exc_info.branch_taken && (entry.taken > 1))
+        instr_if->set_curr_instr_cycles(entry.taken);
+    else if (entry.not_taken > 1)
+        instr_if->set_curr_instr_cycles(entry.not_taken);
 }

src/plugin/instruction_count.cpp

@@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
             try {
                 is >> root;
             } catch (Json::RuntimeError &e) {
-                LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
-            LOG(ERROR) << "Could not open input file " << config_file_name;
+            LOG(ERR) << "Could not open input file " << config_file_name;
         }
     }
 }
@@ -85,7 +85,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
     	}
     	rep_counts.resize(delays.size());
     } else {
-        LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
     }
 	return true;
 }

src/plugin/pctrace.cpp

@@ -0,0 +1,180 @@
+#include <iss/arch_if.h>
+#include <iss/plugin/pctrace.h>
+#include <util/logging.h>
+#include <util/ities.h>
+#include <rapidjson/document.h>
+#include <rapidjson/istreamwrapper.h>
+#include "rapidjson/writer.h"
+#include "rapidjson/stringbuffer.h"
+#include <rapidjson/ostreamwrapper.h>
+#include <rapidjson/error/en.h>
+#include <fstream>
+#include <iostream>
+#ifdef WITH_LZ4
+#include <lz4frame.h>
+#endif
+
+namespace iss {
+namespace plugin {
+
+using namespace rapidjson;
+using namespace std;
+
+#ifdef WITH_LZ4
+class lz4compress_steambuf: public std::streambuf {
+public:
+    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
+    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
+    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
+    : sink(sink)
+    , src_buf(buf_size)
+    , dest_buf(LZ4F_compressBound(buf_size, nullptr))
+    {
+        auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
+        if (LZ4F_isError(errCode) != 0)
+            throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
+        size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
+        if (LZ4F_isError(ret) != 0)
+            throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
+        setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
+        sink.write(dest_buf.data(), ret);
+    }
+
+    ~lz4compress_steambuf() {
+        close();
+    }
+
+    void close() {
+        if (closed)
+            return;
+        sync();
+        auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
+        if (LZ4F_isError(ret) != 0)
+            throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
+        sink.write(dest_buf.data(), ret);
+        LZ4F_freeCompressionContext(ctx);
+        closed = true;
+    }
+
+private:
+    int_type overflow(int_type ch) override {
+        compress_and_write();
+        *pptr() = static_cast<char_type>(ch);
+        pbump(1);
+        return ch;
+    }
+
+    int_type sync() override {
+        compress_and_write();
+        return 0;
+    }
+
+    void compress_and_write() {
+        if (closed)
+            throw std::runtime_error("Cannot write to closed stream");
+        if(auto orig_size = pptr() - pbase()){
+            auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
+            if (LZ4F_isError(ret) != 0)
+                throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
+            if(ret) sink.write(dest_buf.data(), ret);
+            pbump(-orig_size);
+        }
+    }
+
+    std::ostream &sink;
+    std::vector<char> src_buf;
+    std::vector<char> dest_buf;
+    LZ4F_compressionContext_t ctx{ nullptr };
+    bool closed{ false };
+};
+#endif
+
+cov::cov(std::string const &filename)
+: instr_if(nullptr)
+, filename(filename)
+, output("output.trc")
+#ifdef WITH_LZ4
+, strbuf(new lz4compress_steambuf(output, 4096))
+, ostr(strbuf.get())
+#endif
+{ }
+
+cov::~cov() { }
+
+bool cov::registration(const char *const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    if(!instr_if) return false;
+    const string  core_name = instr_if->core_type_name();
+    if (filename.length() > 0) {
+        ifstream is(filename);
+        if (is.is_open()) {
+            try {
+                IStreamWrapper isw(is);
+                Document d;
+                ParseResult ok = d.ParseStream(isw);
+                if(ok) {
+                    Value& val = d[core_name.c_str()];
+                    if(val.IsArray()){
+                        delays.reserve(val.Size());
+                        for (auto it = val.Begin(); it != val.End(); ++it) {
+                            auto& name = (*it)["name"];
+                            auto& size = (*it)["size"];
+                            auto& delay = (*it)["delay"];
+                            auto& branch = (*it)["branch"];
+                            if(delay.IsArray()) {
+                                auto dt = delay[0].Get<unsigned>();
+                                auto dnt = delay[1].Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
+                            } else if(delay.Is<unsigned>()) {
+                                auto d = delay.Get<unsigned>();
+                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
+                            } else
+                                throw runtime_error("JSON parse error");
+
+                        }
+                    } else {
+                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
+                        return false;
+                    }
+                } else {
+                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
+                    return false;
+                }
+            } catch (runtime_error &e) {
+                LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
+                return false;
+            }
+        } else {
+            LOG(ERR) << "Could not open input file " << filename;
+            return false;
+        }
+    }
+    return true;
+}
+
+void cov::callback(instr_info_t iinfo, const exec_info& einfo) {
+    auto delay = 0;
+    size_t id = iinfo.instr_id;
+    auto entry = delays[id];
+    auto instr = instr_if->get_instr_word();
+    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
+    bool taken = einfo.branch_taken;
+    bool compressed = (instr&0x3)!=0x3;
+    if (einfo.branch_taken) {
+        delay = entry.taken;
+        if(entry.taken > 1)
+            instr_if->set_curr_instr_cycles(entry.taken);
+    } else {
+        delay = entry.not_taken;
+        if (entry.not_taken > 1)
+            instr_if->set_curr_instr_cycles(entry.not_taken);
+    }
+#ifndef WITH_LZ4
+    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
+#else
+    auto rdbuf=ostr.rdbuf();
+    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
+#endif
+}
+}
+}

src/sysc/core_complex.cpp

@@ -30,39 +30,50 @@
  *
  *******************************************************************************/
 
-#include "sysc/core_complex.h"
-#ifdef CORE_TGC_B
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_b.h"
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#endif
-#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_D
-#include "iss/arch/riscv_hart_mu_p.h"
-#include "iss/arch/tgc_d.h"
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
-#endif
-#include "iss/debugger/encoderdecoder.h"
-#include "iss/debugger/gdb_session.h"
-#include "iss/debugger/server.h"
-#include "iss/debugger/target_adapter_if.h"
-#include "iss/iss.h"
-#include "iss/vm_types.h"
-#include "scc/report.h"
+// clang-format off
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/encoderdecoder.h>
+#include <iss/debugger/server.h>
+#include <iss/debugger/target_adapter_if.h>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <iss/plugin/loader.h>
+#include <sysc/core_complex.h>
+#include <iss/arch/tgc_mapper.h>
+#include <scc/report.h>
+#include <util/ities.h>
 #include <iostream>
 #include <sstream>
+#include <array>
+#include <iss/plugin/cycle_estimate.h>
+#include <iss/plugin/instruction_count.h>
+#include <iss/plugin/pctrace.h>
+
+// clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN) \
 if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
 
-#ifdef WITH_SCV
-#include <array>
+#ifdef HAS_SCV
 #include <scv.h>
+#else
+#include <scv-tr.h>
+using namespace scv_tr;
 #endif
 
+#ifndef CWR_SYSTEMC
+#define GET_PROP_VALUE(P) P.get_value()
+#else
+#define GET_PROP_VALUE(P) P.getValue()
+#endif
+
+#ifdef _MSC_VER
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+#define strncasecmp _strnicmp
+#define strcasecmp _stricmp
+#endif
+
 namespace sysc {
 namespace tgfs {
 using namespace std;
@@ -94,21 +105,21 @@ public:
     heart_state_t &get_state() { return this->state; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART) owner->sync(this->reg.icount);
+        if (p == iss::arch_if::ISTART) owner->sync(this->icount);
     }
 
     sync_type needed_sync() const override { return PRE_SYNC; }
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
+        if (!owner->disass_output(pc, instr)) {
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-            Log<Output2FILE<disass>>().get(INFO, "disass")
+              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
+              << this->icount + this->cycle_offset << "]";
+            SCCDEBUG(owner->name())<<"disass: "
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                 << std::setfill(' ') << std::left << instr << s.str();
         }
-        owner->disass_output(pc, instr);
     };
 
     status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
@@ -135,6 +146,7 @@ public:
     }
 
     status read_csr(unsigned addr, reg_t &val) override {
+#ifndef CWR_SYSTEMC
         if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
             uint64_t time_val;
             bool ret = owner->mtime_o->nb_peek(time_val);
@@ -145,6 +157,17 @@ public:
                 val = static_cast<reg_t>(time_val >> 32);
             }
             return ret?Ok:Err;
+#else
+		if((addr==arch::time || addr==arch::timeh)){
+			uint64_t time_val = owner->mtime_i.read();
+			if (addr == iss::arch::time) {
+				val = static_cast<reg_t>(time_val);
+			} else if (addr == iss::arch::timeh) {
+				if (sizeof(reg_t) != 4) return iss::Err;
+				val = static_cast<reg_t>(time_val >> 32);
+			}
+			return Ok;
+#endif
         } else {
             return PLAT::read_csr(addr, val);
         }
@@ -152,9 +175,9 @@ public:
 
     void wait_until(uint64_t flags) override {
         SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        do {
+        while(this->pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
             sc_core::wait(wfi_evt);
-        } while (this->reg.pending_trap == 0);
+        }
         PLAT::wait_until(flags);
     }
 
@@ -181,7 +204,7 @@ public:
             this->csr[arch::mip] &= ~mask;
         this->check_interrupt();
         if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->pending_trap;
     }
 
 private:
@@ -265,9 +288,15 @@ public:
 #endif
 #ifdef CORE_TGC_D
         CREATE_CORE(tgc_d)
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+        CREATE_CORE(tgc_d_xrb_mac)
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        CREATE_CORE(tgc_d_xrb_nn)
 #endif
         {
-            LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
         }
         auto *srv = debugger::server<debugger::gdb_session>::get();
         if (srv) tgt_adapter = srv->get_target();
@@ -285,18 +314,29 @@ public:
     iss::debugger::target_adapter_if *tgt_adapter{nullptr};
 };
 
-core_complex::core_complex(sc_module_name name)
+struct core_trace {
+    //! transaction recording database
+    scv_tr_db *m_db{nullptr};
+    //! blocking transaction recording stream handle
+    scv_tr_stream *stream_handle{nullptr};
+    //! transaction generator handle for blocking transactions
+    scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle{nullptr};
+    scv_tr_handle tr_handle;
+};
+
+SC_HAS_PROCESS(core_complex);// NOLINT
+#ifndef CWR_SYSTEMC
+core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
-#ifdef WITH_SCV
-, m_db(scv_tr_db::get_default_db())
-, stream_handle(nullptr)
-, instr_tr_handle(nullptr)
-, fetch_tr_handle(nullptr)
-#endif
 {
-    SC_HAS_PROCESS(core_complex);// NOLINT
+	init();
+}
+#endif
+
+void core_complex::init(){
+	trc=new core_trace();
     initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = read_lut.getEntry(start);
         if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@@ -309,8 +349,6 @@ core_complex::core_complex(sc_module_name name)
     });
 
     SC_THREAD(run);
-    SC_METHOD(clk_cb);
-    sensitive << clk_i;
     SC_METHOD(rst_cb);
     sensitive << rst_i;
     SC_METHOD(sw_irq_cb);
@@ -319,61 +357,119 @@ core_complex::core_complex(sc_module_name name)
     sensitive << timer_irq_i;
     SC_METHOD(global_irq_cb);
     sensitive << global_irq_i;
+    trc->m_db=scv_tr_db::get_default_db();
+
+	SC_METHOD(forward);
+#ifndef CWR_SYSTEMC
+	sensitive<<clk_i;
+#else
+	sensitive<<curr_clk;
+	t2t.reset(new scc::tick2time{"t2t"});
+	t2t->clk_i(clk_i);
+	t2t->clk_o(curr_clk);
+#endif
 }
 
-core_complex::~core_complex() = default;
+core_complex::~core_complex(){
+    delete cpu;
+    delete trc;
+    for (auto *p : plugin_list)
+        delete p;
+}
 
 void core_complex::trace(sc_trace_file *trf) const {}
 
 void core_complex::before_end_of_elaboration() {
-    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
-    cpu = scc::make_unique<core_wrapper>(this);
-    cpu->create_cpu(core_type.get_value(), backend.get_value(), gdb_server_port.get_value(), mhartid.get_value());
+    SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
+    // cpu = scc::make_unique<core_wrapper>(this);
+    cpu = new core_wrapper(this);
+    cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
     sc_assert(cpu->vm!=nullptr);
-#ifdef WITH_SCV
-    cpu->vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
-#else
-    cpu->vm->setDisassEnabled(enable_disass.get_value());
-#endif
+    cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
+    if (GET_PROP_VALUE(plugins).length()) {
+        auto p = util::split(GET_PROP_VALUE(plugins), ';');
+        for (std::string const& opt_val : p) {
+            std::string plugin_name=opt_val;
+            std::string filename{"cycles.txt"};
+            std::size_t found = opt_val.find('=');
+            if (found != std::string::npos) {
+                plugin_name = opt_val.substr(0, found);
+                filename = opt_val.substr(found + 1, opt_val.size());
+            }
+            if (plugin_name == "ic") {
+                auto *plugin = new iss::plugin::instruction_count(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else if (plugin_name == "ce") {
+                auto *plugin = new iss::plugin::cycle_estimate(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else if (plugin_name == "pctrace") {
+                auto *plugin = new iss::plugin::cov(filename);
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else {
+                std::array<char const*, 1> a{{filename.c_str()}};
+                iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                if(plugin){
+                    cpu->vm->register_plugin(*plugin);
+                    plugin_list.push_back(plugin);
+                } else
+                    SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
+            }
+        }
+    }
+
 }
 
 void core_complex::start_of_simulation() {
     quantum_keeper.reset();
-    if (elf_file.get_value().size() > 0) {
-        istringstream is(elf_file.get_value());
+    if (GET_PROP_VALUE(elf_file).size() > 0) {
+        istringstream is(GET_PROP_VALUE(elf_file));
         string s;
         while (getline(is, s, ',')) {
             std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
+#ifndef CWR_SYSTEMC
             if (reset_address.is_default_value() && start_addr.second == true)
                 reset_address.set_value(start_addr.first);
+#else
+            if (start_addr.second == true)
+                reset_address=start_addr.first;
+#endif
         }
     }
-#ifdef WITH_SCV
-    if (m_db != nullptr && stream_handle == nullptr) {
+    if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
         string basename(this->name());
-        stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
-        instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
-        fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
+        trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);
+        trc->instr_tr_handle = new scv_tr_generator<>("execute", *trc->stream_handle);
     }
+}
+
+bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
+    if (trc->m_db == nullptr) return false;
+    if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
+    trc->tr_handle = trc->instr_tr_handle->begin_transaction();
+    trc->tr_handle.record_attribute("PC", pc);
+    trc->tr_handle.record_attribute("INSTR", instr_str);
+    trc->tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
+    trc->tr_handle.record_attribute("MSTATUS", cpu->get_state());
+    trc->tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
+    return true;
+}
+
+void core_complex::forward() {
+#ifndef CWR_SYSTEMC
+	set_clock_period(clk_i.read());
+#else
+	set_clock_period(curr_clk.read());
+
 #endif
 }
 
-void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
-#ifdef WITH_SCV
-    if (m_db == nullptr) return;
-    if (tr_handle.is_active()) tr_handle.end_transaction();
-    tr_handle = instr_tr_handle->begin_transaction();
-    tr_handle.record_attribute("PC", pc);
-    tr_handle.record_attribute("INSTR", instr_str);
-    tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
-    tr_handle.record_attribute("MSTATUS", cpu->get_state());
-    tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
-#endif
-}
-
-void core_complex::clk_cb() {
-    curr_clk = clk_i.read();
-    if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
+void core_complex::set_clock_period(sc_core::sc_time period) {
+	curr_clk = period;
+    if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
 }
 
 void core_complex::rst_cb() {
@@ -390,11 +486,11 @@ void core_complex::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
         if (rst_i.read()) {
-            cpu->reset(reset_address.get_value());
+            cpu->reset(GET_PROP_VALUE(reset_address));
             wait(rst_i.negedge_event());
         }
-        while (clk_i.read() == SC_ZERO_TIME) {
-            wait(clk_i.value_changed_event());
+        while (curr_clk.read() == SC_ZERO_TIME) {
+            wait(curr_clk.value_changed_event());
         }
         cpu->set_interrupt_execution(false);
         cpu->start();
@@ -418,15 +514,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay=quantum_keeper.get_local_time();
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            if (is_fetch && tr_handle.is_active()) {
-                tr_handle.end_transaction();
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            if (is_fetch && trc->tr_handle.is_active()) {
+                trc->tr_handle.end_transaction();
             }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-#endif
         initiator->b_transport(gp, delay);
         SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
@@ -467,12 +561,10 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay=quantum_keeper.get_local_time();
-#ifdef WITH_SCV
-        if (m_db != nullptr && tr_handle.is_valid()) {
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+        if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-#endif
         initiator->b_transport(gp, delay);
         quantum_keeper.set(delay);
         SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
@@ -535,6 +627,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
         return initiator->transport_dbg(gp) == length;
     }
 }
-
 } /* namespace SiFive */
 } /* namespace sysc */