 eyck
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52ed8b81a6
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fixed template to work with previous code generator
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2022-05-30 14:08:02 +02:00 |
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eyck
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0703a0a845
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update tgc-mapper
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2022-05-30 07:45:32 +02:00 |
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eyck
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0c542d42aa
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separate generated sources
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2022-05-21 12:48:28 +02:00 |
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eyck
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966d1616c5
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change source code to unified layout
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2022-05-21 11:55:24 +02:00 |
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eyck
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df16378605
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update template for changed code generator
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2022-05-18 19:10:34 +02:00 |
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eyck
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1438f0f373
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add backannotation to pc trace plugin
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2022-05-17 15:29:04 +02:00 |
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eyck
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766f3ba9ee
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fix assertion in compressed pctrace writer
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2022-05-13 12:38:12 +02:00 |
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eyck
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5da4e6b424
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fix alignment check for unaligned debugger accesses
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2022-05-13 12:37:47 +02:00 |
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eyck
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e382217e04
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update vm_tgc_c due reworked CoreDSL generator
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2022-05-11 18:52:15 +02:00 |
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eyck
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9db4e3fd87
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fix assertion
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2022-05-10 16:13:21 +02:00 |
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|
eyck
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e56bc12788
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fix non-lz4 build of plugin
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2022-05-07 17:27:11 +02:00 |
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eyck
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e88f309ea2
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add lz4 compression to pctrace
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2022-05-07 17:22:06 +02:00 |
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eyck
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03bec27376
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implement extended instrumentation interface
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2022-04-26 17:14:33 +02:00 |
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eyck
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9d9008a3a2
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fix pointer mess
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2022-04-26 15:35:17 +02:00 |
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eyck
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a92b84bef4
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add code word access for ISS plugins
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2022-04-25 14:18:19 +02:00 |
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eyck
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477c530847
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extend debug mode handling
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2022-04-13 11:41:01 +02:00 |
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eyck
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c054d75717
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update to latest coredsl description
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2022-04-10 18:55:44 +02:00 |
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eyck
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15cd26f800
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remove CoreDSL ISA repo
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2022-04-10 12:15:40 +02:00 |
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eyck
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9465cffe79
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adapt to change in dbt-rise-core
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2022-04-09 14:55:36 +02:00 |
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eyck
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00d2d06cbd
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adapt to privileged spec
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2022-03-31 20:33:12 +02:00 |
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eyck
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8e4e702cb9
|
Merge remote-tracking branch 'origin/feature/reduced_output' into develop
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2022-03-28 14:09:06 +02:00 |
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eyck
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49be143588
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make features configurable
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2022-03-27 17:54:08 +02:00 |
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eyck
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0aea1d0177
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remove mcounteren in M-mode only wrapper
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2022-03-27 17:21:46 +02:00 |
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eyck
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6ea7721961
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add TCM
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2022-03-27 15:38:18 +02:00 |
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eyck
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b0cb997009
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add TGC_X with DMR
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2022-03-26 10:48:21 +01:00 |
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eyck
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9dfca612b7
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add hardware loop CSR access
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2022-03-25 11:33:44 +01:00 |
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eyck
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30ae743361
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add pctrace plugin to iss
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2022-03-20 17:41:54 +01:00 |
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eyck
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d91f5f9df4
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fix compiler warning for reduced number of registers
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2022-03-14 15:38:05 +01:00 |
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eyck
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2e670c4d03
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change interpreter structure
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2022-03-06 15:11:38 +01:00 |
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eyck
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3d32c33333
|
update gitignore
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2022-03-05 20:59:45 +01:00 |
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eyck
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521f40a3d6
|
refactored interpreter backend structure
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2022-03-05 20:59:17 +01:00 |
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eyck
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b37ef973de
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clean up
|
2022-02-14 20:36:12 +01:00 |
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eyck
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b8fa5fbbda
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adapt to extended instrumentation interface
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2022-02-09 21:01:17 +01:00 |
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eyck
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ac86f14a54
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add tgc_c_xrb_nn to tgc-sim
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2022-02-02 21:33:42 +01:00 |
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eyck
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68b5697c8f
|
Fix cycles JSON template
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2022-02-01 21:48:56 +01:00 |
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eyck
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09b0f0d0c8
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fix cycle estimation plugin
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2022-02-01 21:14:50 +01:00 |
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eyck
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98b418ff43
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fix JSON reading
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2022-02-01 19:28:11 +01:00 |
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eyck
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059bd0d371
|
rework cycle estimation
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2022-02-01 19:03:45 +01:00 |
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eyck
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ef2a4df925
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simplify spawn block handling
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2022-01-31 23:40:31 +01:00 |
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eyck
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afe8905ac9
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fix else-ambiguity in CoreDSL description
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2022-01-31 20:30:46 +01:00 |
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eyck
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3563ba80d0
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add spawn blocks
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2022-01-12 07:21:16 +01:00 |
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eyck
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09955be90f
|
update gitignore
|
2021-12-05 08:45:49 +01:00 |
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eyck
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dd4c19a15c
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add option to configure number of irq
|
2021-12-01 12:56:36 +01:00 |
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eyck
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07d5af1dde
|
fix stand-alone ISS compilation to include all generated cores
|
2021-11-26 17:56:40 +01:00 |
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eyck
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6f8595759e
|
make tgc-sim include all available ISS
|
2021-11-25 20:00:27 +01:00 |
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eyck
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309758b994
|
fix clic_cfg access scheme
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2021-11-17 07:59:02 +01:00 |
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|
eyck
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965929d1eb
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remove descriptions
|
2021-11-15 09:30:16 +01:00 |
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eyck
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d47375a70e
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fix ebreak CSR update
|
2021-11-13 12:47:23 +01:00 |
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eyck
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d31b4ef5a8
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fix MISA val
|
2021-11-11 12:58:57 +01:00 |
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eyck
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7452c5df43
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add TGC_D_XRB_NN definition
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2021-11-11 12:16:35 +01:00 |
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eyck
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43d7b99905
|
revert pmp check implementation
|
2021-11-11 09:58:19 +01:00 |
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eyck
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f90c48e881
|
adapt to changed define names
|
2021-11-11 08:33:35 +01:00 |
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eyck
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2d7973520b
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fix mip handling
|
2021-11-09 19:47:34 +01:00 |
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eyck
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fd98ad95f6
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rework PMP check and fix MISA for TGC_D
|
2021-11-09 15:55:22 +01:00 |
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eyck
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bfa8166223
|
fix wrong template class name
|
2021-11-08 10:44:33 +01:00 |
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eyck
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c42e336509
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fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
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eyck
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49d09a05d7
|
fix access rights to debug CSR register (#268)
|
2021-11-07 16:45:10 +01:00 |
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|
eyck
|
459794b863
|
add proper handling of store access fault (hart_mu_p)
|
2021-11-06 13:29:11 +01:00 |
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eyck
|
039746112b
|
fix exception behavior
|
2021-11-02 15:10:20 +01:00 |
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eyck
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ac6d7ea5d4
|
add debug feature to platform
|
2021-11-02 11:13:29 +01:00 |
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|
eyck
|
8b6e3abd23
|
fix hard-code arch in templates
|
2021-10-30 13:37:17 +02:00 |
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|
eyck
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
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|
eyck
|
a20f39e847
|
update core definitions to include Zicsr and Zifencei (#276)
|
2021-10-30 12:56:31 +02:00 |
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|
eyck
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
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|
eyck
|
eb2ca33e5a
|
remove unused sources
|
2021-10-12 15:17:56 +02:00 |
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|
eyck
|
0ea4cba1ca
|
add dynamic plugin loading
|
2021-10-12 14:24:55 +02:00 |
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|
eyck
|
1d13c8196e
|
fix wrong PGMASK usage
|
2021-10-11 10:40:01 +02:00 |
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|
eyck
|
ee6e1d4092
|
Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
|
2021-10-11 09:42:40 +02:00 |
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|
eyck
|
c8679fca85
|
remove MSVC warning
|
2021-10-10 19:56:33 +02:00 |
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|
eyck
|
f0ada1ba8c
|
add MSVC 16 compatibility
|
2021-10-10 19:06:41 +02:00 |
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|
eyck
|
b17682e50e
|
fix YAML template
|
2021-10-01 23:49:04 +02:00 |
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|
eyck
|
5866acf565
|
update .gitignore
|
2021-10-01 13:06:10 +02:00 |
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|
eyck
|
6acf73a40f
|
add template to generate instruction YAML
|
2021-10-01 13:05:36 +02:00 |
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|
eyck
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
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|
eyck
|
d78fcc48e5
|
use marchid in platform
|
2021-09-30 19:27:03 +02:00 |
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|
eyck
|
4186723d37
|
add marchid setting to CoreDSL description
|
2021-09-30 19:26:21 +02:00 |
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|
eyck
|
17ee7b138d
|
update generated TGC-C VM
|
2021-09-29 00:44:17 +02:00 |
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|
eyck
|
aa84a27a5b
|
fix JALR alignment in description
|
2021-09-29 00:43:42 +02:00 |
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|
eyck
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
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|
eyck
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
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|
eyck
|
ba9339a50d
|
fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
|
2021-09-21 16:52:40 +02:00 |
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|
eyck
|
65b4db5eca
|
remove mcounteren in M-mode only platform
|
2021-09-18 11:40:00 +02:00 |
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|
eyck
|
0fd82f1f3c
|
add tgc_d_xrb_mac to SC and C++ ISS
|
2021-09-04 13:04:34 +02:00 |
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|
eyck
|
a3084456fd
|
rework core definitions
|
2021-09-04 12:47:07 +02:00 |
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|
eyck
|
09b01af3fa
|
fix find_package use and debug access alignment check
|
2021-08-26 22:10:27 +02:00 |
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|
eyck
|
9c8b72693e
|
correct trap ids of access faults
|
2021-08-20 09:02:56 +02:00 |
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|
eyck
|
c409e7b7ca
|
adapt to fixed handling of SystemCPackage
|
2021-08-19 13:38:29 +02:00 |
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|
eyck
|
2f05083cf0
|
fix elf loader and pmp check for debug accesses
|
2021-08-19 10:50:25 +02:00 |
|
|
eyck
|
e934049dd4
|
fix inconsistency due to PA adaptation
|
2021-08-16 17:55:14 +02:00 |
|
 Eyck Jentzsch
|
94f796ebdb
|
add install target and PA compatibility
|
2021-08-16 17:02:31 +02:00 |
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|
eyck
|
836ba269e3
|
fix clic reset values
|
2021-08-16 15:05:05 +02:00 |
|
|
eyck
|
c8681096be
|
update vm_tgfs_c to match CoreDSL
|
2021-08-14 10:57:36 +02:00 |
|
|
eyck
|
adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
|
|
eyck
|
d95846a849
|
fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
|
|
eyck
|
af887c286f
|
fix for #2
|
2021-07-28 09:09:08 +02:00 |
|
|
eyck
|
4ddf50162c
|
make library naming consistent
|
2021-07-27 15:55:08 +02:00 |
|
|
eyck
|
da819d8890
|
fix SystemC lib handling in build system
|
2021-07-27 12:25:31 +02:00 |
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|
eyck
|
5ef5d57d30
|
Merge branch 'tmp' into develop
|
2021-07-27 10:49:35 +02:00 |
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|
eyck
|
d7bddd825c
|
add clic CSRs
|
2021-07-27 10:47:48 +02:00 |
|
|
eyck
|
15f46a87db
|
adapt core_complex to use scv-tr (scc commit id a3cde47)
|
2021-07-27 09:38:05 +02:00 |
|