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• 813b40409d Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop Eyck Jentzsch 2023-08-30 10:05:42 +0200
• c8a4a4c736 renames core(s) Eyck Jentzsch 2023-08-27 15:17:12 +0200
• 18e08cfc50 fixes missing template updates Eyck Jentzsch 2023-08-08 06:23:38 +0200
• 20e920338c removes v2p function Eyck Jentzsch 2023-08-04 13:08:10 +0200
• e151416f58 fixes systemc factory registration Eyck Jentzsch 2023-07-31 12:55:09 +0200
• 24de2bbdf5 purge build system Eyck Jentzsch 2023-07-30 13:55:57 +0200
• e68f9c573f Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop Eyck Jentzsch 2023-07-30 09:14:58 +0200
• f38cc7d8b9 updates LLVM build Eyck Jentzsch 2023-07-29 17:55:37 +0200
• 7af7e040da Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop Eyck-Alexander Jentzsch 2023-07-29 11:47:25 +0200
• 6e52af168b adds faster decoding to tcc and cleans up others Eyck-Alexander Jentzsch 2023-07-29 11:42:46 +0200
• bd0d15f3a2 updates template for faster instruction decoding Eyck-Alexander Jentzsch 2023-07-23 08:10:57 +0200
• c78026b720 adds faster instruction decoding Eyck-Alexander Jentzsch 2023-07-23 08:05:15 +0200
• edba497fa1 fixes linker isseu using whole-archive Eyck Jentzsch 2023-07-19 08:19:38 +0200
• 94e46b9968 adds some cleanup Eyck Jentzsch 2023-07-17 19:57:09 +0200
• 9459632f6c adds llvm build support incl. conan Eyck Jentzsch 2023-07-17 19:52:50 +0200
• a0ca3cdfa5 revive LLVM support (WIP) Eyck Jentzsch 2023-07-13 09:42:39 +0200
• 720236ec3f add generated core registration Eyck Jentzsch 2023-07-14 12:51:51 +0200
• 957145ca84 add SystemC ISS factory Eyck Jentzsch 2023-07-14 11:11:03 +0200
• 0b719a4b57 fixes literal type Eyck Jentzsch 2023-07-10 20:39:02 +0200
• 57da07eb17 rework sc wrapper build Eyck Jentzsch 2023-07-10 12:52:48 +0200
• b4b03f7850 fixes build system to handle TCC properly Eyck Jentzsch 2023-07-09 22:20:50 +0200
• 145a0cf68b updates registration of cores for sysc Eyck Jentzsch 2023-07-09 20:24:45 +0200
• 1cef7de8c7 fixes missing namespaces Eyck Jentzsch 2023-07-09 20:15:12 +0200
• a6c7b1427e fixes missing namespaces feature/iss_factory Eyck Jentzsch 2023-07-09 20:15:12 +0200
• e95f422aab cleans vm implementation up Eyck Jentzsch 2023-07-09 20:13:26 +0200
• 250ea3c980 extends factory to support SystemC core wrapper Eyck Jentzsch 2023-07-06 08:02:48 +0200
• 7b31b8ca8e adds updated generated files Eyck-Alexander Jentzsch 2023-07-09 16:58:47 +0200
• 91a23a4a18 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop Eyck-Alexander Jentzsch 2023-07-09 16:55:06 +0200
• 21d3250e1a changes templates Eyck-Alexander Jentzsch 2023-07-09 16:53:59 +0200
• 2b094c3162 removes trace compass nature Eyck Jentzsch 2023-07-06 10:39:59 +0200
• 2f8ee6e89d extends factory to support SystemC core wrapper feature/core_factory Eyck Jentzsch 2023-07-06 08:02:48 +0200
• a20eab0c2b Merge branch 'feature/update_coredsl' into develop Eyck Jentzsch 2023-07-05 15:15:06 +0200
• a32c83e1be fixes CLI handling of plugin paramters in ISS Eyck Jentzsch 2023-07-05 08:32:05 +0200
• 7e45a25218 adds a instr yaml for TGC Eyck Jentzsch 2023-07-05 08:28:42 +0200
• f796c24a26 prepares templates for CoreDSL 2.0.9 drop Eyck Jentzsch 2023-07-03 20:59:16 +0200
• 87b4082633 Merge branch 'tmp' into develop Eyck-Alexander Jentzsch 2023-07-03 14:22:50 +0200
• 4dbc7433a5 fixes cause CSR handling Eyck Jentzsch 2023-06-12 17:38:56 +0200
• 99a9970ddd fixes sysc compile issues Eyck Jentzsch 2023-06-12 09:58:24 +0200
• 0b5de90fb1 changes [m|u]cause rd/wr handling Eyck Jentzsch 2023-06-11 18:29:48 +0200
• 15cd36dcd4 adds fix for compressed instructions and reads Eyck-Alexander Jentzsch 2023-06-05 17:57:38 +0200
• 2281ec4144 corrects errors and adds new backend and Eyck-Alexander Jentzsch 2023-06-05 15:18:27 +0200
• 11c481cec2 adds verbosity to error Eyck-Alexander Jentzsch 2023-06-05 15:17:16 +0200
• 60d07f2eb6 changes default loglevel to info for tgc-sim Eyck Jentzsch 2023-06-01 06:55:21 +0200
• a123beb301 fixes duplicate variable declaration and templates Eyck Jentzsch 2023-05-27 10:20:49 +0200
• ee6218279e adapts to latest code gen changes Eyck Jentzsch 2023-05-25 12:52:30 +0200
• ce5b2e60b9 amends template to fix branching instructions Eyck-Alexander Jentzsch 2023-05-22 17:00:36 +0200
• c792f50427 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop Eyck-Alexander Jentzsch 2023-05-16 21:57:32 +0200
• 6ed7eafc5d adds inital version of tcc backend Eyck-Alexander Jentzsch 2023-05-16 21:51:35 +0200
• 8a5fe58d51 adds needed arch state members for TCC to tgc_c Eyck Jentzsch 2023-05-16 08:56:18 +0200
• 16cd6d5ff5 fixes core name deduction in cmake build script Eyck Jentzsch 2023-05-16 08:54:08 +0200
• ee2ded931d adds remaining register offsets Eyck-Alexander Jentzsch 2023-05-14 17:16:42 +0200
• 95ba5c901a re-introduces last_branch register Eyck Jentzsch 2023-05-14 17:00:37 +0200
• 32848ec396 fixes build system and typo in wt_cache Eyck Jentzsch 2023-05-13 16:57:01 +0200
• 6789cf4c32 fixes case of unavailable backend Eyck Jentzsch 2023-05-12 15:45:53 +0200
• 3bc4884a9d remove unneeded cmake include Eyck Jentzsch 2023-05-12 09:28:43 +0200
• fd6b738168 changes compile dependencies Eyck Jentzsch 2023-05-11 23:43:12 +0200
• afdf8fb97f adds missing namespaces Eyck Jentzsch 2023-05-11 23:11:04 +0200
• cfa7b72363 changes time handling at sockets Eyck Jentzsch 2023-05-06 19:57:29 +0200
• d330307ed5 splits bus into 2 sockets for i/dbus Eyck Jentzsch 2023-05-04 21:59:31 +0200
• 916de2a26d changes build setup to compile specific files if a core is specified Eyck Jentzsch 2023-05-04 16:08:33 +0200
• aa70d8a54a fixes CLIC to match clicinfo description in CLIC spec 11.04.2023 Eyck Jentzsch 2023-05-02 17:22:13 +0200
• b493745cd7 sets reset start time to 0 Eyck Jentzsch 2023-05-02 11:21:42 +0200
• f9e8e1d857 fixes core_complex wrt. tlm quantum and DMI Eyck Jentzsch 2023-05-02 11:13:25 +0200
• 974d64a627 adds logo to imported instance Eyck Jentzsch 2023-05-02 08:17:17 +0200
• d70489cbb8 update import script to initialize broker Eyck Jentzsch 2023-05-02 07:58:48 +0200
• d990f1cf5d fixes reading of 64bit CSR register Eyck Jentzsch 2023-05-01 22:23:35 +0200
• 1672b01e62 adds WT cache functionality as mixin Eyck Jentzsch 2023-04-27 12:20:30 +0200
• 00b0f101ac adapts to changes of instrumentation interface in dbt-rise-core Eyck Jentzsch 2023-04-22 17:04:41 +0200
• 54f75f92ea improved testbench import; added prebuild FW for testing Rocco Jonack 2023-04-24 08:44:12 -0700
• 0304aac9e5 fixed some issues in import script; added README for reference; added initial testbench script(to be improved) Rocco Jonack 2023-04-19 05:20:58 -0700
• 8ff55d7b92 updates CWR dependent core_complex definition Eyck Jentzsch 2023-04-14 19:34:41 +0200
• f626ee2684 fixes privilege wrapper for M/U to cope with 64bit Eyck Jentzsch 2023-04-05 15:38:25 +0200
• a8a2782329 adds changes from latest CoreDSL description Eyck Jentzsch 2023-04-04 16:10:12 +0200
• 98dd329833 fixes CSR access rights Eyck Jentzsch 2023-04-04 09:23:08 +0200
• 6213445bc4 fixes 64bit behavior of CSR regs Eyck Jentzsch 2023-03-27 12:04:43 +0200
• c5465bf9e2 fixes according to fixed generator Eyck Jentzsch 2023-03-26 14:44:15 +0200
• d881cb6e63 fix data width of generated code Eyck Jentzsch 2023-03-26 12:12:34 +0200
• 2e4faa4d50 fixes mstatus mask Eyck Jentzsch 2023-03-25 09:14:56 +0100
• 8e1951f298 adds 64bit mstatus Eyck Jentzsch 2023-03-23 07:47:21 +0100
• 7efa924510 fixes m/uintstatus read Eyck Jentzsch 2023-03-17 10:51:39 +0100
• febbc4fff0 fixes m/uintstatus read Eyck Jentzsch 2023-03-17 10:23:05 +0100
• 39b2788b7e implements and fixes CLIC CSR behavior Eyck Jentzsch 2023-03-17 09:09:09 +0100
• a943dd3bdf fixes wrong array size which led to unintended CSR definitions Eyck Jentzsch 2023-03-15 14:16:08 +0100
• fedbff5971 fixes xcause and u-mode clic CSRs Eyck Jentzsch 2023-03-15 12:27:39 +0100
• c2758e8321 removes mscratchcsw from CLIC feature Eyck Jentzsch 2023-03-15 09:07:00 +0100
• 8be5fe71df fixes template name typo Eyck Jentzsch 2023-03-12 07:42:09 +0100
• 3f7ce41b9d fixes CLIC mtvt register behavior Eyck Jentzsch 2023-03-11 14:03:03 +0100
• ad1cbedf00 adds back missing max irq functions Eyck Jentzsch 2023-03-11 12:47:10 +0100
• 83f54b5074 fixes CLICCFG settings Eyck Jentzsch 2023-03-11 08:48:03 +0100
• a83928fd8c fixes CSR/CLIC implementation Eyck Jentzsch 2023-03-10 20:40:21 +0100
• ec55efd322 adds generator changed files Eyck Jentzsch 2023-02-17 06:36:34 +0100
• 8c3709f92a adds generator changed files Eyck Jentzsch 2023-02-17 06:29:27 +0100
• 207dbf1071 fixes out of range access for register alias names Eyck Jentzsch 2023-02-17 06:28:30 +0100
• 62c118e501 fixes CSR to match latest fast interrupts spec Eyck Jentzsch 2023-01-20 16:21:04 +0100
• 65dca13b42 fixes WFI miss of interrupt Eyck Jentzsch 2023-01-14 17:40:21 +0100
• 3187cbdfe2 removes CONAN_PKG from build system Eyck Jentzsch 2022-12-12 02:55:44 +0100
• 8c701d55c1 adapt to latest changes in SCC Eyck Jentzsch 2022-12-05 09:15:48 +0100
• f585489ff5 fixes pin naming Eyck Jentzsch 2022-10-26 17:21:44 +0200
• 7113683ee0 moves pending interrupt check before handling trap thus saving 1 cycle Eyck Jentzsch 2022-10-15 10:47:35 +0200
• 1a0fc4bd5d fixes wrong mcounteren in M-mode only priv wrapper Eyck Jentzsch 2022-10-10 08:59:27 +0200