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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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a249aea703
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getting rid of the error: reference to 'wait' is ambiguous
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2021-06-25 13:35:42 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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8c385647dd
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remove redundant code from checked in generated sources
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2021-05-26 23:06:31 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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4b3f5a6b0c
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add missing change
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2021-05-16 16:44:30 +02:00 |
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d41e1d816a
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add factory for ISS and use it in main.cpp
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2021-05-16 16:44:14 +02:00 |
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |
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c57884caee
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small fix
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2021-05-13 16:01:04 +02:00 |
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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2f4cfb68dc
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update to latest SCC
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2021-04-07 18:56:46 +02:00 |
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7009943106
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fix wait for interrupt. Adapt for new SCC structure
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2021-04-07 17:42:08 +02:00 |
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32e4aa83b8
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use extracted variables
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2021-03-27 09:36:52 +00:00 |
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78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
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ea3ff3c0cd
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build with SCV lib
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2021-03-23 11:57:47 +01:00 |
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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51fbc34fb3
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change namespace of core complex
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2021-03-22 11:57:40 +00:00 |
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4e0f20eba0
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rework abort conditions
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2021-03-17 19:32:57 +00:00 |
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ff3fa19208
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fix RVM description bugs
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2021-03-13 10:46:41 +00:00 |
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
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a5186ff88d
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optional dependency to TGF_B_src target
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2021-03-12 11:16:24 +01:00 |
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f4ec21007b
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fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
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768716b064
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fix another missing XLEN
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2021-03-09 11:07:56 +00:00 |
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bea0dcc387
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update missing XLEN
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2021-03-09 11:03:37 +00:00 |
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a6691bcd3c
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update generated code with correct sign extension
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2021-03-09 10:21:36 +00:00 |
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40db74ce02
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remove tgf_b code generation
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2021-03-07 16:26:14 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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dae8acb8a3
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checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
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f7cec99fa6
|
adapt to changes in SCC
|
2021-03-01 21:08:18 +00:00 |
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be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
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2021-03-01 06:26:33 +00:00 |
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1668df0531
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regenerated sources and and add opcode enum to headers
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2021-02-23 08:29:31 +00:00 |
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337f1634c0
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add mssing change
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2021-02-15 18:01:46 +00:00 |
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72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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c4da47cedd
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integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
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ab554539e3
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first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
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43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
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969b408288
|
Implement MHARTID register
|
2020-09-04 15:37:21 +02:00 |
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886b8f5716
|
TGF02 is a default core
|
2020-08-31 14:20:13 +02:00 |
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9754e3953f
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Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
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8fce0c4759
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Generate TGF01 and TGF02 cores
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2020-08-20 17:29:36 +02:00 |
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71b976811b
|
add backend selection
|
2020-06-18 09:58:43 +02:00 |
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edeff7add8
|
update log macros
|
2020-06-18 07:38:56 +02:00 |
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e902936931
|
make interpreter default
|
2020-06-18 07:22:50 +02:00 |
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55450f4900
|
[WIP] update dependencies in core desc
|
2020-06-18 06:18:59 +02:00 |
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c619194465
|
[WIP] rework generator
|
2020-06-05 07:25:40 +02:00 |
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abcfb75011
|
[WIP]
|
2020-05-31 16:41:04 +02:00 |
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10797a473d
|
modernize build system and cleanup dependencies
|
2020-05-30 14:16:10 +02:00 |
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