DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

[WIP]

Browse Source
This commit is contained in:
Eyck Jentzsch
2020-05-31 16:41:04 +02:00
parent 10797a473d
commit abcfb75011
13 changed files with 2356 additions and 3079 deletions
Download Patch File Download Diff File Expand all files Collapse all files

403
src/vm/tcc/vm_mnrv32.cpp
View File

@ -364,8 +364,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -391,12 +390,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
cur_pc_val,
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -422,10 +420,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 32U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
@ -460,16 +457,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto new_pc_val = tu.add(
auto new_pc_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 32U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.l_and(
new_pc_val,
@ -753,17 +749,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -789,17 +784,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -825,17 +819,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -861,17 +854,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
32,
true), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -897,17 +889,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
32,
true), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -933,16 +924,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 8);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 8));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 15);
@ -967,16 +957,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 16);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 16));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 16);
@ -1001,16 +990,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 17);
@ -1036,12 +1024,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1068,7 +1055,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1076,8 +1063,7 @@ private:
32, false),
tu.constant(imm, 32U)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1105,14 +1091,13 @@ private:
tu.open_scope();
int32_t full_imm_val = imm;
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(full_imm_val, 32U)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1139,12 +1124,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1171,12 +1155,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1203,12 +1186,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1238,10 +1220,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1272,10 +1253,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1306,10 +1286,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1337,10 +1316,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1367,10 +1345,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1397,14 +1374,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1431,7 +1407,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1441,8 +1417,7 @@ private:
tu.load(rs2 + traits<ARCH>::X0, 0),
32, false)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1469,7 +1444,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.ext(
@ -1481,8 +1456,7 @@ private:
32,
true)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1509,10 +1483,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1539,14 +1512,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1573,14 +1545,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1607,10 +1578,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1637,10 +1607,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1664,15 +1633,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.l_or(
tu.shl(
tu.constant(pred, 32U),
tu.constant(4, 32U)),
tu.constant(succ, 32U)), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(0, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.l_or(
tu.shl(
tu.constant(pred, 32U),
tu.constant(4, 32U)),
tu.constant(succ, 32U)), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 37);
@ -1694,11 +1662,10 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(imm, 32U), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(1, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.constant(imm, 32U), 32));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1829,16 +1796,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(rs1, 32U), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(2, 64U),
FENCEtmp0_val_v);
auto FENCEtmp1_val_v = tu.assignment("FENCEtmp1_val", tu.constant(rs2, 32U), 32);
tu.trunc(tu.constant(rs1, 32U), 32));
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(3, 64U),
FENCEtmp1_val_v);
tu.trunc(tu.constant(rs2, 32U), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 45);
@ -1863,22 +1828,19 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto rs_val_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto rs_val_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto csr_val_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", rs_val_val, 32);
auto csr_val_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", csr_val_val, 32);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.trunc(rs_val_val, 32));
tu.store(csr_val_val, rd + traits<ARCH>::X0);
} else {
auto CSRtmp2_val_v = tu.assignment("CSRtmp2_val", rs_val_val, 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp2_val_v);
tu.trunc(rs_val_val, 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1904,20 +1866,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_or(
xrd_val,
xrs1_val), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_or(
xrd_val,
xrs1_val), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1943,20 +1903,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1983,17 +1941,15 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), rd + traits<ARCH>::X0);
}
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.ext(
tu.constant(zimm, 32U),
32,
true), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.ext(
tu.constant(zimm, 32U),
32,
true), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 49);
@ -2018,22 +1974,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
if(zimm != 0){
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 32U),
32,
true)), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
tu.trunc(tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 32U),
32,
true)), 32));
}
if(rd != 0){
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", res_val, 32);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2059,22 +2013,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", res_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
if(zimm != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 32U),
32,
true))), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 32U),
32,
true))), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2102,10 +2054,9 @@ private:
if(imm == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + 8 + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + 8 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 52);
@ -2130,14 +2081,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(rs1 + 8 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(uimm, 32U)), 32);
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + 8 + traits<ARCH>::X0);
false), rd + 8 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 53);
@ -2162,14 +2112,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(rs1 + 8 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + 8 + traits<ARCH>::X0, 0), 32);
tu.constant(uimm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + 8 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 54);
@ -2193,12 +2142,11 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rs1 + traits<ARCH>::X0);
tu.constant(imm, 32U)), rs1 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 55);
@ -2240,10 +2188,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(2, 32U)), 32);
tu.store(Xtmp0_val_v, 1 + traits<ARCH>::X0);
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
cur_pc_val,
@ -2279,8 +2226,7 @@ private:
if(rd == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 58);
@ -2310,8 +2256,7 @@ private:
if(imm == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 59);
@ -2334,12 +2279,11 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(2 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, 2 + traits<ARCH>::X0);
tu.constant(imm, 32U)), 2 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 60);
@ -2364,10 +2308,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 61);
@ -2392,10 +2335,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 62);
@ -2420,12 +2362,11 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(imm, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 63);
@ -2450,10 +2391,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 64);
@ -2478,10 +2418,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
@ -2506,10 +2445,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 66);
@ -2534,10 +2472,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 67);
@ -2675,10 +2612,9 @@ private:
if(rs1 == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1 + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 71);
@ -2702,14 +2638,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(uimm, 32U)), 32);
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 72);
@ -2733,8 +2668,7 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.load(rs2 + traits<ARCH>::X0, 0), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 73);
@ -2782,10 +2716,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rd + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 75);
@ -2808,10 +2741,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(2, 32U)), 32);
tu.store(Xtmp0_val_v, 1 + traits<ARCH>::X0);
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
@ -2855,14 +2787,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(uimm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);

1684
src/vm/tcc/vm_rv32gc.cpp
View File

File diff suppressed because it is too large Load Diff

671
src/vm/tcc/vm_rv32imac.cpp
View File

File diff suppressed because it is too large Load Diff

2192
src/vm/tcc/vm_rv64gc.cpp
View File

File diff suppressed because it is too large Load Diff

416
src/vm/tcc/vm_rv64i.cpp
View File

@ -332,8 +332,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 64U), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 64U), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -359,12 +358,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
cur_pc_val,
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -390,10 +388,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 64U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
@ -428,25 +425,24 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto new_pc_val = tu.add(
auto new_pc_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto align_val = tu.l_and(
tu.constant(imm, 64U)), 64);
auto align_val = tu.assignment(tu.l_and(
new_pc_val,
tu.constant(0x2, 64U));
tu.constant(0x2, 64U)), 64);
tu( " if({}) {{", tu.icmp(
ICmpInst::ICMP_NE,
align_val,
tu.constant(0, 64U)));
this->gen_raise_trap(tu, 0, 0);
tu(" } else {");
tu(" }} else {{");
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 64U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.l_and(
new_pc_val,
@ -731,17 +727,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -767,17 +762,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -803,17 +797,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -839,17 +832,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -875,17 +867,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -911,16 +902,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 8);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 8));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 15);
@ -945,16 +935,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 16);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 16));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 16);
@ -979,16 +968,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 17);
@ -1014,12 +1002,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1046,7 +1033,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1054,8 +1041,7 @@ private:
64, false),
tu.constant(imm, 64U)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1083,14 +1069,13 @@ private:
tu.open_scope();
int64_t full_imm_val = imm;
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(full_imm_val, 64U)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1117,12 +1102,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1149,12 +1133,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1181,12 +1164,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1213,10 +1195,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1243,10 +1224,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1273,10 +1253,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1303,10 +1282,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1333,10 +1311,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1363,14 +1340,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1397,7 +1373,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1407,8 +1383,7 @@ private:
tu.load(rs2 + traits<ARCH>::X0, 0),
64, false)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1435,7 +1410,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.ext(
@ -1447,8 +1422,7 @@ private:
64,
true)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1475,10 +1449,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1505,14 +1478,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1539,14 +1511,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1573,10 +1544,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1603,10 +1573,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1630,15 +1599,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.l_or(
tu.shl(
tu.constant(pred, 64U),
tu.constant(4, 64U)),
tu.constant(succ, 64U)), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(0, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.l_or(
tu.shl(
tu.constant(pred, 64U),
tu.constant(4, 64U)),
tu.constant(succ, 64U)), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 37);
@ -1660,11 +1628,10 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(imm, 64U), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(1, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.constant(imm, 64U), 64));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1795,16 +1762,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(rs1, 64U), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(2, 64U),
FENCEtmp0_val_v);
auto FENCEtmp1_val_v = tu.assignment("FENCEtmp1_val", tu.constant(rs2, 64U), 64);
tu.trunc(tu.constant(rs1, 64U), 64));
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(3, 64U),
FENCEtmp1_val_v);
tu.trunc(tu.constant(rs2, 64U), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 45);
@ -1829,22 +1794,19 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto rs_val_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto rs_val_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto csr_val_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", rs_val_val, 64);
auto csr_val_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", csr_val_val, 64);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.trunc(rs_val_val, 64));
tu.store(csr_val_val, rd + traits<ARCH>::X0);
} else {
auto CSRtmp2_val_v = tu.assignment("CSRtmp2_val", rs_val_val, 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp2_val_v);
tu.trunc(rs_val_val, 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1870,20 +1832,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_or(
xrd_val,
xrs1_val), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_or(
xrd_val,
xrs1_val), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1909,20 +1869,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1949,17 +1907,15 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), rd + traits<ARCH>::X0);
}
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.ext(
tu.constant(zimm, 64U),
64,
true), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.ext(
tu.constant(zimm, 64U),
64,
true), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 49);
@ -1984,22 +1940,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
if(zimm != 0){
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 64U),
64,
true)), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
tu.trunc(tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 64U),
64,
true)), 64));
}
if(rd != 0){
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", res_val, 64);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2025,22 +1979,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", res_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
if(zimm != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 64U),
64,
true))), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 64U),
64,
true))), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2066,17 +2018,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2102,17 +2053,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 64),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2138,16 +2088,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 64);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 54);
@ -2173,19 +2122,18 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.add(
auto res_val = tu.assignment(tu.add(
tu.ext(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
32, false),
tu.constant(imm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(imm, 32U)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2212,17 +2160,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.shl(
auto sh_val_val = tu.assignment(tu.shl(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2249,17 +2196,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.lshr(
auto sh_val_val = tu.assignment(tu.lshr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2286,17 +2232,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.ashr(
auto sh_val_val = tu.assignment(tu.ashr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2320,7 +2265,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.add(
auto res_val = tu.assignment(tu.add(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
@ -2328,12 +2273,11 @@ private:
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2357,7 +2301,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.sub(
auto res_val = tu.assignment(tu.sub(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
@ -2365,12 +2309,11 @@ private:
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2398,23 +2341,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.shl(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.shl(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2442,23 +2384,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.lshr(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.lshr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2486,23 +2427,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.ashr(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.ashr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);