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DBT-RISE-TGC
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[WIP]

This commit is contained in:
Eyck Jentzsch 2020-05-31 16:41:04 +02:00
parent 10797a473d
commit abcfb75011
13 changed files with 2356 additions and 3079 deletions
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7
CMakeLists.txt
View File

@ -61,11 +61,11 @@ set(LIB_SOURCES ${LIB_SOURCES}
endif()
# Define the library
add_library(riscv ${LIB_SOURCES})
SET(riscv -Wl,-whole-archive -lriscv -Wl,-no-whole-archive)
add_library(riscv SHARED ${LIB_SOURCES})
target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
target_include_directories(riscv PUBLIC incl ../external/elfio)
target_link_libraries(riscv PUBLIC softfloat dbt-core scc-util)
target_link_libraries(riscv PUBLIC softfloat scc-util)
target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
set_target_properties(riscv PROPERTIES
VERSION ${PROJECT_VERSION}
FRAMEWORK FALSE
@ -104,7 +104,6 @@ endif()
# Links the target exe against the libraries
target_link_libraries(riscv-sim riscv)
target_link_libraries(riscv-sim jsoncpp)
target_link_libraries(riscv-sim dbt-core)
target_link_libraries(riscv-sim external)
target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
if (Tcmalloc_FOUND)

20
gen_input/RVF.core_desc
View File

@ -10,7 +10,7 @@ InsructionSet RV32F extends RV32I{
instructions{
FLW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
args_disass:"f{rd}, {imm}(x{rs1})";
args_disass:"f{rd}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
@ -22,13 +22,13 @@ InsructionSet RV32F extends RV32I{
}
FSW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
args_disass:"f{rs2}, {imm}(x{rs1})";
args_disass:"f{rs2}, {imm}({name(rs1)])";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32}<=F[rs2]{32};
}
FMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -45,7 +45,7 @@ InsructionSet RV32F extends RV32I{
}
FMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -62,7 +62,7 @@ InsructionSet RV32F extends RV32I{
}
FNMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"name(rd), f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -79,7 +79,7 @@ InsructionSet RV32F extends RV32I{
}
FNMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -359,7 +359,7 @@ InsructionSet RV64F extends RV32F{
instructions{
FCVT.L.S { // fp to 64bit signed integer
encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
args_disass:"{name(rd)}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(0, 32), rm{8});
X[rd]<= sext(res);
val flags[32] <= fdispatch_fget_flags();
@ -367,7 +367,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.LU.S { // fp to 64bit unsigned integer
encoding: b1100000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
args_disass:"{name(rd)}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(1, 32), rm{8});
X[rd]<= zext(res);
val flags[32] <= fdispatch_fget_flags();
@ -375,7 +375,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.S.L { // 64bit signed int to to fp
encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
args_disass:"f{rd}, {name(rs1)}";
val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32), rm{8});
if(FLEN==32)
F[rd] <= res;
@ -386,7 +386,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.S.LU { // 64bit unsigned int to to fp
encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
args_disass:"f{rd}, {name(rs1)}";
val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32), rm{8});
if(FLEN==32)
F[rd] <= res;

10
gen_input/RVM.core_desc
View File

@ -2,14 +2,14 @@ import "RISCVBase.core_desc"
InsructionSet RV32M extends RISCVBase {
constants {
MAXLEN:=128
MUL_LEN
}
instructions{
MUL{
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= zext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res , XLEN);
}
}
@ -17,7 +17,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
val res[MUL_LEN] <= sext(X[rs1], MUL_LEN) * sext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -25,7 +25,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= sext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -33,7 +33,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= zext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}

3
gen_input/minres_rv.core_desc
View File

@ -22,6 +22,7 @@ Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000101;
@ -35,6 +36,7 @@ Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
XLEN:=32;
FLEN:=64;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
@ -60,6 +62,7 @@ Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
XLEN:=64;
FLEN:=64;
PCLEN:=64;
MUL_LEN:=128;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;

23
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -857,6 +857,8 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned addr, reg_t &val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto it = csr_rd_cb.find(addr);
if (it == csr_rd_cb.end()) {
val = csr[addr & csr.page_addr_mask];
@ -869,6 +871,11 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned addr, reg_t val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.machine_state < req_priv_lvl)
throw illegal_instruction_fault(this->fault_data);
if((addr&0xc00)==0xc00)
throw illegal_instruction_fault(this->fault_data);
auto it = csr_wr_cb.find(addr);
if (it == csr_wr_cb.end()) {
csr[addr & csr.page_addr_mask] = val;
@ -902,15 +909,13 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_status(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
val = state.mstatus & hart_state<reg_t>::get_mask(req_priv_lvl);
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
state.write_mstatus(val, req_priv_lvl);
check_interrupt();
update_vm_info();
@ -918,8 +923,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsig
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
val = csr[mie];
if (addr < mie) val &= csr[mideleg];
if (addr < sie) val &= csr[sideleg];
@ -927,8 +930,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned a
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
csr[mie] = (csr[mie] & ~mask) | (val & mask);
check_interrupt();
@ -936,8 +938,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
val = csr[mip];
if (addr < mip) val &= csr[mideleg];
if (addr < sip) val &= csr[sideleg];
@ -945,8 +945,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned a
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
mask &= ~(1 << 7); // MTIP is read only
csr[mip] = (csr[mip] & ~mask) | (val & mask);

2
incl/iss/arch/rv32gc.h
View File

@ -54,7 +54,7 @@ template <> struct traits<rv32gc> {
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;

2
incl/iss/arch/rv32imac.h
View File

@ -54,7 +54,7 @@ template <> struct traits<rv32imac> {
static constexpr std::array<const char*, 33> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 0;

2
incl/iss/arch/rv64gc.h
View File

@ -54,7 +54,7 @@ template <> struct traits<rv64gc> {
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=64, FLEN=64, PCLEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=64, FLEN=64, PCLEN=64, MUL_LEN=128, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;

403
src/vm/tcc/vm_mnrv32.cpp
View File

@ -364,8 +364,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -391,12 +390,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
cur_pc_val,
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -422,10 +420,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 32U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
@ -460,16 +457,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto new_pc_val = tu.add(
auto new_pc_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 32U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.l_and(
new_pc_val,
@ -753,17 +749,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -789,17 +784,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -825,17 +819,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -861,17 +854,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
32,
true), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -897,17 +889,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
tu.constant(imm, 32U)), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
32,
true), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -933,16 +924,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 8);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 8));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 15);
@ -967,16 +957,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 16);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 16));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 16);
@ -1001,16 +990,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(imm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 17);
@ -1036,12 +1024,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1068,7 +1055,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1076,8 +1063,7 @@ private:
32, false),
tu.constant(imm, 32U)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1105,14 +1091,13 @@ private:
tu.open_scope();
int32_t full_imm_val = imm;
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(full_imm_val, 32U)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1139,12 +1124,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1171,12 +1155,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1203,12 +1186,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1238,10 +1220,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1272,10 +1253,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1306,10 +1286,9 @@ private:
this->gen_raise_trap(tu, 0, 0);
} else {
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rd + traits<ARCH>::X0);
}
}
tu.close_scope();
@ -1337,10 +1316,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1367,10 +1345,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1397,14 +1374,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1431,7 +1407,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1441,8 +1417,7 @@ private:
tu.load(rs2 + traits<ARCH>::X0, 0),
32, false)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1469,7 +1444,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.ext(
@ -1481,8 +1456,7 @@ private:
32,
true)),
tu.constant(1, 32U),
tu.constant(0, 32U)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 32U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1509,10 +1483,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1539,14 +1512,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1573,14 +1545,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(32, 32U),
tu.constant(1, 32U)))), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 32U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1607,10 +1578,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1637,10 +1607,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1664,15 +1633,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.l_or(
tu.shl(
tu.constant(pred, 32U),
tu.constant(4, 32U)),
tu.constant(succ, 32U)), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(0, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.l_or(
tu.shl(
tu.constant(pred, 32U),
tu.constant(4, 32U)),
tu.constant(succ, 32U)), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 37);
@ -1694,11 +1662,10 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(imm, 32U), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(1, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.constant(imm, 32U), 32));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1829,16 +1796,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(rs1, 32U), 32);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(2, 64U),
FENCEtmp0_val_v);
auto FENCEtmp1_val_v = tu.assignment("FENCEtmp1_val", tu.constant(rs2, 32U), 32);
tu.trunc(tu.constant(rs1, 32U), 32));
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(3, 64U),
FENCEtmp1_val_v);
tu.trunc(tu.constant(rs2, 32U), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 45);
@ -1863,22 +1828,19 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto rs_val_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto rs_val_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto csr_val_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", rs_val_val, 32);
auto csr_val_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", csr_val_val, 32);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.trunc(rs_val_val, 32));
tu.store(csr_val_val, rd + traits<ARCH>::X0);
} else {
auto CSRtmp2_val_v = tu.assignment("CSRtmp2_val", rs_val_val, 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp2_val_v);
tu.trunc(rs_val_val, 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1904,20 +1866,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_or(
xrd_val,
xrs1_val), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_or(
xrd_val,
xrs1_val), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1943,20 +1903,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1983,17 +1941,15 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), rd + traits<ARCH>::X0);
}
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.ext(
tu.constant(zimm, 32U),
32,
true), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.ext(
tu.constant(zimm, 32U),
32,
true), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 49);
@ -2018,22 +1974,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
if(zimm != 0){
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 32U),
32,
true)), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
tu.trunc(tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 32U),
32,
true)), 32));
}
if(rd != 0){
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", res_val, 32);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2059,22 +2013,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 32), 32);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", res_val, 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
if(zimm != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 32U),
32,
true))), 32);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 32U),
32,
true))), 32));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2102,10 +2054,9 @@ private:
if(imm == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rd + 8 + traits<ARCH>::X0);
tu.constant(imm, 32U)), rd + 8 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 52);
@ -2130,14 +2081,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(rs1 + 8 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(uimm, 32U)), 32);
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + 8 + traits<ARCH>::X0);
false), rd + 8 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 53);
@ -2162,14 +2112,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(rs1 + 8 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + 8 + traits<ARCH>::X0, 0), 32);
tu.constant(uimm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + 8 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 54);
@ -2193,12 +2142,11 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rs1 + traits<ARCH>::X0);
tu.constant(imm, 32U)), rs1 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 55);
@ -2240,10 +2188,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(2, 32U)), 32);
tu.store(Xtmp0_val_v, 1 + traits<ARCH>::X0);
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
cur_pc_val,
@ -2279,8 +2226,7 @@ private:
if(rd == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 58);
@ -2310,8 +2256,7 @@ private:
if(imm == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 32U), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 32U), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 59);
@ -2334,12 +2279,11 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(2 + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, 2 + traits<ARCH>::X0);
tu.constant(imm, 32U)), 2 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 60);
@ -2364,10 +2308,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 61);
@ -2392,10 +2335,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 62);
@ -2420,12 +2362,11 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1_idx_val + traits<ARCH>::X0, 0),
32, false),
tu.constant(imm, 32U)), 32);
tu.store(Xtmp0_val_v, rs1_idx_val + traits<ARCH>::X0);
tu.constant(imm, 32U)), rs1_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 63);
@ -2450,10 +2391,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 64);
@ -2478,10 +2418,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
@ -2506,10 +2445,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 66);
@ -2534,10 +2472,9 @@ private:
pc=pc+2;
tu.open_scope();
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rd_idx_val + traits<ARCH>::X0, 0),
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd_idx_val + traits<ARCH>::X0);
tu.load(rs2 + 8 + traits<ARCH>::X0, 0)), rd_idx_val + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 67);
@ -2675,10 +2612,9 @@ private:
if(rs1 == 0){
this->gen_raise_trap(tu, 0, 2);
}
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 32U)), 32);
tu.store(Xtmp0_val_v, rs1 + traits<ARCH>::X0);
tu.constant(shamt, 32U)), rs1 + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 71);
@ -2702,14 +2638,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(uimm, 32U)), 32);
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
32,
false), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 72);
@ -2733,8 +2668,7 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.load(rs2 + traits<ARCH>::X0, 0), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 73);
@ -2782,10 +2716,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rd + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 32);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 75);
@ -2808,10 +2741,9 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(2, 32U)), 32);
tu.store(Xtmp0_val_v, 1 + traits<ARCH>::X0);
tu.constant(2, 32U)), 1 + traits<ARCH>::X0);
auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits<ARCH>::X0, 0), 32);
tu.store(PC_val_v, traits<ARCH>::NEXT_PC);
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32U), traits<ARCH>::LAST_BRANCH);
@ -2855,14 +2787,13 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+2;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.load(2 + traits<ARCH>::X0, 0),
tu.constant(uimm, 32U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(uimm, 32U)), 32);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);

1684
src/vm/tcc/vm_rv32gc.cpp
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671
src/vm/tcc/vm_rv32imac.cpp
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File diff suppressed because it is too large Load Diff

2192
src/vm/tcc/vm_rv64gc.cpp
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File diff suppressed because it is too large Load Diff

416
src/vm/tcc/vm_rv64i.cpp
View File

@ -332,8 +332,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.constant(imm, 64U), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.constant(imm, 64U), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -359,12 +358,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
cur_pc_val,
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -390,10 +388,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 64U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.add(
tu.ext(
@ -428,25 +425,24 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto new_pc_val = tu.add(
auto new_pc_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto align_val = tu.l_and(
tu.constant(imm, 64U)), 64);
auto align_val = tu.assignment(tu.l_and(
new_pc_val,
tu.constant(0x2, 64U));
tu.constant(0x2, 64U)), 64);
tu( " if({}) {{", tu.icmp(
ICmpInst::ICMP_NE,
align_val,
tu.constant(0, 64U)));
this->gen_raise_trap(tu, 0, 0);
tu(" } else {");
tu(" }} else {{");
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
cur_pc_val,
tu.constant(4, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(4, 64U)), rd + traits<ARCH>::X0);
}
auto PC_val_v = tu.assignment("PC_val", tu.l_and(
new_pc_val,
@ -731,17 +727,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -767,17 +762,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -803,17 +797,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -839,17 +832,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 8),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -875,17 +867,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 16),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -911,16 +902,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 8);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 8));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 15);
@ -945,16 +935,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 16);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 16));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 16);
@ -979,16 +968,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 32);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 32));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 17);
@ -1014,12 +1002,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1046,7 +1033,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1054,8 +1041,7 @@ private:
64, false),
tu.constant(imm, 64U)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1083,14 +1069,13 @@ private:
tu.open_scope();
int64_t full_imm_val = imm;
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(full_imm_val, 64U)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1117,12 +1102,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1149,12 +1133,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1181,12 +1164,11 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(imm, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1213,10 +1195,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1243,10 +1224,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1273,10 +1253,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.constant(shamt, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(shamt, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1303,10 +1282,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.add(
tu.store(tu.add(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1333,10 +1311,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.sub(
tu.store(tu.sub(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1363,14 +1340,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.shl(
tu.store(tu.shl(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1397,7 +1373,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_SLT,
tu.ext(
@ -1407,8 +1383,7 @@ private:
tu.load(rs2 + traits<ARCH>::X0, 0),
64, false)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1435,7 +1410,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.choose(
tu.store(tu.choose(
tu.icmp(
ICmpInst::ICMP_ULT,
tu.ext(
@ -1447,8 +1422,7 @@ private:
64,
true)),
tu.constant(1, 64U),
tu.constant(0, 64U)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(0, 64U)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1475,10 +1449,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_xor(
tu.store(tu.l_xor(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1505,14 +1478,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.lshr(
tu.store(tu.lshr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1539,14 +1511,13 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ashr(
tu.store(tu.ashr(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.l_and(
tu.load(rs2 + traits<ARCH>::X0, 0),
tu.sub(
tu.constant(64, 64U),
tu.constant(1, 64U)))), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.constant(1, 64U)))), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1573,10 +1544,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_or(
tu.store(tu.l_or(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1603,10 +1573,9 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.l_and(
tu.store(tu.l_and(
tu.load(rs1 + traits<ARCH>::X0, 0),
tu.load(rs2 + traits<ARCH>::X0, 0)), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.load(rs2 + traits<ARCH>::X0, 0)), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1630,15 +1599,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.l_or(
tu.shl(
tu.constant(pred, 64U),
tu.constant(4, 64U)),
tu.constant(succ, 64U)), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(0, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.l_or(
tu.shl(
tu.constant(pred, 64U),
tu.constant(4, 64U)),
tu.constant(succ, 64U)), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 37);
@ -1660,11 +1628,10 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(imm, 64U), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(1, 64U),
FENCEtmp0_val_v);
tu.trunc(tu.constant(imm, 64U), 64));
tu.close_scope();
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1795,16 +1762,14 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto FENCEtmp0_val_v = tu.assignment("FENCEtmp0_val", tu.constant(rs1, 64U), 64);
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(2, 64U),
FENCEtmp0_val_v);
auto FENCEtmp1_val_v = tu.assignment("FENCEtmp1_val", tu.constant(rs2, 64U), 64);
tu.trunc(tu.constant(rs1, 64U), 64));
tu.write_mem(
traits<ARCH>::FENCE,
tu.constant(3, 64U),
FENCEtmp1_val_v);
tu.trunc(tu.constant(rs2, 64U), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 45);
@ -1829,22 +1794,19 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto rs_val_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto rs_val_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto csr_val_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", rs_val_val, 64);
auto csr_val_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", csr_val_val, 64);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.trunc(rs_val_val, 64));
tu.store(csr_val_val, rd + traits<ARCH>::X0);
} else {
auto CSRtmp2_val_v = tu.assignment("CSRtmp2_val", rs_val_val, 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp2_val_v);
tu.trunc(rs_val_val, 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1870,20 +1832,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_or(
xrd_val,
xrs1_val), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_or(
xrd_val,
xrs1_val), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1909,20 +1869,18 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto xrd_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto xrs1_val = tu.load(rs1 + traits<ARCH>::X0, 0);
auto xrd_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
auto xrs1_val = tu.assignment(tu.load(rs1 + traits<ARCH>::X0, 0), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", xrd_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(xrd_val, rd + traits<ARCH>::X0);
}
if(rs1 != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
xrd_val,
tu.l_not(xrs1_val)), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -1949,17 +1907,15 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), rd + traits<ARCH>::X0);
}
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.ext(
tu.constant(zimm, 64U),
64,
true), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.ext(
tu.constant(zimm, 64U),
64,
true), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 49);
@ -1984,22 +1940,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
if(zimm != 0){
auto CSRtmp0_val_v = tu.assignment("CSRtmp0_val", tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 64U),
64,
true)), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp0_val_v);
tu.trunc(tu.l_or(
res_val,
tu.ext(
tu.constant(zimm, 64U),
64,
true)), 64));
}
if(rd != 0){
auto Xtmp1_val_v = tu.assignment("Xtmp1_val", res_val, 64);
tu.store(Xtmp1_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2025,22 +1979,20 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto res_val = tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64);
auto res_val = tu.assignment(tu.read_mem(traits<ARCH>::CSR, tu.constant(csr, 16U), 64), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", res_val, 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
tu.store(res_val, rd + traits<ARCH>::X0);
}
if(zimm != 0){
auto CSRtmp1_val_v = tu.assignment("CSRtmp1_val", tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 64U),
64,
true))), 64);
tu.write_mem(
traits<ARCH>::CSR,
tu.constant(csr, 16U),
CSRtmp1_val_v);
tu.trunc(tu.l_and(
res_val,
tu.l_not(tu.ext(
tu.constant(zimm, 64U),
64,
true))), 64));
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2066,17 +2018,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 32),
64,
true), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
true), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2102,17 +2053,16 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
tu.constant(imm, 64U)), 64);
if(rd != 0){
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.store(tu.ext(
tu.read_mem(traits<ARCH>::MEM, offs_val, 64),
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2138,16 +2088,15 @@ private:
auto cur_pc_val = tu.constant(pc.val, arch::traits<ARCH>::reg_bit_widths[traits<ARCH>::PC]);
pc=pc+4;
tu.open_scope();
auto offs_val = tu.add(
auto offs_val = tu.assignment(tu.add(
tu.ext(
tu.load(rs1 + traits<ARCH>::X0, 0),
64, false),
tu.constant(imm, 64U));
auto MEMtmp0_val_v = tu.assignment("MEMtmp0_val", tu.load(rs2 + traits<ARCH>::X0, 0), 64);
tu.constant(imm, 64U)), 64);
tu.write_mem(
traits<ARCH>::MEM,
offs_val,
MEMtmp0_val_v);
tu.trunc(tu.load(rs2 + traits<ARCH>::X0, 0), 64));
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
vm_base<ARCH>::gen_sync(tu, POST_SYNC, 54);
@ -2173,19 +2122,18 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.add(
auto res_val = tu.assignment(tu.add(
tu.ext(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
32, false),
tu.constant(imm, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(imm, 32U)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2212,17 +2160,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.shl(
auto sh_val_val = tu.assignment(tu.shl(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2249,17 +2196,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.lshr(
auto sh_val_val = tu.assignment(tu.lshr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2286,17 +2232,16 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto sh_val_val = tu.ashr(
auto sh_val_val = tu.assignment(tu.ashr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
tu.constant(shamt, 32U));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
tu.constant(shamt, 32U)), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2320,7 +2265,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.add(
auto res_val = tu.assignment(tu.add(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
@ -2328,12 +2273,11 @@ private:
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2357,7 +2301,7 @@ private:
pc=pc+4;
tu.open_scope();
if(rd != 0){
auto res_val = tu.sub(
auto res_val = tu.assignment(tu.sub(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
@ -2365,12 +2309,11 @@ private:
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
));
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
)), 32);
tu.store(tu.ext(
res_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2398,23 +2341,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.shl(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.shl(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2442,23 +2384,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.lshr(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.lshr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);
@ -2486,23 +2427,22 @@ private:
tu.open_scope();
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = tu.l_and(
auto count_val = tu.assignment(tu.l_and(
tu.trunc(
tu.load(rs2 + traits<ARCH>::X0, 0),
32
),
tu.constant(mask_val, 32U));
auto sh_val_val = tu.ashr(
tu.constant(mask_val, 32U)), 32);
auto sh_val_val = tu.assignment(tu.ashr(
tu.trunc(
tu.load(rs1 + traits<ARCH>::X0, 0),
32
),
count_val);
auto Xtmp0_val_v = tu.assignment("Xtmp0_val", tu.ext(
count_val), 32);
tu.store(tu.ext(
sh_val_val,
64,
false), 64);
tu.store(Xtmp0_val_v, rd + traits<ARCH>::X0);
false), rd + traits<ARCH>::X0);
}
tu.close_scope();
gen_set_pc(tu, pc, traits<ARCH>::NEXT_PC);