Implement MHARTID register
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parent
886b8f5716
commit
969b408288
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@ -43,9 +43,9 @@
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <elfio/elfio.hpp>
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#include <fmt/format.h>
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#include <iomanip>
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#include <sstream>
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#include <type_traits>
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@ -266,7 +266,7 @@ public:
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trap_store_page_fault(uint64_t badaddr)
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: trap_access(15 << 16, badaddr) {}
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};
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}
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} // namespace
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template <typename BASE> class riscv_hart_m_p : public BASE {
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public:
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@ -392,6 +392,9 @@ public:
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virtual uint64_t leave_trap(uint64_t flags) override;
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void wait_until(uint64_t flags) override;
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const reg_t& get_mhartid() const { return mhartid_reg; }
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void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
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void disass_output(uint64_t pc, const std::string instr) override {
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CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
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pc, instr, lvl[this->reg.machine_state], (reg_t)state.mstatus, this->reg.icount);
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@ -464,6 +467,9 @@ private:
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iss::status write_satp(unsigned addr, reg_t val);
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iss::status read_fcsr(unsigned addr, reg_t &val);
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iss::status write_fcsr(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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reg_t mhartid_reg{0xF};
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protected:
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void check_interrupt();
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@ -507,14 +513,7 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr_wr_cb[sie] = &riscv_hart_m_p<BASE>::write_ie;
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csr_rd_cb[uie] = &riscv_hart_m_p<BASE>::read_ie;
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csr_wr_cb[uie] = &riscv_hart_m_p<BASE>::write_ie;
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csr_rd_cb[satp] = &riscv_hart_m_p<BASE>::read_satp;
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csr_wr_cb[satp] = &riscv_hart_m_p<BASE>::write_satp;
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csr_rd_cb[fcsr] = &riscv_hart_m_p<BASE>::read_fcsr;
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csr_wr_cb[fcsr] = &riscv_hart_m_p<BASE>::write_fcsr;
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csr_rd_cb[fflags] = &riscv_hart_m_p<BASE>::read_fcsr;
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csr_wr_cb[fflags] = &riscv_hart_m_p<BASE>::write_fcsr;
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csr_rd_cb[frm] = &riscv_hart_m_p<BASE>::read_fcsr;
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csr_wr_cb[frm] = &riscv_hart_m_p<BASE>::write_fcsr;
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csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
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}
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template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
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@ -838,6 +837,11 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
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val = mhartid_reg;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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@ -1281,7 +1285,7 @@ template <typename BASE> void riscv_hart_m_p<BASE>::wait_until(uint64_t flags) {
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this->fault_data = this->reg.PC;
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}
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}
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}
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}
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} // namespace arch
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} // namespace iss
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#endif /* _RISCV_CORE_H_ */
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@ -56,7 +56,7 @@ template <typename BASE> class riscv_hart_m_p;
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namespace debugger {
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class target_adapter_if;
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}
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}
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} // namespace iss
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namespace sysc {
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@ -103,6 +103,8 @@ public:
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cci::cci_param<bool> dump_ir{"dump_ir", false};
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cci::cci_param<uint32_t> mhartid{"mhartid", 0};
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core_complex(sc_core::sc_module_name name);
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~core_complex();
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12
src/main.cpp
12
src/main.cpp
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@ -84,7 +84,7 @@ int main(int argc, char *argv[]) {
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("mem,m", po::value<std::string>(), "the memory input file")
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("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
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("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
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("isa", po::value<std::string>()->default_value("rv32gc"), "isa to use for simulation");
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("isa", po::value<std::string>()->default_value("tgf02"), "isa to use for simulation");
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// clang-format on
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auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
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try {
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@ -129,10 +129,12 @@ int main(int argc, char *argv[]) {
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vm_ptr vm{nullptr};
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cpu_ptr cpu{nullptr};
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std::string isa_opt(clim["isa"].as<std::string>());
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if (isa_opt=="tgf01") {
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std::tie(cpu, vm) = create_cpu<iss::arch::tgf01>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else if (isa_opt=="tgf02") {
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std::tie(cpu, vm) = create_cpu<iss::arch::tgf02>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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if (isa_opt == "tgf01") {
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std::tie(cpu, vm) =
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create_cpu<iss::arch::tgf01>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else if (isa_opt == "tgf02") {
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std::tie(cpu, vm) =
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create_cpu<iss::arch::tgf02>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
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} else {
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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return 127;
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@ -40,8 +40,8 @@
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#include "iss/iss.h"
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#include "iss/vm_types.h"
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#include "scc/report.h"
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#include <sstream>
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#include <iostream>
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#include <sstream>
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#ifdef WITH_SCV
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#include <array>
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@ -59,7 +59,6 @@ namespace {
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iss::debugger::encoder_decoder encdec;
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}
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//using core_type = iss::arch::rv32imac;
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using core_type = iss::arch::tgf02;
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namespace {
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@ -95,9 +94,7 @@ public:
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using base_type = arch::riscv_hart_m_p<core_type>;
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using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
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core_wrapper(core_complex *owner)
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: owner(owner)
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{
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}
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: owner(owner) { }
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uint32_t get_mode() { return this->reg.machine_state; }
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@ -288,6 +285,8 @@ vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_po
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void core_complex::before_end_of_elaboration() {
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SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
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cpu = scc::make_unique<core_wrapper>(this);
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cpu->set_mhartid(mhartid.get_value());
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vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
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#ifdef WITH_SCV
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vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
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