DBT-RISE/DBT-RISE-TGC
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Implement MHARTID register

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This commit is contained in:
Stanislaw Kaushanski
2020-09-04 15:37:21 +02:00
parent 886b8f5716
commit 969b408288
4 changed files with 30 additions and 23 deletions
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12
src/main.cpp
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@@ -84,7 +84,7 @@ int main(int argc, char *argv[]) {
("mem,m", po::value<std::string>(), "the memory input file")
("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
("isa", po::value<std::string>()->default_value("rv32gc"), "isa to use for simulation");
("isa", po::value<std::string>()->default_value("tgf02"), "isa to use for simulation");
// clang-format on
auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
try {
@@ -129,10 +129,12 @@ int main(int argc, char *argv[]) {
vm_ptr vm{nullptr};
cpu_ptr cpu{nullptr};
std::string isa_opt(clim["isa"].as<std::string>());
if (isa_opt=="tgf01") {
std::tie(cpu, vm) = create_cpu<iss::arch::tgf01>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else if (isa_opt=="tgf02") {
std::tie(cpu, vm) = create_cpu<iss::arch::tgf02>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
if (isa_opt == "tgf01") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf01>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else if (isa_opt == "tgf02") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf02>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else {
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
return 127;

9
src/sysc/core_complex.cpp
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@@ -40,8 +40,8 @@
#include "iss/iss.h"
#include "iss/vm_types.h"
#include "scc/report.h"
#include <sstream>
#include <iostream>
#include <sstream>
#ifdef WITH_SCV
#include <array>
@@ -59,7 +59,6 @@ namespace {
iss::debugger::encoder_decoder encdec;
}
//using core_type = iss::arch::rv32imac;
using core_type = iss::arch::tgf02;
namespace {
@@ -95,9 +94,7 @@ public:
using base_type = arch::riscv_hart_m_p<core_type>;
using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
core_wrapper(core_complex *owner)
: owner(owner)
{
}
: owner(owner) { }
uint32_t get_mode() { return this->reg.machine_state; }
@@ -288,6 +285,8 @@ vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_po
void core_complex::before_end_of_elaboration() {
SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
cpu = scc::make_unique<core_wrapper>(this);
cpu->set_mhartid(mhartid.get_value());
vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
#ifdef WITH_SCV
vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);