DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

update RISC-V descriptions

Browse Source
This commit is contained in:
Eyck Jentzsch
2021-02-15 18:01:33 +00:00
parent 3261055871
commit 72b09472d5
3 changed files with 24 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/vm/interp/vm_tgf_c.cpp
View File

@ -1644,7 +1644,10 @@ private:
uint8_t pred = ((bit_sub<24,4>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "fence");
auto mnemonic = fmt::format(
"{mnemonic:10} {pred}, {succ}, {rs1}, {rd}", fmt::arg("mnemonic", "fence"),
fmt::arg("pred", name(pred)), fmt::arg("succ", name(succ)), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
@ -1675,7 +1678,10 @@ private:
uint16_t imm = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "fence_i");
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", name(imm)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
@ -1873,7 +1879,10 @@ private:
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "sfence_vma");
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {rs1}", fmt::arg("mnemonic", "sfence_vma"),
fmt::arg("rs2", name(rs2)), fmt::arg("rs1", rs1));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution