DBT-RISE/DBT-RISE-TGC
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regenerated sources and and add opcode enum to headers

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This commit is contained in:
Eyck Jentzsch
2021-02-23 08:29:12 +00:00
parent d8e009c72b
commit 1668df0531
7 changed files with 960 additions and 759 deletions
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10
src/iss/tgf_b.cpp
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/tgf_b.h>
@ -39,9 +39,9 @@
using namespace iss::arch;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_names;
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
tgf_b::tgf_b() {

1328
src/vm/interp/vm_tgf_b.cpp
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File diff suppressed because it is too large Load Diff

18
src/vm/interp/vm_tgf_c.cpp
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@ -516,7 +516,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) == *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) == *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
@ -550,7 +550,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) != *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) != *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
@ -584,7 +584,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) < *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
@ -618,7 +618,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) >= *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
@ -652,7 +652,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) < *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
@ -686,7 +686,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
if(*(X+rs1) >= *(X+rs2)) *PC = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
@ -788,7 +788,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (int32_t)readSpace4(traits::MEM, *(X+rs1) + imm);
if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12);
@ -3076,7 +3076,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+(rs1 + 8)) == 0? (int8_t)*PC + imm : *PC + 2;
if(*(X+(rs1 + 8)) == 0) *PC = (int8_t)*PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
@ -3109,7 +3109,7 @@ private:
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+(rs1 + 8)) != 0? (int8_t)*PC + imm : *PC + 2;
if(*(X+(rs1 + 8)) != 0) *PC = (int8_t)*PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);