DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

update names

Browse Source
This commit is contained in:
Eyck Jentzsch
2021-05-13 15:38:33 +02:00
parent f2bf6d682a
commit cf7b62a3f9
10 changed files with 67 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/iss/.gitignore vendored
View File

@ -1 +1 @@
/tgf_b.cpp
/tgc_*.cpp

22
src/iss/tgf_c.cpp → src/iss/tgc_c.cpp
View File

@ -32,26 +32,26 @@
#include "util/ities.h"
#include <util/logging.h>
#include <iss/arch/tgf_c.h>
#include <iss/arch/tgc_c.h>
#include <cstdio>
#include <cstring>
#include <fstream>
using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 38> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
tgf_c::tgf_c() {
tgc_c::tgc_c() {
reg.icount = 0;
}
tgf_c::~tgf_c() = default;
tgc_c::~tgc_c() = default;
void tgf_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
void tgc_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.PRIV=0x3;
@ -59,11 +59,11 @@ void tgf_c::reset(uint64_t address) {
reg.icount=0;
}
uint8_t *tgf_c::get_regs_base_ptr() {
uint8_t *tgc_c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
}
tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

14
src/main.cpp
View File

@ -36,10 +36,14 @@
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_m_p.h>
#ifdef WITH_TGF_B
#include <iss/arch/tgf_b.h>
#ifdef CORE_TGC_C
#include "iss/arch/tgc_c.h"
using core_type = iss::arch::tgc_c;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/tgc_d.h"
using core_type = iss::arch::tgc_d;
#endif
#include <iss/arch/tgf_c.h>
#ifdef WITH_LLVM
#include <iss/llvm/jit_helper.h>
#endif
@ -139,7 +143,7 @@ int main(int argc, char *argv[]) {
#endif
if (isa_opt == "tgf_c") {
std::tie(cpu, vm) =
create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
create_cpu<core_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else {
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
return 127;
@ -179,7 +183,7 @@ int main(int argc, char *argv[]) {
}
uint64_t start_address = 0;
if (clim.count("mem"))
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_c>::MEM);
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<core_type>::MEM);
if (clim.count("elf"))
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
auto start_addr = vm->get_arch()->load_file(input);

10
src/sysc/core_complex.cpp
View File

@ -32,7 +32,14 @@
#include "sysc/core_complex.h"
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgf_c.h"
#ifdef CORE_TGC_C
#include "iss/arch/tgc_c.h"
using core_type = iss::arch::tgc_c;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/tgc_d.h"
using core_type = iss::arch::tgc_d;
#endif
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/server.h"
@ -59,7 +66,6 @@ namespace {
iss::debugger::encoder_decoder encdec;
}
using core_type = iss::arch::tgf_c;
namespace {

2
src/vm/interp/.gitignore vendored
View File

@ -1 +1 @@
/vm_tgf_b.cpp
/vm_tgc_*.cpp

8
src/vm/interp/vm_tgf_c.cpp → src/vm/interp/vm_tgc_c.cpp
View File

@ -31,7 +31,7 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/tgf_c.h>
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace tgf_c {
namespace tgc_c {
using namespace iss::arch;
using namespace iss::debugger;
@ -3542,8 +3542,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}