 eyck
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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
|
 stas
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a249aea703
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getting rid of the error: reference to 'wait' is ambiguous
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2021-06-25 13:35:42 +02:00 |
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eyck
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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|
eyck
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8c385647dd
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remove redundant code from checked in generated sources
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2021-05-26 23:06:31 +02:00 |
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|
eyck
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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|
eyck
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4b3f5a6b0c
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add missing change
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2021-05-16 16:44:30 +02:00 |
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eyck
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d41e1d816a
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add factory for ISS and use it in main.cpp
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2021-05-16 16:44:14 +02:00 |
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eyck
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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|
eyck
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |
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|
eyck
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c57884caee
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small fix
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2021-05-13 16:01:04 +02:00 |
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|
eyck
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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eyck
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f2bf6d682a
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fix build setup
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2021-05-13 14:03:10 +02:00 |
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eyck
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a1fa8877f7
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make core name a cmake option
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2021-05-13 09:32:38 +02:00 |
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|
eyck
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391f9bb808
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remove unneeded constants
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2021-05-08 15:14:19 +02:00 |
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stas
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ef02dba8c5
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add read misa callback
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2021-04-09 11:20:51 +02:00 |
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stas
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2f4cfb68dc
|
update to latest SCC
|
2021-04-07 18:56:46 +02:00 |
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stas
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7009943106
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fix wait for interrupt. Adapt for new SCC structure
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2021-04-07 17:42:08 +02:00 |
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|
eyck
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0a76ccbdac
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make RSP register response independend of register definition
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2021-03-31 07:48:46 +00:00 |
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eyck
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32e4aa83b8
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use extracted variables
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2021-03-27 09:36:52 +00:00 |
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|
eyck
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78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
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|
eyck
|
412a4bd9bb
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update name
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2021-03-23 17:13:32 +00:00 |
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stas
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ea3ff3c0cd
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build with SCV lib
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2021-03-23 11:57:47 +01:00 |
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|
eyck
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b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
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stas
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c941890901
|
SCC refactoring
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2021-03-22 14:50:53 +01:00 |
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|
eyck
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51fbc34fb3
|
change namespace of core complex
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2021-03-22 11:57:40 +00:00 |
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|
eyck
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4e0f20eba0
|
rework abort conditions
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2021-03-17 19:32:57 +00:00 |
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|
eyck
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ff3fa19208
|
fix RVM description bugs
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2021-03-13 10:46:41 +00:00 |
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eyck
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
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stas
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a5186ff88d
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optional dependency to TGF_B_src target
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2021-03-12 11:16:24 +01:00 |
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|
eyck
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f4ec21007b
|
fix signedness issues
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2021-03-11 16:12:28 +00:00 |
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|
eyck
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ac8eab6e25
|
update RISC-V desciptions
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2021-03-10 17:31:10 +00:00 |
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stas
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b7c0fb2b1c
|
fix bitfield structure
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2021-03-10 12:40:06 +01:00 |
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|
eyck
|
768716b064
|
fix another missing XLEN
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2021-03-09 11:07:56 +00:00 |
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|
eyck
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bea0dcc387
|
update missing XLEN
|
2021-03-09 11:03:37 +00:00 |
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|
eyck
|
a6691bcd3c
|
update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
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|
eyck
|
40db74ce02
|
remove tgf_b code generation
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2021-03-07 16:26:14 +00:00 |
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|
eyck
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c171e3c1ba
|
update CoreDSL descriptions
|
2021-03-07 10:51:15 +00:00 |
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eyck
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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|
eyck
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dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
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|
eyck
|
f7cec99fa6
|
adapt to changes in SCC
|
2021-03-01 21:08:18 +00:00 |
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|
eyck
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
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|
eyck
|
4aa26b85a0
|
adapt to change in SCC
|
2021-03-01 06:36:27 +00:00 |
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|
eyck
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
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|
eyck
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
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|
eyck
|
d8e009c72b
|
update CoreDSL decriptions
|
2021-02-15 18:15:13 +00:00 |
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|
eyck
|
d07c8679ed
|
update core definition
|
2021-02-15 18:14:52 +00:00 |
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eyck
|
3d5b61f301
|
move boost libraries from tgfs_sc to tgfs library
|
2021-02-15 18:03:39 +00:00 |
|
|
eyck
|
337f1634c0
|
add mssing change
|
2021-02-15 18:01:46 +00:00 |
|
|
eyck
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
|
eyck
|
3261055871
|
update description to latest CoreDSL2
|
2021-02-15 11:35:56 +00:00 |
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