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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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d41e1d816a
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add factory for ISS and use it in main.cpp
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2021-05-16 16:44:14 +02:00 |
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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391f9bb808
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remove unneeded constants
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2021-05-08 15:14:19 +02:00 |
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ef02dba8c5
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add read misa callback
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2021-04-09 11:20:51 +02:00 |
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2f4cfb68dc
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update to latest SCC
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2021-04-07 18:56:46 +02:00 |
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7009943106
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fix wait for interrupt. Adapt for new SCC structure
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2021-04-07 17:42:08 +02:00 |
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0a76ccbdac
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make RSP register response independend of register definition
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2021-03-31 07:48:46 +00:00 |
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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c941890901
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SCC refactoring
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2021-03-22 14:50:53 +01:00 |
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51fbc34fb3
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change namespace of core complex
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2021-03-22 11:57:40 +00:00 |
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f4ec21007b
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fix signedness issues
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2021-03-11 16:12:28 +00:00 |
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b7c0fb2b1c
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fix bitfield structure
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2021-03-10 12:40:06 +01:00 |
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40db74ce02
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remove tgf_b code generation
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2021-03-07 16:26:14 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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dae8acb8a3
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checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
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be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
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4aa26b85a0
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adapt to change in SCC
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2021-03-01 06:36:27 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
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2021-03-01 06:26:33 +00:00 |
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1668df0531
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regenerated sources and and add opcode enum to headers
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2021-02-23 08:29:31 +00:00 |
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d07c8679ed
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update core definition
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2021-02-15 18:14:52 +00:00 |
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72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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da7e29fbb7
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update definitions of derived constants
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2021-01-01 09:19:48 +00:00 |
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c4da47cedd
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integrate code generation into build process (first attempt)
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2020-12-30 07:29:52 +00:00 |
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ab554539e3
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first version of tgf_c based on CoreDSL 2.0
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2020-12-29 08:48:22 +00:00 |
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43488676dd
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Update TGF naming convention
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2020-09-11 10:45:44 +02:00 |
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f3d578f050
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Remove 64bit support
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2020-09-07 14:30:19 +02:00 |
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293c396a0d
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update core wrapper: remove virtual memory support
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2020-09-07 13:29:45 +02:00 |
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6f3963a473
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Strip down privileged modes. Only machine mode is supported
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2020-09-07 11:54:45 +02:00 |
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969b408288
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Implement MHARTID register
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2020-09-04 15:37:21 +02:00 |
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9754e3953f
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Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
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8fce0c4759
|
Generate TGF01 and TGF02 cores
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2020-08-20 17:29:36 +02:00 |
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18976e2ce4
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adapt to newer gdb protocol
|
2020-06-22 08:45:12 +02:00 |
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71b976811b
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add backend selection
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2020-06-18 09:58:43 +02:00 |
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abcfb75011
|
[WIP]
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2020-05-31 16:41:04 +02:00 |
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0ff6ccf9e2
|
get all compile clean
|
2020-05-30 11:27:44 +02:00 |
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0698b604fd
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add TCC backend
|
2020-05-29 08:52:55 +02:00 |
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264053a8d6
|
[WIP] add next increment for TCC
|
2020-04-17 19:23:43 +02:00 |
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15f4c059e6
|
[WIP] first working version
|
2020-01-12 18:19:48 +01:00 |
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e483887c43
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[WIP] Cleanup of namespaces etc to get compile clean
|
2020-01-10 11:12:20 +01:00 |
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116ed9bb5c
|
[WIP] started to add TinyCC backend
|
2020-01-09 19:43:17 +01:00 |
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d037141d98
|
Fixed C++11 compatibility
|
2019-07-16 15:52:34 +02:00 |
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1947a2114f
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Fixed FMT header define
|
2019-07-14 16:51:14 +02:00 |
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7f06bba239
|
Fixed time csr handling
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2019-06-28 20:58:02 +02:00 |
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67d9beb7bd
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reorganized layout to only contain risc-v stuff
|
2019-06-11 16:49:37 +00:00 |
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