DBT-RISE/DBT-RISE-TGC
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Fixed C++11 compatibility

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This commit is contained in:
Eyck Jentzsch 2019-07-16 15:52:34 +02:00
parent 1947a2114f
commit d037141d98
4 changed files with 9 additions and 8 deletions
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8
incl/iss/arch/riscv_hart_msu_vp.h
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@ -426,11 +426,13 @@ public:
static constexpr T get_misa() { return (2ULL << 62) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
static constexpr T get_mask(unsigned priv_lvl) {
uint64_t ret;
switch (priv_lvl) {
case PRIV_U: return 0x8000000f00000011ULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
case PRIV_S: return 0x8000000f000de133ULL; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
default: return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
case PRIV_U: ret = 0x8000000f00000011ULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
case PRIV_S: ret = 0x8000000f000de133ULL;break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
default: ret = 0x8000000f007ff9ddULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
}
return ret;
}
static inline vm_info decode_vm_info(uint32_t state, T sptbr) {

4
incl/sysc/core_complex.h
View File

@ -130,8 +130,8 @@ public:
void disass_output(uint64_t pc, const std::string instr);
protected:
void before_end_of_elaboration();
void start_of_simulation();
void before_end_of_elaboration() override;
void start_of_simulation() override;
void run();
void clk_cb();
void rst_cb();

2
src/main.cpp
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@ -101,7 +101,7 @@ int main(int argc, char *argv[]) {
auto res = 0;
try {
// application code comes here //
iss::init_jit(argc, argv);
iss::init_jit_debug(argc, argv);
bool dump = clim.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> vm{nullptr};

3
src/sysc/core_complex.cpp
View File

@ -252,7 +252,6 @@ core_complex::core_complex(sc_module_name name)
, fetch_tr_handle(nullptr)
#endif
{
initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
auto lut_entry = read_lut.getEntry(start);
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@ -282,7 +281,7 @@ core_complex::~core_complex() = default;
void core_complex::trace(sc_trace_file *trf) const {}
void core_complex::before_end_of_elaboration() {
cpu = std::make_unique<core_wrapper>(this);
cpu = scc::make_unique<core_wrapper>(this);
vm = create<arch::rv32imac>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
#ifdef WITH_SCV
vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);