Fixed C++11 compatibility
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1947a2114f
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d037141d98
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@ -426,11 +426,13 @@ public:
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static constexpr T get_misa() { return (2ULL << 62) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
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static constexpr T get_mask(unsigned priv_lvl) {
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uint64_t ret;
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switch (priv_lvl) {
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case PRIV_U: return 0x8000000f00000011ULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
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case PRIV_S: return 0x8000000f000de133ULL; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
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default: return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
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case PRIV_U: ret = 0x8000000f00000011ULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
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case PRIV_S: ret = 0x8000000f000de133ULL;break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011
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default: ret = 0x8000000f007ff9ddULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
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}
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return ret;
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}
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static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
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@ -130,8 +130,8 @@ public:
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void disass_output(uint64_t pc, const std::string instr);
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protected:
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void before_end_of_elaboration();
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void start_of_simulation();
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void before_end_of_elaboration() override;
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void start_of_simulation() override;
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void run();
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void clk_cb();
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void rst_cb();
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@ -101,7 +101,7 @@ int main(int argc, char *argv[]) {
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auto res = 0;
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try {
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// application code comes here //
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iss::init_jit(argc, argv);
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iss::init_jit_debug(argc, argv);
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bool dump = clim.count("dump-ir");
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// instantiate the simulator
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std::unique_ptr<iss::vm_if> vm{nullptr};
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@ -252,7 +252,6 @@ core_complex::core_complex(sc_module_name name)
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, fetch_tr_handle(nullptr)
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#endif
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{
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initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = read_lut.getEntry(start);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
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@ -282,7 +281,7 @@ core_complex::~core_complex() = default;
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void core_complex::trace(sc_trace_file *trf) const {}
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void core_complex::before_end_of_elaboration() {
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cpu = std::make_unique<core_wrapper>(this);
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cpu = scc::make_unique<core_wrapper>(this);
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vm = create<arch::rv32imac>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
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#ifdef WITH_SCV
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vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
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