add TCC backend
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@ -657,10 +657,12 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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const uint64_t addr, const unsigned length, uint8_t *const data) {
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#ifndef NDEBUG
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if (access && iss::access_type::DEBUG) {
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LOG(TRACE) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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} else if(access && iss::access_type::FETCH){
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LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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}
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}
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#endif
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try {
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switch (space) {
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@ -1318,7 +1320,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
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sprintf(buffer.data(), "0x%016lx", addr);
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if((flags&0xffffffff) != 0xffffffff)
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CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << trap_id << ")"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
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<< " at address " << buffer.data() << " occurred, changing privilege level from "
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<< lvl[cur_priv] << " to " << lvl[new_priv];
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update_vm_info();
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