[WIP] add next increment for TCC
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ae1c0b99fe
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264053a8d6
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@ -172,6 +172,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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inline bool should_stop() { return interrupt_sim; }
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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@ -204,7 +206,7 @@ protected:
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std::array<address_type, 4> addr_mode;
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bool interrupt_sim=false;
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uint64_t interrupt_sim=0;
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<%
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def fcsr = allRegs.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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@ -60,7 +60,7 @@ public:
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using ICmpInst = typename super::ICmpInst;
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using tu_builder = typename super::tu_builder;
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vm_impl();
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@ -77,11 +77,10 @@ public:
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using translation_unit = typename vm_base<ARCH>::translation_unit;
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = std::tuple<continuation_e>;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, translation_unit&);
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
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inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
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@ -89,34 +88,34 @@ protected:
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super::setup_module(m);
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}
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compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, translation_unit&) override;
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compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
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void gen_trap_behavior(translation_unit& tu) override;
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void gen_trap_behavior(tu_builder& tu) override;
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void gen_raise_trap(translation_unit& tu, uint16_t trap_id, uint16_t cause);
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void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(translation_unit& tu, unsigned lvl);
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void gen_leave_trap(tu_builder& tu, unsigned lvl);
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void gen_wait(translation_unit& tu, unsigned type);
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void gen_wait(tu_builder& tu, unsigned type);
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inline void gen_trap_check(translation_unit& tu) {
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tu<<" if(*trap_state!=0) goto trap_entry;";
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inline void gen_trap_check(tu_builder& tu) {
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tu("if(*trap_state!=0) goto trap_entry;");
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}
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inline void gen_set_pc(translation_unit& tu, virt_addr_t pc, unsigned reg_num) {
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inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
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switch(reg_num){
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case traits<ARCH>::NEXT_PC:
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tu(" *next_pc = {:#x};", pc.val);
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tu("*next_pc = {:#x};", pc.val);
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break;
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case traits<ARCH>::PC:
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tu(" *pc = {:#x};", pc.val);
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tu("*pc = {:#x};", pc.val);
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break;
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default:
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if(!tu.defined_regs[reg_num]){
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tu(" reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
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tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
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tu.defined_regs[reg_num]=true;
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}
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tu(" *reg{:02d} = {:#x};", reg_num, pc.val);
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tu("*reg{:02d} = {:#x};", reg_num, pc.val);
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}
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}
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@ -191,14 +190,14 @@ private:
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, translation_unit& tu){<%instr.code.eachLine{%>
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
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${it}<%}%>
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, translation_unit& tu) {
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
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vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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gen_raise_trap(tu, 0, 2); // illegal instruction trap
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@ -230,7 +229,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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template <typename ARCH>
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std::tuple<continuation_e>
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, translation_unit& tu) {
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
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// we fetch at max 4 byte, alignment is 2
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enum {TRAP_ID=1<<16};
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code_word_t insn = 0;
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@ -259,24 +258,25 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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return (this->*f)(pc, insn, tu);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(translation_unit& tu, uint16_t trap_id, uint16_t cause) {
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
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tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
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tu << tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(translation_unit& tu, unsigned lvl) {
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tu(" leave_trap(core_ptr, {});", lvl);
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tu(" *next_pc = {};", tu.create_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8));
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tu << tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
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tu("leave_trap(core_ptr, {});", lvl);
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tu.create_store(tu.create_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8),traits<ARCH>::NEXT_PC);
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(translation_unit& tu, unsigned type) {
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(translation_unit& tu) {
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tu<<"trap_entry:";
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tu(" enter_trap(core_ptr, *trap_state, *pc);");
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tu(" return *next_pc;");
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu("trap_entry:");
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tu("enter_trap(core_ptr, *trap_state, *pc);");
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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tu("return *next_pc;");
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}
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} // namespace mnrv32
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@ -182,6 +182,8 @@ struct mnrv32: public arch_if {
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inline bool should_stop() { return interrupt_sim; }
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<mnrv32>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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@ -238,7 +240,7 @@ protected:
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std::array<address_type, 4> addr_mode;
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bool interrupt_sim=false;
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uint64_t interrupt_sim=0;
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uint32_t get_fcsr(){return 0;}
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void set_fcsr(uint32_t val){}
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@ -1082,7 +1082,10 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
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LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
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<< "), stopping simulation";
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}
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throw(iss::simulation_stopped(hostvar));
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this->reg.trap_state=std::numeric_limits<uint32_t>::max();
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this->interrupt_sim=hostvar;
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break;
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//throw(iss::simulation_stopped(hostvar));
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case 0x0101: {
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char c = static_cast<char>(hostvar & 0xff);
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if (c == '\n' || c == 0) {
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@ -1313,6 +1316,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
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this->reg.trap_state = 0;
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std::array<char, 32> buffer;
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sprintf(buffer.data(), "0x%016lx", addr);
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if((flags&0xffffffff) != 0xffffffff)
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CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << trap_id << ")"
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<< " at address " << buffer.data() << " occurred, changing privilege level from "
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@ -102,7 +102,7 @@ public:
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uint32_t get_mode() { return this->reg.machine_state; }
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inline void set_interrupt_execution(bool v) { this->interrupt_sim = v; }
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inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
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inline bool get_interrupt_execution() { return this->interrupt_sim; }
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