add TCC backend
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264053a8d6
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@ -260,13 +260,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
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tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
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tu("leave_trap(core_ptr, {});", lvl);
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tu.create_store(tu.create_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8),traits<ARCH>::NEXT_PC);
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
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@ -275,7 +275,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu("trap_entry:");
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tu("enter_trap(core_ptr, *trap_state, *pc);");
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tu.create_store(tu.gen_const(32, std::numeric_limits<uint32_t>::max()),traits<ARCH>::LAST_BRANCH);
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tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
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tu("return *next_pc;");
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}
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@ -657,10 +657,12 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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const uint64_t addr, const unsigned length, uint8_t *const data) {
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#ifndef NDEBUG
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if (access && iss::access_type::DEBUG) {
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LOG(TRACE) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
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} else if(access && iss::access_type::FETCH){
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LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
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}
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}
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#endif
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try {
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switch (space) {
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@ -1318,7 +1320,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
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sprintf(buffer.data(), "0x%016lx", addr);
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if((flags&0xffffffff) != 0xffffffff)
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CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << trap_id << ")"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
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<< " at address " << buffer.data() << " occurred, changing privilege level from "
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<< lvl[cur_priv] << " to " << lvl[new_priv];
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update_vm_info();
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14
src/main.cpp
14
src/main.cpp
@ -63,6 +63,7 @@ int main(int argc, char *argv[]) {
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("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
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("mem,m", po::value<std::string>(), "the memory input file")
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("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
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("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
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("isa", po::value<std::string>()->default_value("rv32gc"), "isa to use for simulation");
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// clang-format on
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auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
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@ -82,6 +83,8 @@ int main(int argc, char *argv[]) {
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}
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std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
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LOGGER(DEFAULT)::print_time() = false;
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LOGGER(connection)::print_time() = false;
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if (clim.count("verbose")) {
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auto l = logging::as_log_level(clim["verbose"].as<int>());
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LOGGER(DEFAULT)::reporting_level() = l;
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@ -105,9 +108,12 @@ int main(int argc, char *argv[]) {
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std::unique_ptr<iss::arch_if> cpu{nullptr};
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std::string isa_opt(clim["isa"].as<std::string>());
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iss::arch::mnrv32* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::mnrv32>();
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//vm = iss::interp::create(lcpu, clim["gdb-port"].as<unsigned>());
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//vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
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vm = iss::tcc::create(lcpu, clim["gdb-port"].as<unsigned>());
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if(clim["backend"].as<std::string>() == "interp")
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vm = iss::interp::create(lcpu, clim["gdb-port"].as<unsigned>());
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if(clim["backend"].as<std::string>() == "llvm")
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vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
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if(clim["backend"].as<std::string>() == "tcc")
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vm = iss::tcc::create(lcpu, clim["gdb-port"].as<unsigned>());
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cpu.reset(lcpu);
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if (clim.count("plugin")) {
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for (std::string opt_val : clim["plugin"].as<std::vector<std::string>>()) {
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@ -135,10 +141,10 @@ int main(int argc, char *argv[]) {
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if (clim.count("disass")) {
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vm->setDisassEnabled(true);
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LOGGER(disass)::reporting_level() = logging::INFO;
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LOGGER(disass)::print_time() = false;
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auto file_name = clim["disass"].as<std::string>();
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if (file_name.length() > 0) {
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LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
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LOGGER(disass)::print_time() = false;
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LOGGER(disass)::print_severity() = false;
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}
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}
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