regenerated sources and and add opcode enum to headers
This commit is contained in:
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,7 +30,6 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_B_H_
|
||||
#define _TGF_B_H_
|
||||
|
||||
@ -46,15 +45,15 @@ struct tgf_b;
|
||||
|
||||
template <> struct traits<tgf_b> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_B";
|
||||
constexpr static char const* const core_type = "TGF_B";
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
static constexpr std::array<const char*, 35> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
@ -92,45 +91,14 @@ template <> struct traits<tgf_b> {
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
PRIV,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
ICOUNT
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
@ -143,17 +111,73 @@ template <> struct traits<tgf_b> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
static constexpr std::array<const uint32_t, 40> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
FENCE_I = 38,
|
||||
ECALL = 39,
|
||||
EBREAK = 40,
|
||||
URET = 41,
|
||||
SRET = 42,
|
||||
MRET = 43,
|
||||
WFI = 44,
|
||||
SFENCE_VMA = 45,
|
||||
CSRRW = 46,
|
||||
CSRRS = 47,
|
||||
CSRRC = 48,
|
||||
CSRRWI = 49,
|
||||
CSRRSI = 50,
|
||||
CSRRCI = 51,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgf_b: public arch_if {
|
||||
@ -199,40 +223,41 @@ struct tgf_b: public arch_if {
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct TGF_B_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
struct TGF_B_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint8_t PRIV = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
@ -242,8 +267,8 @@ protected:
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -45,13 +45,13 @@ struct tgf_c;
|
||||
|
||||
template <> struct traits<tgf_c> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_C";
|
||||
constexpr static char const* const core_type = "TGF_C";
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
static constexpr std::array<const char*, 35> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
||||
|
||||
@ -111,17 +111,109 @@ template <> struct traits<tgf_c> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
|
||||
static constexpr std::array<const uint32_t, 40> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
FENCE_I = 38,
|
||||
ECALL = 39,
|
||||
EBREAK = 40,
|
||||
URET = 41,
|
||||
SRET = 42,
|
||||
MRET = 43,
|
||||
WFI = 44,
|
||||
SFENCE_VMA = 45,
|
||||
CSRRW = 46,
|
||||
CSRRS = 47,
|
||||
CSRRC = 48,
|
||||
CSRRWI = 49,
|
||||
CSRRSI = 50,
|
||||
CSRRCI = 51,
|
||||
MUL = 52,
|
||||
MULH = 53,
|
||||
MULHSU = 54,
|
||||
MULHU = 55,
|
||||
DIV = 56,
|
||||
DIVU = 57,
|
||||
REM = 58,
|
||||
REMU = 59,
|
||||
CADDI4SPN = 60,
|
||||
CLW = 61,
|
||||
CSW = 62,
|
||||
CADDI = 63,
|
||||
CNOP = 64,
|
||||
CJAL = 65,
|
||||
CLI = 66,
|
||||
CLUI = 67,
|
||||
CADDI16SP = 68,
|
||||
CSRLI = 69,
|
||||
CSRAI = 70,
|
||||
CANDI = 71,
|
||||
CSUB = 72,
|
||||
CXOR = 73,
|
||||
COR = 74,
|
||||
CAND = 75,
|
||||
CJ = 76,
|
||||
CBEQZ = 77,
|
||||
CBNEZ = 78,
|
||||
CSLLI = 79,
|
||||
CLWSP = 80,
|
||||
CMV = 81,
|
||||
CJR = 82,
|
||||
CADD = 83,
|
||||
CJALR = 84,
|
||||
CEBREAK = 85,
|
||||
CSWSP = 86,
|
||||
DII = 87,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgf_c: public arch_if {
|
||||
@ -211,8 +303,8 @@ protected:
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user