adapt to newer gdb protocol
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@ -6,7 +6,7 @@ import "RVC.core_desc"
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import "RVF.core_desc"
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import "RVD.core_desc"
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/*
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Core MNRV32 provides RV32I, RV32IC {
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constants {
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XLEN:=32;
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@ -57,7 +57,7 @@ Core RV64I provides RV64I {
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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*/
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Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
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constants {
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XLEN:=64;
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@ -184,33 +184,28 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
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avail.clear();
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const uint8_t *reg_base = core->get_regs_base_ptr();
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for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for (size_t j = 0; j < reg_width; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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// if(arch::traits<ARCH>::XLEN < 64)
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// for(unsigned j=0; j<4; ++j){
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// data.push_back(0);
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// avail.push_back(0xff);
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// }
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}
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// work around fill with F type registers
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if (arch::traits<ARCH>::NUM_REGS < 65) {
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auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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for (size_t j = 0; j < reg_width; ++j) {
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data.push_back(0x0);
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avail.push_back(0x00);
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}
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// if(arch::traits<ARCH>::XLEN < 64)
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// for(unsigned j=0; j<4; ++j){
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// data.push_back(0x0);
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// avail.push_back(0x00);
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// }
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}
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}
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// if (arch::traits<ARCH>::NUM_REGS < 65) {
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// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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// for (size_t j = 0; j < reg_width; ++j) {
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// data.push_back(0x0);
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// avail.push_back(0x00);
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// }
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// // if(arch::traits<ARCH>::XLEN < 64)
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// // for(unsigned j=0; j<4; ++j){
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// // data.push_back(0x0);
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// // avail.push_back(0x00);
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// // }
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// }
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// }
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return Ok;
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}
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